128 lines
3.8 KiB
Plaintext
128 lines
3.8 KiB
Plaintext
############################################################################
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# arch/xtensa/src/esp32s3/Make.defs
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#
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# Licensed to the Apache Software Foundation (ASF) under one or more
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# contributor license agreements. See the NOTICE file distributed with
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# this work for additional information regarding copyright ownership. The
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# ASF licenses this file to you under the Apache License, Version 2.0 (the
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# "License"); you may not use this file except in compliance with the
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# License. You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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# License for the specific language governing permissions and limitations
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# under the License.
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#
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############################################################################
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include chip/Bootloader.mk
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# The start-up, "head", file. May be either a .S or a .c file.
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HEAD_ASRC = xtensa_vectors.S xtensa_window_vector.S xtensa_windowspill.S
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HEAD_ASRC += xtensa_int_handlers.S xtensa_user_handler.S
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HEAD_CSRC = esp32s3_start.c
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# Common XTENSA files (arch/xtensa/src/common)
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CMN_ASRCS = xtensa_context.S xtensa_coproc.S xtensa_cpuint.S xtensa_panic.S
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CMN_ASRCS += xtensa_sigtramp.S
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CMN_CSRCS = xtensa_assert.c xtensa_blocktask.c xtensa_copystate.c
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CMN_CSRCS += xtensa_cpenable.c xtensa_createstack.c xtensa_exit.c
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CMN_CSRCS += xtensa_initialize.c xtensa_initialstate.c xtensa_interruptcontext.c
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CMN_CSRCS += xtensa_irqdispatch.c xtensa_lowputs.c xtensa_mdelay.c
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CMN_CSRCS += xtensa_modifyreg8.c xtensa_modifyreg16.c xtensa_modifyreg32.c
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CMN_CSRCS += xtensa_puts.c xtensa_releasepending.c xtensa_releasestack.c
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CMN_CSRCS += xtensa_reprioritizertr.c xtensa_schedsigaction.c
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CMN_CSRCS += xtensa_sigdeliver.c xtensa_stackframe.c xtensa_udelay.c
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CMN_CSRCS += xtensa_unblocktask.c xtensa_usestack.c xtensa_swint.c
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CMN_CSRCS += xtensa_switchcontext.c
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# Configuration-dependent common XTENSA files
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ifeq ($(CONFIG_DEBUG_ALERT),y)
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CMN_CSRCS += xtensa_dumpstate.c
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endif
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ifeq ($(CONFIG_SPINLOCK),y)
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CMN_CSRCS += xtensa_testset.c
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endif
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ifeq ($(CONFIG_SMP),y)
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CMN_CSRCS += xtensa_cpupause.c
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endif
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ifeq ($(CONFIG_STACK_COLORATION),y)
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CMN_CSRCS += xtensa_checkstack.c
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endif
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ifeq ($(CONFIG_XTENSA_SEMIHOSTING_HOSTFS),y)
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CMN_ASRCS += xtensa_simcall.S
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CMN_CSRCS += xtensa_hostfs.c
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endif
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# Required ESP32-S3 files (arch/xtensa/src/esp32s3)
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CHIP_CSRCS = esp32s3_irq.c esp32s3_clockconfig.c esp32s3_region.c
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CHIP_CSRCS += esp32s3_systemreset.c esp32s3_user.c esp32s3_allocateheap.c
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CHIP_CSRCS += esp32s3_wdt.c esp32s3_gpio.c esp32s3_lowputc.c esp32s3_serial.c
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# Configuration-dependent ESP32-S3 files
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ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
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CHIP_CSRCS += esp32s3_idle.c
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endif
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ifeq ($(CONFIG_SMP),y)
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CHIP_ASRCS = esp32s3_cpuindex.S
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CHIP_CSRCS += esp32s3_cpuidlestack.c esp32s3_cpustart.c esp32s3_intercpu_interrupt.c
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endif
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ifeq ($(CONFIG_SCHED_TICKLESS),y)
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CHIP_CSRCS += esp32s3_tickless.c
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else
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CHIP_CSRCS += esp32s3_timerisr.c
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endif
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ifeq ($(CONFIG_ESP32S3_TIMER),y)
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CHIP_CSRCS += esp32s3_tim.c
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ifeq ($(CONFIG_TIMER),y)
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CHIP_CSRCS += esp32s3_tim_lowerhalf.c
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endif
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endif
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ifeq ($(CONFIG_WATCHDOG),y)
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CHIP_CSRCS += esp32s3_wdt_lowerhalf.c
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endif
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ifeq ($(CONFIG_ESP32S3_ONESHOT),y)
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CHIP_CSRCS += esp32s3_oneshot.c
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ifeq ($(CONFIG_ONESHOT),y)
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CHIP_CSRCS += esp32s3_oneshot_lowerhalf.c
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endif
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endif
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ifeq ($(CONFIG_ESP32S3_FREERUN),y)
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CHIP_CSRCS += esp32s3_freerun.c
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endif
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ifeq ($(CONFIG_ESP32S3_RT_TIMER),y)
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CHIP_CSRCS += esp32s3_rt_timer.c
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endif
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ifeq ($(CONFIG_ESP32S3_SPIFLASH),y)
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CHIP_CSRCS += esp32s3_spiflash.c
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ifeq ($(CONFIG_ESP32S3_MTD),y)
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CHIP_CSRCS += esp32s3_spiflash_mtd.c
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endif
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endif
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ifeq ($(CONFIG_ESP32S3_SPIRAM),y)
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CHIP_CSRCS += esp32s3_spiram.c
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CHIP_CSRCS += esp32s3_psram.c
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endif
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