Gustavo Henrique Nihei
7ede285cfe
xtensa/esp32s3: Add support for RT-Timer based on Systimer peripheral
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Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-03-12 15:27:30 +02:00
Alan C. Assis
dc1b6776b9
xtensa/esp32s3: Add SPI RAM/PSRAM Support
2022-03-09 19:22:56 +02:00
Gustavo Henrique Nihei
4a29fa903b
xtensa/esp32s3: Enable SMP support
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Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-03-09 10:42:50 +08:00
Abdelatif Guettouche
9d5b13cd0e
xtensa/esp32s3: Add SPI-Flash support.
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Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-03-03 19:57:59 +08:00
Gustavo Henrique Nihei
16030f713e
xtensa/esp32s3: Add support for Free-running Timer
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Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-03-03 10:58:53 +08:00
Gustavo Henrique Nihei
3b7a6ae311
xtensa/esp32s3: Add support for Tickless kernel using Systimer
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Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-03-02 18:08:44 +01:00
zhuyanlin
fbc1da98b7
xtensa: use swint to swith context
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Reason for use sw-interrupt as syscall interrupt:
The xtensa `syscall` instruction can cause SYSCALL interrupt.
But SYSCALL interrupt is same interrupt level with level-one
interrupt.
Nuttx swint can enter `enter_critical_section` and gerenate
interrupt.
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-02-25 20:43:03 +08:00
Gustavo Henrique Nihei
add99fead3
xtensa/esp32s3: Add support for Oneshot timer
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Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-02-25 10:51:25 +08:00
Gustavo Henrique Nihei
b49ee3d4ed
xtensa/esp32s3: Add support for Main System Watchdog Timers
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Support for RTC Watchdog Timer is currently in place, but not yet
functional due to not yet implemented RTC driver.
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-02-25 02:13:00 +08:00
Gustavo Henrique Nihei
83f3ba6d22
xtensa/esp32s3: Add support for Timer Groups 0 and 1
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Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-02-25 00:13:34 +08:00
zhuyanlin
fc9791c269
xtensa:esp32s3: setup software interrupt as swi interrupt.
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Enable and setup software interrupt.
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-02-24 00:06:43 +01:00
Gustavo Henrique Nihei
b0d24f53c4
xtensa: Add initial support for ESP32-S3
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Co-authored-by: Alan Carvalho de Assis <alan.carvalho@espressif.com>
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-01-27 13:46:50 -03:00