5cdd038df2
Squashed commit of the following:
arch/arm: Rename include/stm32f0l0 and src/stm32f0l0 to stm32f0l0g0.
Change all occurrences of lower-case stm32f0l0 to stm32f0l0g0.
Change all occurrences of upper-case STM32F0L0 to STM32F0L0G0.
133 lines
7.3 KiB
C
133 lines
7.3 KiB
C
/****************************************************************************************************
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* arch/arm/include/stm32f0l0g0/stm32l0_irq.h
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Author: Mateusz Szafoni <raiden00@railab.me>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************************/
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/* This file should never be included directed but, rather, only indirectly through nuttx/irq.h */
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#ifndef __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32L0_IRQ_H
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#define __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32L0_IRQ_H
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/****************************************************************************************************
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* Included Files
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****************************************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/irq.h>
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#include <arch/stm32f0l0g0/chip.h>
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/****************************************************************************************************
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* Pre-processor Definitions
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****************************************************************************************************/
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/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to
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* bits in the NVIC. This does, however, waste several words of memory in the IRQ
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* to handle mapping tables.
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*
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* Processor Exceptions (vectors 0-15). These common definitions can be found
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* in nuttx/arch/arm/include/stm32f0l0g0/irq.h
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*/
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#define STM32_IRQ_WWDG (STM32_IRQ_EXTINT + 0) /* 0: Window Watchdog interrupt */
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#define STM32_IRQ_PVD (STM32_IRQ_EXTINT + 1) /* 1: PVD through EXTI Line detection interrupt */
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#define STM32_IRQ_RTC (STM32_IRQ_EXTINT + 2) /* 2: RTC global interrupt */
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#define STM32_IRQ_FLASH (STM32_IRQ_EXTINT + 3) /* 3: Flash global interrupt */
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#define STM32_IRQ_RCC_CRS (STM32_IRQ_EXTINT + 4) /* 4: RCC and CRS global interrupt */
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#define STM32_IRQ_EXTI0_1 (STM32_IRQ_EXTINT + 5) /* 5: EXTI Line 0-1 interrupt */
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#define STM32_IRQ_EXTI2_3 (STM32_IRQ_EXTINT + 6) /* 6: EXTI Line 2-3 interrupt */
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#define STM32_IRQ_EXTI4_15 (STM32_IRQ_EXTINT + 7) /* 7: EXTI Line 4-15 interrupt */
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#define STM32_IRQ_TSC (STM32_IRQ_EXTINT + 8) /* 8: TSC global interrupt */
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#define STM32_IRQ_DMA1CH1 (STM32_IRQ_EXTINT + 9) /* 9: DMA1 channel 1 global interrupt */
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#define STM32_IRQ_DMA1CH2 (STM32_IRQ_EXTINT + 10) /* 10: DMA1 channel 2 global interrupt */
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#define STM32_IRQ_DMA1CH3 (STM32_IRQ_EXTINT + 10) /* 10: DMA1 channel 3 global interrupt */
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#define STM32_IRQ_DMA1CH4 (STM32_IRQ_EXTINT + 11) /* 11: DMA1 channel 4 global interrupt */
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#define STM32_IRQ_DMA1CH5 (STM32_IRQ_EXTINT + 11) /* 11: DMA1 channel 5 global interrupt */
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#define STM32_IRQ_DMA1CH6 (STM32_IRQ_EXTINT + 11) /* 11: DMA1 channel 6 global interrupt */
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#define STM32_IRQ_DMA1CH7 (STM32_IRQ_EXTINT + 11) /* 11: DMA1 channel 7 global interrupt */
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#define STM32_IRQ_ADC (STM32_IRQ_EXTINT + 12) /* 12: ADC global interrupt */
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#define STM32_IRQ_COMP (STM32_IRQ_EXTINT + 12) /* 12: COMP global interrupt */
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#define STM32_IRQ_LPTIM1 (STM32_IRQ_EXTINT + 13) /* 13: LPTIM1 global interrupt */
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#define STM32_IRQ_USART4 (STM32_IRQ_EXTINT + 14) /* 14: USART4 global interrupt */
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#define STM32_IRQ_USART5 (STM32_IRQ_EXTINT + 14) /* 14: USART5 global interrupt */
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#define STM32_IRQ_TIM2 (STM32_IRQ_EXTINT + 15) /* 15: TIM2 global interrupt */
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#define STM32_IRQ_TIM3 (STM32_IRQ_EXTINT + 16) /* 16: TIM3 global interrupt */
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#define STM32_IRQ_TIM6 (STM32_IRQ_EXTINT + 17) /* 17: TIM6 global interrupt */
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#define STM32_IRQ_DAC1 (STM32_IRQ_EXTINT + 17) /* 17: DAC1 global interrupts */
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#define STM32_IRQ_TIM7 (STM32_IRQ_EXTINT + 18) /* 18: TIM7 global interrupt */
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#define STM32_IRQ_RESERVED18 (STM32_IRQ_EXTINT + 18) /* 19: Reserved */
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#define STM32_IRQ_TIM21 (STM32_IRQ_EXTINT + 20) /* 20: TIM21 global interrupt */
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#define STM32_IRQ_I2C3 (STM32_IRQ_EXTINT + 21) /* 21: I2C3 global interrupt */
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#define STM32_IRQ_TIM22 (STM32_IRQ_EXTINT + 22) /* 22: TIM22 global interrupt */
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#define STM32_IRQ_I2C1 (STM32_IRQ_EXTINT + 23) /* 23: I2C1 global interrupt */
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#define STM32_IRQ_I2C2 (STM32_IRQ_EXTINT + 24) /* 24: I2C2 global interrupt */
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#define STM32_IRQ_SPI1 (STM32_IRQ_EXTINT + 25) /* 25: SPI1 global interrupt */
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#define STM32_IRQ_SPI2 (STM32_IRQ_EXTINT + 26) /* 26: SPI2 global interrupt */
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#define STM32_IRQ_USART1 (STM32_IRQ_EXTINT + 27) /* 27: USART1 global interrupt */
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#define STM32_IRQ_USART2 (STM32_IRQ_EXTINT + 28) /* 28: USART2 global interrupt */
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#define STM32_IRQ_LPUART1 (STM32_IRQ_EXTINT + 29) /* 29: LPUART1 global interrupt */
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#define STM32_IRQ_AES (STM32_IRQ_EXTINT + 29) /* 29: AES global interrupt */
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#define STM32_IRQ_RNG (STM32_IRQ_EXTINT + 29) /* 29: RNG gloabl interrupt */
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#define STM32_IRQ_LCD (STM32_IRQ_EXTINT + 30) /* 30: LCD global interrupt */
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#define STM32_IRQ_USB (STM32_IRQ_EXTINT + 31) /* 31: USB global interrupt */
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#define STM32_IRQ_NEXTINT (32)
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/****************************************************************************************************
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* Public Types
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****************************************************************************************************/
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/****************************************************************************************************
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* Public Data
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****************************************************************************************************/
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************************************
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* Public Functions
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****************************************************************************************************/
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif
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#endif /* __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32L0_IRQ_H */
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