319 lines
17 KiB
C
319 lines
17 KiB
C
/************************************************************************************
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* arch/arm/src/sama5/sama5d4x_periphclks.h
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*
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* Copyright (C) 2014 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAMA5_SAMAD54X_PERIPHCLKS_H
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#define __ARCH_ARM_SRC_SAMA5_SAMAD54X_PERIPHCLKS_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <arch/irq.h>
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#include "chip/sam_pmc.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Helper macros */
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#define sam_enableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCER0)
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#define sam_enableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PCER1)
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#define sam_disableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCDR0)
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#define sam_disableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PCDR1)
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#define sam_isenabled0(s) (getreg32(SAM_PMC_PCER0) & (1 << (s)) != 0)
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#define sam_isenabled1(s) (getreg32(SAM_PMC_PCER1) & (1 << ((s) - 32)) != 0)
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/* Enable peripheral clocking */
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#define sam_arm_enableclk() sam_enableperiph0(SAM_PID_ARM)
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#define sam_pit_enableclk() sam_enableperiph0(SAM_PID_PIT)
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#define sam_wdt_enableclk() sam_enableperiph0(SAM_PID_WDT)
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#define sam_piod_enableclk() sam_enableperiph0(SAM_PID_PIOD)
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#define sam_usart0_enableclk() sam_enableperiph0(SAM_PID_USART0)
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#define sam_usart1_enableclk() sam_enableperiph0(SAM_PID_USART1)
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#define sam_xdmac0_enableclk() sam_enableperiph0(SAM_PID_XDMAC0)
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#define sam_icm_enableclk() sam_enableperiph0(SAM_PID_ICM)
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#define sam_cpkcc_enableclk() sam_enableperiph0(SAM_PID_CPKCC)
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#define sam_aes_enableclk() sam_enableperiph0(SAM_PID_AES)
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#define sam_aesb_enableclk() sam_enableperiph0(SAM_PID_AESB)
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#define sam_tdes_enableclk() sam_enableperiph0(SAM_PID_TDES)
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#define sam_sha_enableclk() sam_enableperiph0(SAM_PID_SHA)
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#define sam_mpddrc_enableclk() sam_enableperiph0(SAM_PID_MPDDRC)
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#define sam_matrix1_enableclk() sam_enableperiph0(SAM_PID_MATRIX1)
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#define sam_matrix0_enableclk() sam_enableperiph0(SAM_PID_MATRIX0)
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#define sam_vdec_enableclk() sam_enableperiph0(SAM_PID_VDEC)
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#define sam_sbm_enableclk() sam_enableperiph0(SAM_PID_SBM)
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#define sam_hsmc_enableclk() sam_enableperiph0(SAM_PID_HSMC)
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#define sam_pioa_enableclk() sam_enableperiph0(SAM_PID_PIOA)
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#define sam_piob_enableclk() sam_enableperiph0(SAM_PID_PIOB)
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#define sam_pioc_enableclk() sam_enableperiph0(SAM_PID_PIOC)
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#define sam_pioe_enableclk() sam_enableperiph0(SAM_PID_PIOE)
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#define sam_uart0_enableclk() sam_enableperiph0(SAM_PID_UART0)
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#define sam_uart1_enableclk() sam_enableperiph0(SAM_PID_UART1)
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#define sam_usart2_enableclk() sam_enableperiph0(SAM_PID_USART2)
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#define sam_usart3_enableclk() sam_enableperiph0(SAM_PID_USART3)
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#define sam_usart4_enableclk() sam_enableperiph0(SAM_PID_USART4)
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#define sam_twi0_enableclk() sam_enableperiph1(SAM_PID_TWI0)
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#define sam_twi1_enableclk() sam_enableperiph1(SAM_PID_TWI1)
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#define sam_twi2_enableclk() sam_enableperiph1(SAM_PID_TWI2)
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#define sam_hsmci0_enableclk() sam_enableperiph1(SAM_PID_HSMCI0)
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#define sam_hsmci1_enableclk() sam_enableperiph1(SAM_PID_HSMCI1)
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#define sam_spi0_enableclk() sam_enableperiph1(SAM_PID_SPI0)
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#define sam_spi1_enableclk() sam_enableperiph1(SAM_PID_SPI1)
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#define sam_spi2_enableclk() sam_enableperiph1(SAM_PID_SPI2)
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#define sam_tc0_enableclk() sam_enableperiph1(SAM_PID_TC0)
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#define sam_tc1_enableclk() sam_enableperiph1(SAM_PID_TC1)
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#define sam_tc2_enableclk() sam_enableperiph1(SAM_PID_TC2)
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#define sam_pwm_enableclk() sam_enableperiph1(SAM_PID_PWM)
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#define sam_adc_enableclk() sam_enableperiph1(SAM_PID_ADC)
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#define sam_dbgu_enableclk() sam_enableperiph1(SAM_PID_DBGU)
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#define sam_uhphs_enableclk() sam_enableperiph1(SAM_PID_UHPHS)
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#define sam_udphs_enableclk() sam_enableperiph1(SAM_PID_UDPHS)
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#define sam_ssc0_enableclk() sam_enableperiph1(SAM_PID_SSC0)
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#define sam_ssc1_enableclk() sam_enableperiph1(SAM_PID_SSC1)
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#define sam_xdmac1_enableclk() sam_enableperiph1(SAM_PID_XDMAC1)
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#define sam_lcdc_enableclk() sam_enableperiph1(SAM_PID_LCDC)
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#define sam_isi_enableclk() sam_enableperiph1(SAM_PID_ISI)
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#define sam_trng_enableclk() sam_enableperiph1(SAM_PID_TRNG)
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#define sam_emac0_enableclk() sam_enableperiph1(SAM_PID_EMAC0)
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#define sam_emac1_enableclk() sam_enableperiph1(SAM_PID_EMAC1)
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#define sam_aicid_enableclk() sam_enableperiph1(SAM_PID_AICID)
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#define sam_sfc_enableclk() sam_enableperiph1(SAM_PID_SFC)
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#define sam_secureram_enableclk() sam_enableperiph1(SAM_PID_SECURAM)
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#define sam_smd_enableclk() sam_enableperiph1(SAM_PID_SMD)
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#define sam_twi3_enableclk() sam_enableperiph1(SAM_PID_TWI3)
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#define sam_catb_enableclk() sam_enableperiph1(SAM_PID_CATB)
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/* The Advanced Interrupt Controller and L2CC cache controllers are
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* continuously clocked. The Power Management Controller has no effect on
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* their behavior.
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*
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* (I presume that this is true of the SFR as well since it has no PMC
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* bits to control its clocking).
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*/
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#define sam_sfr_enableclk()
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#define sam_aic_enableclk()
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#define sam_saic_enableclk()
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#define sam_l2cc_enableclk()
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/* Disable peripheral clocking */
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#define sam_arm_disableclk() sam_disableperiph0(SAM_PID_ARM)
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#define sam_pit_disableclk() sam_disableperiph0(SAM_PID_PIT)
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#define sam_wdt_disableclk() sam_disableperiph0(SAM_PID_WDT)
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#define sam_piod_disableclk() sam_disableperiph0(SAM_PID_PIOD)
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#define sam_usart0_disableclk() sam_disableperiph0(SAM_PID_USART0)
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#define sam_usart1_disableclk() sam_disableperiph0(SAM_PID_USART1)
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#define sam_xdmac0_disableclk() sam_disableperiph0(SAM_PID_XDMAC0)
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#define sam_icm_disableclk() sam_disableperiph0(SAM_PID_ICM)
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#define sam_cpkcc_disableclk() sam_disableperiph0(SAM_PID_CPKCC)
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#define sam_aes_disableclk() sam_disableperiph0(SAM_PID_AES)
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#define sam_aesb_disableclk() sam_disableperiph0(SAM_PID_AESB)
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#define sam_tdes_disableclk() sam_disableperiph0(SAM_PID_TDES)
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#define sam_sha_disableclk() sam_disableperiph0(SAM_PID_SHA)
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#define sam_mpddrc_disableclk() sam_disableperiph0(SAM_PID_MPDDRC)
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#define sam_matrix1_disableclk() sam_disableperiph0(SAM_PID_MATRIX1)
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#define sam_matrix0_disableclk() sam_disableperiph0(SAM_PID_MATRIX0)
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#define sam_vdec_disableclk() sam_disableperiph0(SAM_PID_VDEC)
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#define sam_sbm_disableclk() sam_disableperiph0(SAM_PID_SBM)
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#define sam_hsmc_disableclk() sam_disableperiph0(SAM_PID_HSMC)
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#define sam_pioa_disableclk() sam_disableperiph0(SAM_PID_PIOA)
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#define sam_piob_disableclk() sam_disableperiph0(SAM_PID_PIOB)
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#define sam_pioc_disableclk() sam_disableperiph0(SAM_PID_PIOC)
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#define sam_pioe_disableclk() sam_disableperiph0(SAM_PID_PIOE)
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#define sam_uart0_disableclk() sam_disableperiph0(SAM_PID_UART0)
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#define sam_uart1_disableclk() sam_disableperiph0(SAM_PID_UART1)
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#define sam_usart2_disableclk() sam_disableperiph0(SAM_PID_USART2)
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#define sam_usart3_disableclk() sam_disableperiph0(SAM_PID_USART3)
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#define sam_usart4_disableclk() sam_disableperiph0(SAM_PID_USART4)
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#define sam_twi0_disableclk() sam_disableperiph1(SAM_PID_TWI0)
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#define sam_twi1_disableclk() sam_disableperiph1(SAM_PID_TWI1)
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#define sam_twi2_disableclk() sam_disableperiph1(SAM_PID_TWI2)
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#define sam_hsmci0_disableclk() sam_disableperiph1(SAM_PID_HSMCI0)
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#define sam_hsmci1_disableclk() sam_disableperiph1(SAM_PID_HSMCI1)
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#define sam_spi0_disableclk() sam_disableperiph1(SAM_PID_SPI0)
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#define sam_spi1_disableclk() sam_disableperiph1(SAM_PID_SPI1)
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#define sam_spi2_disableclk() sam_disableperiph1(SAM_PID_SPI2)
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#define sam_tc0_disableclk() sam_disableperiph1(SAM_PID_TC0)
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#define sam_tc1_disableclk() sam_disableperiph1(SAM_PID_TC1)
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#define sam_tc2_disableclk() sam_disableperiph1(SAM_PID_TC2)
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#define sam_pwm_disableclk() sam_disableperiph1(SAM_PID_PWM)
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#define sam_adc_disableclk() sam_disableperiph1(SAM_PID_ADC)
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#define sam_dbgu_disableclk() sam_disableperiph1(SAM_PID_DBGU)
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#define sam_uhphs_disableclk() sam_disableperiph1(SAM_PID_UHPHS)
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#define sam_udphs_disableclk() sam_disableperiph1(SAM_PID_UDPHS)
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#define sam_ssc0_disableclk() sam_disableperiph1(SAM_PID_SSC0)
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#define sam_ssc1_disableclk() sam_disableperiph1(SAM_PID_SSC1)
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#define sam_xdmac1_disableclk() sam_disableperiph1(SAM_PID_XDMAC1)
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#define sam_lcdc_disableclk() sam_disableperiph1(SAM_PID_LCDC)
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#define sam_isi_disableclk() sam_disableperiph1(SAM_PID_ISI)
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#define sam_trng_disableclk() sam_disableperiph1(SAM_PID_TRNG)
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#define sam_emac0_disableclk() sam_disableperiph1(SAM_PID_EMAC0)
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#define sam_emac1_disableclk() sam_disableperiph1(SAM_PID_EMAC1)
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#define sam_aicid_disableclk() sam_disableperiph1(SAM_PID_AICID)
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#define sam_sfc_disableclk() sam_disableperiph1(SAM_PID_SFC)
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#define sam_secureram_disableclk() sam_disableperiph1(SAM_PID_SECURAM)
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#define sam_smd_disableclk() sam_disableperiph1(SAM_PID_SMD)
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#define sam_twi3_disableclk() sam_disableperiph1(SAM_PID_TWI3)
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#define sam_catb_disableclk() sam_disableperiph1(SAM_PID_CATB)
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/* The Advanced Interrupt Controller and L2CC cache controllers are
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* continuously clocked. The Power Management Controller has no effect on
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* their behavior.
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*
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* (I presume that this is true of the SFR as well since it has no PMC
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* bits to control its clocking).
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*/
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#define sam_sfr_disableclk()
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#define sam_aic_disableclk()
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#define sam_saic_disableclk()
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#define sam_l2cc_disableclk()
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/* Test if peripheral clocking is enabled */
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#define sam_arm_isenabled() sam_isenabled0(SAM_PID_ARM)
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#define sam_pit_isenabled() sam_isenabled0(SAM_PID_PIT)
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#define sam_wdt_isenabled() sam_isenabled0(SAM_PID_WDT)
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#define sam_piod_isenabled() sam_isenabled0(SAM_PID_PIOD)
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#define sam_usart0_isenabled() sam_isenabled0(SAM_PID_USART0)
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#define sam_usart1_isenabled() sam_isenabled0(SAM_PID_USART1)
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#define sam_xdmac0_isenabled() sam_isenabled0(SAM_PID_XDMAC0)
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#define sam_icm_isenabled() sam_isenabled0(SAM_PID_ICM)
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#define sam_cpkcc_isenabled() sam_isenabled0(SAM_PID_CPKCC)
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#define sam_aes_isenabled() sam_isenabled0(SAM_PID_AES)
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#define sam_aesb_isenabled() sam_isenabled0(SAM_PID_AESB)
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#define sam_tdes_isenabled() sam_isenabled0(SAM_PID_TDES)
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#define sam_sha_isenabled() sam_isenabled0(SAM_PID_SHA)
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#define sam_mpddrc_isenabled() sam_isenabled0(SAM_PID_MPDDRC)
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#define sam_matrix1_isenabled() sam_isenabled0(SAM_PID_MATRIX1)
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#define sam_matrix0_isenabled() sam_isenabled0(SAM_PID_MATRIX0)
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#define sam_vdec_isenabled() sam_isenabled0(SAM_PID_VDEC)
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#define sam_sbm_isenabled() sam_isenabled0(SAM_PID_SBM)
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#define sam_hsmc_isenabled() sam_isenabled0(SAM_PID_HSMC)
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#define sam_pioa_isenabled() sam_isenabled0(SAM_PID_PIOA)
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#define sam_piob_isenabled() sam_isenabled0(SAM_PID_PIOB)
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#define sam_pioc_isenabled() sam_isenabled0(SAM_PID_PIOC)
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#define sam_pioe_isenabled() sam_isenabled0(SAM_PID_PIOE)
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#define sam_uart0_isenabled() sam_isenabled0(SAM_PID_UART0)
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#define sam_uart1_isenabled() sam_isenabled0(SAM_PID_UART1)
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#define sam_usart2_isenabled() sam_isenabled0(SAM_PID_USART2)
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#define sam_usart3_isenabled() sam_isenabled0(SAM_PID_USART3)
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#define sam_usart4_isenabled() sam_isenabled0(SAM_PID_USART4)
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#define sam_twi0_isenabled() sam_isenabled1(SAM_PID_TWI0)
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#define sam_twi1_isenabled() sam_isenabled1(SAM_PID_TWI1)
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#define sam_twi2_isenabled() sam_isenabled1(SAM_PID_TWI2)
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#define sam_hsmci0_isenabled() sam_isenabled1(SAM_PID_HSMCI0)
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#define sam_hsmci1_isenabled() sam_isenabled1(SAM_PID_HSMCI1)
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#define sam_spi0_isenabled() sam_isenabled1(SAM_PID_SPI0)
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#define sam_spi1_isenabled() sam_isenabled1(SAM_PID_SPI1)
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#define sam_spi2_isenabled() sam_isenabled1(SAM_PID_SPI2)
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#define sam_tc0_isenabled() sam_isenabled1(SAM_PID_TC0)
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#define sam_tc1_isenabled() sam_isenabled1(SAM_PID_TC1)
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#define sam_tc2_isenabled() sam_isenabled1(SAM_PID_TC2)
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#define sam_pwm_isenabled() sam_isenabled1(SAM_PID_PWM)
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#define sam_adc_isenabled() sam_isenabled1(SAM_PID_ADC)
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#define sam_dbgu_isenabled() sam_isenabled1(SAM_PID_DBGU)
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#define sam_uhphs_isenabled() sam_isenabled1(SAM_PID_UHPHS)
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#define sam_udphs_isenabled() sam_isenabled1(SAM_PID_UDPHS)
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#define sam_ssc0_isenabled() sam_isenabled1(SAM_PID_SSC0)
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#define sam_ssc1_isenabled() sam_isenabled1(SAM_PID_SSC1)
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#define sam_xdmac1_isenabled() sam_isenabled1(SAM_PID_XDMAC1)
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#define sam_lcdc_isenabled() sam_isenabled1(SAM_PID_LCDC)
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#define sam_isi_isenabled() sam_isenabled1(SAM_PID_ISI)
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#define sam_trng_isenabled() sam_isenabled1(SAM_PID_TRNG)
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#define sam_emac0_isenabled() sam_isenabled1(SAM_PID_EMAC0)
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#define sam_emac1_isenabled() sam_isenabled1(SAM_PID_EMAC1)
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#define sam_aicid_isenabled() sam_isenabled1(SAM_PID_AICID)
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#define sam_sfc_isenabled() sam_isenabled1(SAM_PID_SFC)
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#define sam_secureram_isenabled() sam_isenabled1(SAM_PID_SECURAM)
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#define sam_smd_isenabled() sam_isenabled1(SAM_PID_SMD)
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#define sam_twi3_isenabled() sam_isenabled1(SAM_PID_TWI3)
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#define sam_catb_isenabled() sam_isenabled1(SAM_PID_CATB)
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/* The Advanced Interrupt Controller and L2CC cache controllers are
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* continuously clocked. The Power Management Controller has no effect on
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* their behavior.
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*
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* (I presume that this is true of the SFR as well since it has no PMC
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* bits to control its clocking).
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*/
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#define sam_sfr_isenabled() (true)
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#define sam_aic_isenabled() (true)
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#define sam_saic_isenabled() (true)
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#define sam_l2cc_isenabled() (true)
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Inline Functions
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************************************************************************************/
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#ifndef __ASSEMBLY__
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/************************************************************************************
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* Public Data
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************************************************************************************/
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/************************************************************************************
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* Public Function Prototypes
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************************************************************************************/
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#undef EXTERN
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#if defined(__cplusplus)
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_ARM_SRC_SAMA5_SAMAD54X_PERIPHCLKS_H */
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