372 lines
21 KiB
C
372 lines
21 KiB
C
/****************************************************************************************
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* arch/arm/src/sam34/chip/sam_matrix.h
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* Bux matrix definitions for the SAM3U, SAM3X, SAM3A, SAM4E, and SAM4S
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*
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* Copyright (C) 2009-2010, 2013-2014 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_MATRIX_H
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#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_MATRIX_H
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/****************************************************************************************
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* Included Files
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****************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#include "chip/sam_memorymap.h"
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/****************************************************************************************
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* Pre-processor Definitions
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****************************************************************************************/
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/* MATRIX register offsets **************************************************************/
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#define SAM_MATRIX_MCFG_OFFSET(n) ((n)<<2)
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#define SAM_MATRIX_MCFG0_OFFSET 0x0000 /* Master Configuration Register 0 */
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#define SAM_MATRIX_MCFG1_OFFSET 0x0004 /* Master Configuration Register 1 */
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#define SAM_MATRIX_MCFG2_OFFSET 0x0008 /* Master Configuration Register 2 */
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#define SAM_MATRIX_MCFG3_OFFSET 0x000c /* Master Configuration Register 3 */
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#define SAM_MATRIX_MCFG4_OFFSET 0x0010 /* Master Configuration Register 4 */
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#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || \
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defined(CONFIG_ARCH_CHIP_SAM4E)
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# define SAM_MATRIX_MCFG5_OFFSET 0x0014 /* Master Configuration Register 5 */
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#endif
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#if defined(CONFIG_ARCH_CHIP_SAM4E)
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# define SAM_MATRIX_MCFG6_OFFSET 0x0018 /* Master Configuration Register 6 */
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#endif
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/* 0x0018-0x003c: Reserved */
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#define SAM_MATRIX_SCFG_OFFSET(n) (0x0040+((n)<<2))
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#define SAM_MATRIX_SCFG0_OFFSET 0x0040 /* Slave Configuration Register 0 */
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#define SAM_MATRIX_SCFG1_OFFSET 0x0044 /* Slave Configuration Register 1 */
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#define SAM_MATRIX_SCFG2_OFFSET 0x0048 /* Slave Configuration Register 2 */
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#define SAM_MATRIX_SCFG3_OFFSET 0x004c /* Slave Configuration Register 3 */
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#define SAM_MATRIX_SCFG4_OFFSET 0x0050 /* Slave Configuration Register 4 */
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#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
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defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4E)
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# define SAM_MATRIX_SCFG5_OFFSET 0x0054 /* Slave Configuration Register 5 */
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#endif
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#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
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defined(CONFIG_ARCH_CHIP_SAM3A)
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# define SAM_MATRIX_SCFG6_OFFSET 0x0058 /* Slave Configuration Register 6 */
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# define SAM_MATRIX_SCFG7_OFFSET 0x005c /* Slave Configuration Register 7 */
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# define SAM_MATRIX_SCFG8_OFFSET 0x0060 /* Slave Configuration Register 8 */
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#endif
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#if defined(CONFIG_ARCH_CHIP_SAM3U)
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# define SAM_MATRIX_SCFG9_OFFSET 0x0064 /* Slave Configuration Register 9 */
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#endif
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#define SAM_MATRIX_PRAS_OFFSET(n) (0x0080+((n)<<3))
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#define SAM_MATRIX_PRAS0_OFFSET 0x0080 /* Priority Register A for Slave 0 */
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#define SAM_MATRIX_PRAS1_OFFSET 0x0088 /* Priority Register A for Slave 1 */
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#define SAM_MATRIX_PRAS2_OFFSET 0x0090 /* Priority Register A for Slave 2 */
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#define SAM_MATRIX_PRAS3_OFFSET 0x0098 /* Priority Register A for Slave 3 */
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#define SAM_MATRIX_PRAS4_OFFSET 0x00a0 /* Priority Register A for Slave 4 */
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#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
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defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4E)
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# define SAM_MATRIX_PRAS5_OFFSET 0x00a8 /* Priority Register A for Slave 5 */
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#endif
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#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
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defined(CONFIG_ARCH_CHIP_SAM3A)
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# define SAM_MATRIX_PRAS6_OFFSET 0x00b0 /* Priority Register A for Slave 6 */
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# define SAM_MATRIX_PRAS7_OFFSET 0x00b8 /* Priority Register A for Slave 7 */
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# define SAM_MATRIX_PRAS8_OFFSET 0x00c0 /* Priority Register A for Slave 8 */
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#endif
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#if defined(CONFIG_ARCH_CHIP_SAM3U)
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# define SAM_MATRIX_PRAS9_OFFSET 0x00c8 /* Priority Register A for Slave 9 */
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#endif
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#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
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defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4E)
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# define SAM_MATRIX_MRCR_OFFSET 0x0100 /* Master Remap Control Register */
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#endif
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#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || \
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defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
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# define SAM_MATRIX_CCFG_SYSIO_OFFSET 0x0114 /* System I/O Configuration Register */
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#endif
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#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
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# define SAM_MATRIX_CCFG_SMCNFCS_OFFSET 0x011c /* SMC Chip Select NAND Flash Assignment Register */
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#endif
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#define SAM_MATRIX_WPMR_OFFSET 0x01e4 /* Write Protect Mode Register */
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#define SAM_MATRIX_WPSR_OFFSET 0x01e8 /* Write Protect Status Register */
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/* 0x0110 - 0x01fc: Reserved */
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/* MATRIX register addresses ************************************************************/
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#define SAM_MATRIX_MCFG(n)) (SAM_MATRIX_BASE+SAM_MATRIX_MCFG_OFFSET(n))
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#define SAM_MATRIX_MCFG0 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG0_OFFSET)
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#define SAM_MATRIX_MCFG1 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG1_OFFSET)
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#define SAM_MATRIX_MCFG2 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG2_OFFSET)
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#define SAM_MATRIX_MCFG3 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG3_OFFSET)
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#define SAM_MATRIX_MCFG4 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG4_OFFSET)
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#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || \
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defined(CONFIG_ARCH_CHIP_SAM4E)
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# define SAM_MATRIX_MCFG5 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG5_OFFSET)
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#endif
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#if defined(CONFIG_ARCH_CHIP_SAM4E)
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# define SAM_MATRIX_MCFG6 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG6_OFFSET)
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#endif
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#define SAM_MATRIX_SCFG(n) (SAM_MATRIX_BASE+SAM_MATRIX_SCFG_OFFSET(n))
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#define SAM_MATRIX_SCFG0 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG0_OFFSET)
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#define SAM_MATRIX_SCFG1 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG1_OFFSET)
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#define SAM_MATRIX_SCFG2 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG2_OFFSET)
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#define SAM_MATRIX_SCFG3 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG3_OFFSET)
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#define SAM_MATRIX_SCFG4 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG4_OFFSET)
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#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
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defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4E)
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# define SAM_MATRIX_SCFG5 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG5_OFFSET)
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#endif
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#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
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defined(CONFIG_ARCH_CHIP_SAM3A)
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# define SAM_MATRIX_SCFG6 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG6_OFFSET)
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# define SAM_MATRIX_SCFG7 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG7_OFFSET)
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# define SAM_MATRIX_SCFG8 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG8_OFFSET)
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#endif
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#if defined(CONFIG_ARCH_CHIP_SAM3U)
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# define SAM_MATRIX_SCFG9 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG9_OFFSET)
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#endif
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#define SAM_MATRIX_PRAS(n) (SAM_MATRIX_BASE+SAM_MATRIX_PRAS_OFFSET(n))
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#define SAM_MATRIX_PRAS0 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS0_OFFSET)
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#define SAM_MATRIX_PRAS1 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS1_OFFSET)
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#define SAM_MATRIX_PRAS2 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS2_OFFSET)
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#define SAM_MATRIX_PRAS3 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS3_OFFSET)
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#define SAM_MATRIX_PRAS4 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS4_OFFSET)
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#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
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defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4E)
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# define SAM_MATRIX_PRAS5 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS5_OFFSET)
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#endif
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#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
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defined(CONFIG_ARCH_CHIP_SAM3A)
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# define SAM_MATRIX_PRAS6 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS6_OFFSET)
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# define SAM_MATRIX_PRAS7 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS7_OFFSET)
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# define SAM_MATRIX_PRAS8 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS8_OFFSET)
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#endif
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#if defined(CONFIG_ARCH_CHIP_SAM3U)
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# define SAM_MATRIX_PRAS9 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS9_OFFSET)
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#endif
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#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
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defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4E)
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# define SAM_MATRIX_MRCR (SAM_MATRIX_BASE+SAM_MATRIX_MRCR_OFFSET)
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#endif
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#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || \
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defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
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# define SAM_MATRIX_CCFG_SYSIO (SAM_MATRIX_BASE+SAM_MATRIX_CCFG_SYSIO_OFFSET)
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#endif
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#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
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# define SAM_MATRIX_CCFG_SMCNFCS (SAM_MATRIX_BASE+SAM_MATRIX_CCFG_SMCNFCS_OFFSET)
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#endif
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#define SAM_MATRIX_WPMR (SAM_MATRIX_BASE+SAM_MATRIX_WPMR_OFFSET)
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#define SAM_MATRIX_WPSR (SAM_MATRIX_BASE+SAM_MATRIX_WPSR_OFFSET)
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/* MATRIX register bit definitions ******************************************************/
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/* Master Configuration Registers */
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#define MATRIX_MCFG_ULBT_SHIFT (0) /* Bits 0-2: Undefined Length Burst Type */
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#define MATRIX_MCFG_ULBT_MASK (7 << MATRIX_MCFG_ULBT_SHIFT)
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# define MATRIX_MCFG_ULBT_INF (0 << MATRIX_MCFG_ULBT_SHIFT) /* Infinite Length Burst */
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# define MATRIX_MCFG_ULBT_SINGLE (1 << MATRIX_MCFG_ULBT_SHIFT) /* Single Access */
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# define MATRIX_MCFG_ULBT_4BEAT (2 << MATRIX_MCFG_ULBT_SHIFT) /* 4-beat Burst */
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# define MATRIX_MCFG_ULBT_8BEAT (3 << MATRIX_MCFG_ULBT_SHIFT) /* 8-beat Burst */
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# define MATRIX_MCFG_ULBT_16BEAT (4 << MATRIX_MCFG_ULBT_SHIFT) /* 16-beat Burst */
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# if defined(CONFIG_ARCH_CHIP_SAM4E)
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# define MATRIX_MCFG_ULBT_32BEAT (5 << MATRIX_MCFG_ULBT_SHIFT) /* 32-beat Burst */
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# define MATRIX_MCFG_ULBT_64BEAT (6 << MATRIX_MCFG_ULBT_SHIFT) /* 64-beat Burst */
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# define MATRIX_MCFG_ULBT_128BEAT (7 << MATRIX_MCFG_ULBT_SHIFT) /* 128-beat Burst */
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# endif
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/* Bus Matrix Slave Configuration Registers */
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#if defined(CONFIG_ARCH_CHIP_SAM4E)
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# define MATRIX_SCFG_SLOTCYCLE_SHIFT (0) /* Bits 0-8: Maximum Number of Allowed Cycles for a Burst */
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# define MATRIX_SCFG_SLOTCYCLE_MASK (0x1ff << MATRIX_SCFG_SLOTCYCLE_SHIFT)
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# define MATRIX_SCFG_SLOTCYCLE(n) ((uint32_t)(n) << MATRIX_SCFG_SLOTCYCLE_SHIFT)
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#else
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# define MATRIX_SCFG_SLOTCYCLE_SHIFT (0) /* Bits 0-7: Maximum Number of Allowed Cycles for a Burst */
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# define MATRIX_SCFG_SLOTCYCLE_MASK (0xff << MATRIX_SCFG_SLOTCYCLE_SHIFT)
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# define MATRIX_SCFG_SLOTCYCLE(n) ((uint32_t)(n) << MATRIX_SCFG_SLOTCYCLE_SHIFT)
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#endif
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#define MATRIX_SCFG_DEFMSTRTYPE_SHIFT (16) /* Bits 16-17: Default Master Type */
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#define MATRIX_SCFG_DEFMSTRTYPE_MASK (3 << MATRIX_SCFG_DEFMSTRTYPE_SHIFT)
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# define MATRIX_SCFG_DEFMSTRTYPE_NONE (0 << MATRIX_SCFG_DEFMSTRTYPE_SHIFT)
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# define MATRIX_SCFG_DEFMSTRTYPE_LAST (1 << MATRIX_SCFG_DEFMSTRTYPE_SHIFT)
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# define MATRIX_SCFG_DEFMSTRTYPE_FIXED (2 << MATRIX_SCFG_DEFMSTRTYPE_SHIFT)
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#define MATRIX_SCFG_FIXEDDEFMSTR_SHIFT (18) /* Bits 18-20: Fixed Default Master */
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#define MATRIX_SCFG_FIXEDDEFMSTR_MASK (7 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
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# define MATRIX_SCFG0_FIXEDDEFMSTR(n) ((uint32_t)(n) << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
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# define MATRIX_SCFG0_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
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# define MATRIX_SCFG1_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
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# define MATRIX_SCFG2_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
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# define MATRIX_SCFG3_FIXEDDEFMSTR_ARMC (0 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
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# define MATRIX_SCFG4_FIXEDDEFMSTR_ARMC (0 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
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# define MATRIX_SCFG5_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
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# define MATRIX_SCFG6_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
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# define MATRIX_SCFG7_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
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# define MATRIX_SCFG8_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
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# define MATRIX_SCFG8_FIXEDDEFMSTR_HDMA (4 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
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# define MATRIX_SCFG9_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
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# define MATRIX_SCFG9_FIXEDDEFMSTR_HDMA (4 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
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#if !defined(CONFIG_ARCH_CHIP_SAM4E)
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# define MATRIX_SCFG_ARBT_SHIFT (24) /* Bits 24-25: Arbitration Type */
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# define MATRIX_SCFG_ARBT_MASK (3 << MATRIX_SCFG_ARBT_SHIFT)
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# define MATRIX_SCFG_ARBT_RR (0 << MATRIX_SCFG_ARBT_SHIFT) /* Round-Robin Arbitration */
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# define MATRIX_SCFG_ARBT_FIXED (1 << MATRIX_SCFG_ARBT_SHIFT) /* Fixed Priority Arbitration */
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#endif
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/* Bus Matrix Priority Registers For Slaves */
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#define MATRIX_PRAS_MPR_SHIFT(x) ((n)<<2)
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#define MATRIX_PRAS_MPR_MASK(x) (3 << MATRIX_PRAS_MPR_SHIFT(x))
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# define MATRIX_PRAS_M0PR_SHIFT (0) /* Bits 0-1: Master 0 Priority */
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# define MATRIX_PRAS_M0PR_MASK (3 << MATRIX_PRAS_M0PR_SHIFT)
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# define MATRIX_PRAS_M0PR(n) ((uint32_t)(n) << MATRIX_PRAS_M0PR_SHIFT)
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# define MATRIX_PRAS_M1PR_SHIFT (4) /* Bits 4-5: Master 1 Priority */
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# define MATRIX_PRAS_M1PR_MASK (3 << MATRIX_PRAS_M1PR_SHIFT)
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# define MATRIX_PRAS_M1PR(n) ((uint32_t)(n) << MATRIX_PRAS_M1PR_SHIFT)
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# define MATRIX_PRAS_M2PR_SHIFT (8) /* Bits 8-9: Master 2 Priority */
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# define MATRIX_PRAS_M2PR_MASK (3 << MATRIX_PRAS_M2PR_SHIFT)
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# define MATRIX_PRAS_M2PR(n) ((uint32_t)(n) << MATRIX_PRAS_M2PR_SHIFT)
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# define MATRIX_PRAS_M3PR_SHIFT (12) /* Bits 12-13: Master 3 Priority */
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# define MATRIX_PRAS_M3PR_MASK (3 << MATRIX_PRAS_M3PR_SHIFT)
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# define MATRIX_PRAS_M3PR(n) ((uint32_t)(n) << MATRIX_PRAS_M3PR_SHIFT)
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# define MATRIX_PRAS_M4PR_SHIFT (16) /* Bits 16-17: Master 4 Priority */
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# define MATRIX_PRAS_M4PR_MASK (3 << MATRIX_PRAS_M4PR_SHIFT)
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# define MATRIX_PRAS_M4PR(n) ((uint32_t)(n) << MATRIX_PRAS_M4PR_SHIFT)
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#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || \
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defined(CONFIG_ARCH_CHIP_SAM4E)
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# define MATRIX_PRAS_M5PR_SHIFT (20) /* Bits 20-21: Master 5 Priority */
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# define MATRIX_PRAS_M5PR_MASK (3 << MATRIX_PRAS_M5PR_SHIFT)
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# define MATRIX_PRAS_M5PR(n) ((uint32_t)(n) << MATRIX_PRAS_M5PR_SHIFT)
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#endif
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#if defined(CONFIG_ARCH_CHIP_SAM4E)
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# define MATRIX_PRAS_M6PR_SHIFT (24) /* Bits 24-25: Master 6 Priority */
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# define MATRIX_PRAS_M6PR_MASK (3 << MATRIX_PRAS_M6PR_SHIFT)
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# define MATRIX_PRAS_M6PR(n) ((uint32_t)(n) << MATRIX_PRAS_M6PR_SHIFT)
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# define MATRIX_PRAS_M7PR_SHIFT (28) /* Bits 28-29: Master 7 Priority */
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# define MATRIX_PRAS_M7PR_MASK (3 << MATRIX_PRAS_M7PR_SHIFT)
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# define MATRIX_PRAS_M7PR(n) ((uint32_t)(n) << MATRIX_PRAS_M7PR_SHIFT)
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#endif
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/* System I/O Configuration Register */
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#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
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# define MATRIX_CCFG_SYSIO_SYSIO4 (1 << 4) /* Bit 4: PB4 or TDI Assignment */
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# define MATRIX_CCFG_SYSIO_SYSIO5 (1 << 5) /* Bit 5: PB5 or TDO/TRACESWO Assignment */
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# define MATRIX_CCFG_SYSIO_SYSIO6 (1 << 6) /* Bit 6: PB6 or TMS/SWDIO Assignment */
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# define MATRIX_CCFG_SYSIO_SYSIO7 (1 << 7) /* Bit 7: PB7 or TCK/SWCLK Assignment */
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# define MATRIX_CCFG_SYSIO_SYSIO10 (1 << 10) /* Bit 10: PB10 or DDM Assignment */
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# define MATRIX_CCFG_SYSIO_SYSIO11 (1 << 11) /* Bit 11: PB11 or DDP Assignment */
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# define MATRIX_CCFG_SYSIO_SYSIO12 (1 << 12) /* Bit 12: PB12 or ERASE Assignment */
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#endif
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#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
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# define MATRIX_CCFG_SYSIO_SYSIO12 (1 << 12) /* Bit 12: PC0 or ERASE Assignment */
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#endif
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/* SMC Chip Select NAND Flash Assignment Register */
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#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
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# define MATRIX_CCFG_SMCNFCS_SMC_NFCS0 (1 << 0) /* Bit 0: SMC NAND Flash Chip Select 0 Assignment */
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# define MATRIX_CCFG_SMCNFCS_SMC_NFCS1 (1 << 1) /* Bit 1: SMC NAND Flash Chip Select 2 Assignment */
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# define MATRIX_CCFG_SMCNFCS_SMC_NFCS2 (1 << 2) /* Bit 2: SMC NAND Flash Chip Select 2 Assignment */
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# define MATRIX_CCFG_SMCNFCS_SMC_NFCS3 (1 << 3) /* Bit 3: SMC NAND Flash Chip Select 3 Assignment */
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#endif
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/* Master Remap Control Register */
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#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
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defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4E)
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# define MATRIX_MRCR_RCB(x) (1 << (x))
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# define MATRIX_MRCR_RCB0 (1 << 0) /* Bit 0: Remap Command Bit for AHB Master 0 */
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# define MATRIX_MRCR_RCB1 (1 << 1) /* Bit 1: Remap Command Bit for AHB Master 1 */
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# define MATRIX_MRCR_RCB2 (1 << 2) /* Bit 2: Remap Command Bit for AHB Master 2 */
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# define MATRIX_MRCR_RCB3 (1 << 3) /* Bit 3: Remap Command Bit for AHB Master 3 */
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# define MATRIX_MRCR_RCB4 (1 << 4) /* Bit 4: Remap Command Bit for AHB Master 4 */
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#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || \
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defined(CONFIG_ARCH_CHIP_SAM4E)
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# define MATRIX_MRCR_RCB5 (1 << 5) /* Bit 5: Remap Command Bit for AHB Master 5 */
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#endif
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#if defined(CONFIG_ARCH_CHIP_SAM4E)
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# define MATRIX_MRCR_RCB6 (1 << 6) /* Bit 6: Remap Command Bit for AHB Master 6 */
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# define MATRIX_MRCR_RCB7 (1 << 7) /* Bit 7: Remap Command Bit for AHB Master 7 */
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# define MATRIX_MRCR_RCB8 (1 << 8) /* Bit 8: Remap Command Bit for AHB Master 8 */
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# define MATRIX_MRCR_RCB9 (1 << 9) /* Bit 9: Remap Command Bit for AHB Master 9 */
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# define MATRIX_MRCR_RCB10 (1 << 10) /* Bit 10: Remap Command Bit for AHB Master 10 */
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# define MATRIX_MRCR_RCB11 (1 << 11) /* Bit 11: Remap Command Bit for AHB Master 11 */
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# define MATRIX_MRCR_RCB12 (1 << 12) /* Bit 12: Remap Command Bit for AHB Master 12 */
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# define MATRIX_MRCR_RCB13 (1 << 13) /* Bit 13: Remap Command Bit for AHB Master 13 */
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# define MATRIX_MRCR_RCB14 (1 << 14) /* Bit 14: Remap Command Bit for AHB Master 14 */
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# define MATRIX_MRCR_RCB15 (1 << 15) /* Bit 15: Remap Command Bit for AHB Master 15 */
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#endif
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#endif
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/* Write Protect Mode Register */
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#define MATRIX_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */
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#define MATRIX_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY (Write-only) */
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#define MATRIX_WPMR_WPKEY_MASK (0x00ffffff << MATRIX_WPMR_WPKEY_SHIFT)
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# define MATRIX_WPMR_WPKEY (0x004d4154 << MATRIX_WPMR_WPKEY_SHIFT)
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/* Write Protect Status Register */
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#define MATRIX_WPSR_WPVS (1 << 0) /* Bit 0: Enable Write Protect */
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#define MATRIX_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */
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#define MATRIX_WPSR_WPVSRC_MASK (0xffff << MATRIX_WPSR_WPVSRC_SHIFT)
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/****************************************************************************************
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* Public Types
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****************************************************************************************/
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/****************************************************************************************
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* Public Data
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****************************************************************************************/
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/****************************************************************************************
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* Public Functions
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****************************************************************************************/
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#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_MATRIX_H */
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