108 lines
6.3 KiB
C
108 lines
6.3 KiB
C
/****************************************************************************************************
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* arch/arm/include/nrf52/nrf52_irq.h
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_NRF52_NRF52_IRQ_H
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#define __ARCH_ARM_INCLUDE_NRF52_NRF52_IRQ_H
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/****************************************************************************************************
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* Included Files
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****************************************************************************************************/
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/****************************************************************************************************
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* Pre-processor Definitions
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****************************************************************************************************/
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/* Cortex-M4 External interrupts (vectors >= 16) */
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#define NRF52_IRQ_POWER_CLOCK (NRF52_IRQ_EXTINT+0) /* Power, Clock, Bprot */
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#define NRF52_IRQ_RADIO (NRF52_IRQ_EXTINT+1) /* Radio controller */
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#define NRF52_IRQ_UART0 (NRF52_IRQ_EXTINT+2) /* UART/UARTE 0 */
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#define NRF52_IRQ_SPI_TWI_0 (NRF52_IRQ_EXTINT+3) /* SPI / TWI 0 */
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#define NRF52_IRQ_SPI_TWI_1 (NRF52_IRQ_EXTINT+4) /* SPI / TWI 1 */
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#define NRF52_IRQ_NFCT (NRF52_IRQ_EXTINT+5) /* NFCT */
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#define NRF52_IRQ_GPIOTE (NRF52_IRQ_EXTINT+6) /* GPIO Task & Event */
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#define NRF52_IRQ_SAADC (NRF52_IRQ_EXTINT+7) /* Analog to Digital Converter */
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#define NRF52_IRQ_TIMER0 (NRF52_IRQ_EXTINT+8) /* Timer 0 */
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#define NRF52_IRQ_TIMER1 (NRF52_IRQ_EXTINT+9) /* Timer 1 */
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#define NRF52_IRQ_TIMER2 (NRF52_IRQ_EXTINT+10) /* Timer 2 */
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#define NRF52_IRQ_RTC0 (NRF52_IRQ_EXTINT+11) /* Real-time counter 0 */
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#define NRF52_IRQ_TEMP (NRF52_IRQ_EXTINT+12) /* Temperature Sensor */
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#define NRF52_IRQ_RNG (NRF52_IRQ_EXTINT+13) /* Random Number Generator */
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#define NRF52_IRQ_ECB (NRF52_IRQ_EXTINT+14) /* AES ECB Mode Encryption */
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#define NRF52_IRQ_CCM_AAR (NRF52_IRQ_EXTINT+15) /* AES CCM Mode Encryption/Accel. Address Resolve */
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#define NRF52_IRQ_WDT (NRF52_IRQ_EXTINT+16) /* Watchdog Timer */
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#define NRF52_IRQ_RTC1 (NRF52_IRQ_EXTINT+17) /* Real-time counter 1 */
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#define NRF52_IRQ_QDEC (NRF52_IRQ_EXTINT+18) /* Quadrature decoder */
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#define NRF52_IRQ_COMP_LPCOMP (NRF52_IRQ_EXTINT+19) /* Low power comparator */
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#define NRF52_IRQ_SWI0_EGU0 (NRF52_IRQ_EXTINT+20) /* Software interrupt 0 / Event Gen. Unit 0 */
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#define NRF52_IRQ_SWI1_EGU1 (NRF52_IRQ_EXTINT+21) /* Software interrupt 1 / Event Gen. Unit 1 */
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#define NRF52_IRQ_SWI2_EGU2 (NRF52_IRQ_EXTINT+22) /* Software interrupt 2 / Event Gen. Unit 2 */
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#define NRF52_IRQ_SWI3_EGU3 (NRF52_IRQ_EXTINT+23) /* Software interrupt 3 / Event Gen. Unit 3 */
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#define NRF52_IRQ_SWI4_EGU4 (NRF52_IRQ_EXTINT+24) /* Software interrupt 4 / Event Gen. Unit 4 */
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#define NRF52_IRQ_SWI5_EGU5 (NRF52_IRQ_EXTINT+25) /* Software interrupt 5 / Event Gen. Unit 5 */
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#define NRF52_IRQ_TIMER3 (NRF52_IRQ_EXTINT+26) /* Timer 3 */
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#define NRF52_IRQ_TIMER4 (NRF52_IRQ_EXTINT+27) /* Timer 4 */
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#define NRF52_IRQ_PWM0 (NRF52_IRQ_EXTINT+28) /* Pulse Width Modulation Unit 0 */
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#define NRF52_IRQ_PDM (NRF52_IRQ_EXTINT+29) /* Pulse Density Modulation (Digital Mic) Interface */
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#define NRF52_IRQ_NVMC (NRF52_IRQ_EXTINT+30) /* Non Volatile Memory Controller */
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#define NRF52_IRQ_PPI (NRF52_IRQ_EXTINT+31) /* PPI controller */
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#define NRF52_IRQ_MWU (NRF52_IRQ_EXTINT+32) /* Memory Watch Unit */
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#define NRF52_IRQ_PWM1 (NRF52_IRQ_EXTINT+33) /* Pulse Width Modulation Unit 1 */
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#define NRF52_IRQ_PWM2 (NRF52_IRQ_EXTINT+34) /* Pulse Width Modulation Unit 2 */
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#define NRF52_IRQ_SPI2 (NRF52_IRQ_EXTINT+35) /* SPI master 2 / SPI slave 2 */
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#define NRF52_IRQ_RTC2 (NRF52_IRQ_EXTINT+36) /* Real-time counter 2 */
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#define NRF52_IRQ_I2S (NRF52_IRQ_EXTINT+37) /* Inter-IC Sound interface */
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#define NRF52_IRQ_FPU (NRF52_IRQ_EXTINT+38) /* FPU interrupt */
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#if defined(CONFIG_ARCH_FAMILY_NRF52840)
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#define NRF52_IRQ_USBD (NRF52_IRQ_EXTINT+39) /* USB device */
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#define NRF52_IRQ_UARTE1 (NRF52_IRQ_EXTINT+40) /* UARTE 1 */
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#define NRF52_IRQ_QSPI (NRF52_IRQ_EXTINT+41) /* Quad SPI */
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#define NRF52_IRQ_PWM3 (NRF52_IRQ_EXTINT+45) /* Pulse Width Modulation Unit 3 */
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#define NRF52_IRQ_SPIM3 (NRF52_IRQ_EXTINT+47) /* SPI Master 3 */
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#define NRF52_IRQ_NEXTINT (48)
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#else
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#define NRF52_IRQ_NEXTINT (39)
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#endif
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#define NRF52_IRQ_NIRQS (NRF52_IRQ_EXTINT+NRF52_IRQ_NEXTINT)
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/* Total number of IRQ numbers */
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#define NR_IRQS NRF52_IRQ_NIRQS
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#endif /* __ARCH_ARM_INCLUDE_NRF52_NRF52_IRQ_H */
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