238 lines
14 KiB
C
238 lines
14 KiB
C
/****************************************************************************
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* arch/mips/src/pic32mx/pic32mx_adc.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_ADC_H
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#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_ADC_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include "pic32mx_memorymap.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Register Offsets *********************************************************/
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#define PIC32MX_ADC_CON1_OFFSET 0x0000 /* ADC control register 1 */
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#define PIC32MX_ADC_CON1CLR_OFFSET 0x0004 /* ADC control clear register 1 */
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#define PIC32MX_ADC_CON1SET_OFFSET 0x0008 /* ADC control set register 1 */
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#define PIC32MX_ADC_CON1INV_OFFSET 0x000c /* ADC control invert register 1 */
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#define PIC32MX_ADC_CON2_OFFSET 0x0010 /* ADC control register 2 */
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#define PIC32MX_ADC_CON2CLR_OFFSET 0x0014 /* ADC control clear register 2 */
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#define PIC32MX_ADC_CON2SET_OFFSET 0x0018 /* ADC control set register 2 */
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#define PIC32MX_ADC_CON2INV_OFFSET 0x001c /* ADC control invert register 2 */
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#define PIC32MX_ADC_CON3_OFFSET 0x0020 /* ADC control register 3 */
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#define PIC32MX_ADC_CON3CLR_OFFSET 0x0024 /* ADC control clear register 3 */
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#define PIC32MX_ADC_CON3SET_OFFSET 0x0028 /* ADC control set register 3 */
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#define PIC32MX_ADC_CON3INV_OFFSET 0x002c /* ADC control invert register 3 */
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#define PIC32MX_ADC_CHS_OFFSET 0x0040 /* ADC input pin selection register */
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#define PIC32MX_ADC_CHSCLR_OFFSET 0x0044 /* ADC input pin selection clear register */
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#define PIC32MX_ADC_CHSSET_OFFSET 0x0048 /* ADC input pin selection set register */
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#define PIC32MX_ADC_CHSINV_OFFSET 0x004c /* ADC input pin selection invert register */
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#define PIC32MX_ADC_CSSL_OFFSET 0x0050 /* ADC sequentially scanned input register */
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#define PIC32MX_ADC_CSSLCLR_OFFSET 0x0054 /* ADC sequentially scanned input clear register */
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#define PIC32MX_ADC_CSSLSET_OFFSET 0x0058 /* ADC sequentially scanned input set register */
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#define PIC32MX_ADC_CSSLINV_OFFSET 0x005c /* ADC sequentially scanned input invert register */
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#define PIC32MX_ADC_CFG_OFFSET 0x0060 /* ADC input pin configuration register */
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#define PIC32MX_ADC_CFGCLR_OFFSET 0x0064 /* ADC input pin configuration clear register */
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#define PIC32MX_ADC_CFGSET_OFFSET 0x0068 /* ADC input pin configuration set register */
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#define PIC32MX_ADC_CFGINV_OFFSET 0x006c /* ADC input pin configuration invert register */
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#define PIC32MX_ADC_BUF_OFFSET(n) (0x0070 + ((n) << 4))
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#define PIC32MX_ADC_BUF0_OFFSET 0x0070 /* ADC result word 0 */
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#define PIC32MX_ADC_BUF1_OFFSET 0x0080 /* ADC result word 1 */
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#define PIC32MX_ADC_BUF2_OFFSET 0x0090 /* ADC result word 2 */
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#define PIC32MX_ADC_BUF3_OFFSET 0x00a0 /* ADC result word 3 */
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#define PIC32MX_ADC_BUF4_OFFSET 0x00b0 /* ADC result word 4 */
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#define PIC32MX_ADC_BUF5_OFFSET 0x00c0 /* ADC result word 5 */
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#define PIC32MX_ADC_BUF6_OFFSET 0x00d0 /* ADC result word 6 */
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#define PIC32MX_ADC_BUF7_OFFSET 0x00e0 /* ADC result word 7 */
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#define PIC32MX_ADC_BUF8_OFFSET 0x00f0 /* ADC result word 8 */
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#define PIC32MX_ADC_BUF9_OFFSET 0x0100 /* ADC result word 9 */
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#define PIC32MX_ADC_BUF10_OFFSET 0x0110 /* ADC result word 10 */
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#define PIC32MX_ADC_BUF11_OFFSET 0x0120 /* ADC result word 11 */
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#define PIC32MX_ADC_BUF12_OFFSET 0x0130 /* ADC result word 12 */
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#define PIC32MX_ADC_BUF13_OFFSET 0x0140 /* ADC result word 13 */
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#define PIC32MX_ADC_BUF14_OFFSET 0x0150 /* ADC result word 14 */
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#define PIC32MX_ADC_BUF15_OFFSET 0x0160 /* ADC result word 15 */
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/* Register Addresses *******************************************************/
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#define PIC32MX_ADC_CON1 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CON1_OFFSET)
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#define PIC32MX_ADC_CON1CLR (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CON1CLR_OFFSET)
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#define PIC32MX_ADC_CON1SET (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CON1SET_OFFSET)
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#define PIC32MX_ADC_CON1INV (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CON1INV_OFFSET)
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#define PIC32MX_ADC_CON2 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CON2_OFFSET)
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#define PIC32MX_ADC_CON2CLR (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CON2CLR_OFFSET)
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#define PIC32MX_ADC_CON2SET (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CON2SET_OFFSET)
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#define PIC32MX_ADC_CON2INV (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CON2INV_OFFSET)
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#define PIC32MX_ADC_CON3 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CON3_OFFSET)
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#define PIC32MX_ADC_CON3CLR (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CON3CLR_OFFSET)
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#define PIC32MX_ADC_CON3SET (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CON3SET_OFFSET)
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#define PIC32MX_ADC_CON3INV (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CON3INV_OFFSET)
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#define PIC32MX_ADC_CHS (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CHS_OFFSET)
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#define PIC32MX_ADC_CHSCLR (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CHSCLR_OFFSET)
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#define PIC32MX_ADC_CHSSET (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CHSSET_OFFSET)
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#define PIC32MX_ADC_CHSINV (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CHSINV_OFFSET)
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#define PIC32MX_ADC_CSSL (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CSSL_OFFSET)
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#define PIC32MX_ADC_CSSLCLR (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CSSLCLR_OFFSET)
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#define PIC32MX_ADC_CSSLSET (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CSSLSET_OFFSET)
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#define PIC32MX_ADC_CSSLINV (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CSSLINV_OFFSET)
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#define PIC32MX_ADC_CFG (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CFG_OFFSET)
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#define PIC32MX_ADC_CFGCLR (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CFGCLR_OFFSET)
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#define PIC32MX_ADC_CFGSET (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CFGSET_OFFSET)
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#define PIC32MX_ADC_CFGINV (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CFGINV_OFFSET)
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#define PIC32MX_ADC_BUF(n) (PIC32MX_ADC_K1BASE+PIC32MX_ADC_BUF_OFFSET(n))
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#define PIC32MX_ADC_BUF0 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_BUF0_OFFSET)
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#define PIC32MX_ADC_BUF1 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_BUF1_OFFSET)
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#define PIC32MX_ADC_BUF2 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_BUF2_OFFSET)
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#define PIC32MX_ADC_BUF3 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_BUF3_OFFSET)
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#define PIC32MX_ADC_BUF4 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_BUF4_OFFSET)
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#define PIC32MX_ADC_BUF5 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_BUF5_OFFSET)
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#define PIC32MX_ADC_BUF6 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_BUF6_OFFSET)
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#define PIC32MX_ADC_BUF7 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_BUF7_OFFSET)
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#define PIC32MX_ADC_BUF8 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_BUF8_OFFSET)
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#define PIC32MX_ADC_BUF9 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_BUF9_OFFSET)
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#define PIC32MX_ADC_BUF10 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_BUF10_OFFSET)
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#define PIC32MX_ADC_BUF11 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_BUF11_OFFSET)
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#define PIC32MX_ADC_BUF12 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_BUF12_OFFSET)
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#define PIC32MX_ADC_BUF13 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_BUF13_OFFSET)
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#define PIC32MX_ADC_BUF14 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_BUF14_OFFSET)
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#define PIC32MX_ADC_BUF15 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_BUF15_OFFSET)
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/* Register Bit-Field Definitions *******************************************/
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/* ADC control register 1 */
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#define ADC_CON1_DONE (1 << 0) /* Bit 0: A/D conversion status */
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#define ADC_CON1_SAMP (1 << 1) /* Bit 1: ADC sample enable */
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#define ADC_CON1_ASAM (1 << 2) /* Bit 2: ADC sample auto start */
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#define ADC_CON1_CLRASAM (1 << 4) /* Bit 4: Stop conversion sequence */
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#define ADC_CON1_SSRC_SHIFT (5) /* Bits 5-7: Conversion trigger source select */
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#define ADC_CON1_SSRC_MASK (7 << ADC_CON1_SSRC_SHIFT)
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# define ADC_CON1_SSRC_SAMP (0 << ADC_CON1_SSRC_SHIFT) /* Clearing SAMP starts */
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# define ADC_CON1_SSRC_INT0 (1 << ADC_CON1_SSRC_SHIFT) /* INT0 transition starts */
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# define ADC_CON1_SSRC_TIMER3 (2 << ADC_CON1_SSRC_SHIFT) /* Timer3 match starts */
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# define ADC_CON1_SSRC_COUNT (7 << ADC_CON1_SSRC_SHIFT) /* Internal counter starts */
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#define ADC_CON1_FORM_SHIFT (8) /* Bits 8-10: Data output format */
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#define ADC_CON1_FORM_MASK (7 << ADC_CON1_FORM_SHIFT)
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# define ADC_CON1_FORM_UINT16 (0 << ADC_CON1_FORM_SHIFT) /* Integer 16-bit */
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# define ADC_CON1_FORM_SINT16 (1 << ADC_CON1_FORM_SHIFT) /* Signed integer 16-bit */
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# define ADC_CON1_FORM_FRAC16 (2 << ADC_CON1_FORM_SHIFT) /* Fractional 16-bit */
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# define ADC_CON1_FORM_SFRAC16 (3 << ADC_CON1_FORM_SHIFT) /* Signed fractional 16-bit */
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# define ADC_CON1_FORM_UINT32 (4 << ADC_CON1_FORM_SHIFT) /* Integer 32-bit */
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# define ADC_CON1_FORM_SINT32 (5 << ADC_CON1_FORM_SHIFT) /* Signed integer 32-bit */
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# define ADC_CON1_FORM_FRAC32 (6 << ADC_CON1_FORM_SHIFT) /* Fractional 32-bit */
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# define ADC_CON1_FORM_SFRAC32 (7 << ADC_CON1_FORM_SHIFT) /* Signed fractional 32-bit */
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#define ADC_CON1_SIDL (1 << 13) /* Bit 13: Stop in idle mode */
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#define ADC_CON1_FRZ (1 << 14) /* Bit 14: Freeze in debug exception mode */
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#define ADC_CON1_ON (1 << 15) /* Bit 14: ADC operating mode */
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/* ADC control register 2 */
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#define ADC_CON2_ALTS (1 << 0) /* Bit 0: Alternate input sample mode select */
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#define ADC_CON2_BUFM (1 << 1) /* Bit 1: ADC result buffer mode select */
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#define ADC_CON2_SMPI_SHIFT (2) /* Bits 2-5: Sample/sequences per interrupt */
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#define ADC_CON2_SMPI_MASK (15 << ADC_CON2_SMPI_SHIFT)
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# define ADC_CON2_SMPI(n) ((n-1) << ADC_CON2_SMPI_SHIFT) /* Interrupt after nth conversion */
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#define ADC_CON2_BUFS (1 << 7) /* Bit 7: Buffer fill status */
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#define ADC_CON2_CSCNA (1 << 10) /* Bit 10: Scan input selections */
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#define ADC_CON2_OFFCAL (1 << 12) /* Bit 12: Input offset calibration mode select */
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#define ADC_CON2_VCFG_SHIFT (13) /* Bits 13-15: Voltage reference configuration */
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#define ADC_CON2_VCFG_MASK (15 << ADC_CON2_VCFG_SHIFT)
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# define ADC_CON2_VCFG_AVDDAVSS (0 << ADC_CON2_VCFG_SHIFT) /* VR+=AVdd VR-=AVss */
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# define ADC_CON2_VCFG_VREFAVSS (1 << ADC_CON2_VCFG_SHIFT) /* VR+=VREF+ VR-=AVss */
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# define ADC_CON2_VCFG_AVDDVREF (2 << ADC_CON2_VCFG_SHIFT) /* VR+=AVdd VR-=VREF- */
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# define ADC_CON2_VCFG_VREFVREF (3 << ADC_CON2_VCFG_SHIFT) /* VR+=VREF+ VR-=VREF- */
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/* ADC control register 3 */
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#define ADC_CON3_ADCS_SHIFT (0) /* Bits 0-7: ADC conversion clock select */
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#define ADC_CON3_ADCS_MASK (0xff << ADC_CON3_ADCS_SHIFT)
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# define ADC_CON3_ADCS(n) ((((n)>>1)-1) << ADC_CON3_ADCS_SHIFT) /* n*Tpb = Tad, n=2,4,..,512 */
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#define ADC_CON3_SAMC_SHIFT (8) /* Bits 8-12: Auto-sample time bits */
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#define ADC_CON3_SAMC_MASK (31 << ADC_CON3_SAMC_SHIFT)
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# define ADC_CON3_SAMC(n) ((n) << ADC_CON3_SAMC_SHIFT) /* Tad = n, n=1..15 */
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#define ADC_CON3_ADRC (1 << 15) /* Bit 15: ADC conversion clock source */
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/* ADC input pin selection register */
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#define ADC_CHS_CH0SA_SHIFT (16) /* Bits 16-19: MUX A positive input select */
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#define ADC_CHS_CH0SA_MASK (15 << ADC_CHS_CH0SA_SHIFT)
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# define ADC_CHS_CH0SA(n) ((n) << ADC_CHS_CH0SA_SHIFT) /* Channel 0 positive input ANn, n=0..15 */
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#define ADC_CHS_CH0NA (1 << 23) /* Bit 23: MUX A negative input select */
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#define ADC_CHS_CH0SB_SHIFT (24) /* Bits 24-27: MUX B positive input select */
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#define ADC_CHS_CH0SB_MASK (15 << ADC_CHS_CH0SB_SHIFT)
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# define ADC_CHS_CH0SB(n) ((n) << ADC_CHS_CH0SB_SHIFT) /* Channel 0 positive input ANn, n=0..15 */
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#define ADC_CHS_CH0NB (1 << 31) /* Bit 31: MUX B negative input select */
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/* ADC sequentially scanned input register */
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#define ADC_CSSL(n) (1 << (n)) /* Bit n: xx n, n=0..15 */
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/* ADC input pin configuration register */
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#define ADC_CFG(n) (1 << (n)) /* Bit n: xx n, n=0..15 */
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/* ADC result word 0-15 -- 32-bits of ADC result data */
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/****************************************************************************
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* Public Types
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****************************************************************************/
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#ifndef __ASSEMBLY__
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/****************************************************************************
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* Inline Functions
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_ADC_H */
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