zhuyanlin 7b00c8bdb8 arch:xtensa: modify svcall to swint ... Reason: xtensa svcall only have level-1 interrupt level. Sush do not generate interrupt when up_irq_save. Software int can generate interrupt when up_irq_save. Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>		2022-02-22 14:06:24 -03:00
..
esp32	arch/xtensa/esp32: Remove the QEMU special case when initializing the	2022-02-03 16:18:09 -03:00
esp32s2	include: fix double include pre-processor guards	2022-01-16 11:11:14 -03:00
esp32s3	xtensa: Add initial support for ESP32-S3	2022-01-27 13:46:50 -03:00
lx6
lx7	xtensa: Add initial support for ESP32-S3	2022-01-27 13:46:50 -03:00
xtensa	include: fix double include pre-processor guards	2022-01-16 11:11:14 -03:00
.gitignore
arch.h	arch/xtensa: Remove FAR qualifier for Xtensa-specific files	2021-09-22 08:16:01 -03:00
elf.h
inttypes.h	arch: Omni Hoverboards: update licenses to Apache	2021-09-28 04:37:38 -07:00
irq.h	xtensa_context.S: Save and restore SCOMPARE1 when necessary.	2021-10-14 06:32:17 -03:00
limits.h
loadstore.h
setjmp.h	xtensa: add setjmp.h include file	2021-11-17 02:23:45 -06:00
simcall.h
spinlock.h
stdarg.h
syscall.h	arch:xtensa: modify svcall to swint	2022-02-22 14:06:24 -03:00
types.h	arch: Add _wchar_t typedef like other basic types	2021-12-09 16:57:23 +09:00