120 lines
5.6 KiB
C
120 lines
5.6 KiB
C
/****************************************************************************
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* arch/arm/include/dm320/irq.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* This file should never be included directly but, rather,
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* only indirectly through nuttx/irq.h
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*/
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#ifndef __ARCH_ARM_INCLUDE_DM320_IRQ_H
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#define __ARCH_ARM_INCLUDE_DM320_IRQ_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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/****************************************************************************
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* Pre-processor Prototypes
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****************************************************************************/
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/* DM320 Interrupts */
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#define DM320_IRQ_TMR0 0 /* IRQ0: Timer 0 Interrupt */
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#define DM320_IRQ_TMR1 1 /* IRQ1: Timer 1 Interrupt */
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#define DM320_IRQ_TMR2 2 /* IRQ2: Timer 2 Interrupt (CCD timer 0) */
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#define DM320_IRQ_TMR3 3 /* IRQ3: Timer 3 Interrupt (CCD timer 1) */
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#define DM320_IRQ_CCDVD0 4 /* IRQ4: CCD VD Interrupt #0 */
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#define DM320_IRQ_CCDVD1 5 /* IRQ5: CCD VD Interrupt #1 */
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#define DM320_IRQ_CCDWEN 6 /* IRQ6: CCD WEN Interrupt */
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#define DM320_IRQ_VENC 7 /* IRQ7: Video Encoder Interrupt */
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#define DM320_IRQ_SP0 8 /* IRQ8: Serial Port 0 Interrupt (with DMA) */
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#define DM320_IRQ_SP1 9 /* IRQ9: Serial Port 1 Interrupt */
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#define DM320_IRQ_EXTHOST 10 /* IRQ10: External host interrupt */
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#define DM320_IRQ_IMGBUF 11 /* IRQ11: Image Buffer */
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#define DM320_IRQ_UART0 12 /* IRQ12: UART0 Interrupt */
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#define DM320_IRQ_UART1 13 /* IRQ13: UART1 Interrupt */
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#define DM320_IRQ_USB0 14 /* IRQ14: USB 0 Interrupt (DMA) */
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#define DM320_IRQ_USB1 15 /* IRQ15: USB 1 Interrupt (Core) */
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#define DM320_IRQ_VLYNQ 16 /* IRQ16: VLYNQ Interrupt */
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#define DM320_IRQ_MTC0 17 /* IRQ17: Memory Traffic Controller 0 (DMA) */
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#define DM320_IRQ_MTC1 18 /* IRQ18: Memory Traffic Controller 1 (CFC_RDY) */
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#define DM320_IRQ_MMCSD0 19 /* IRQ19: MMC/SD or MS 0 Interrupt */
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#define DM320_IRQ_MMCSD1 20 /* IRQ20: MMC/SD or MS 1 Interrupt */
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#define DM320_IRQ_EXT0 21 /* IRQ21: External Interrupt #0 (GIO0) */
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#define DM320_IRQ_EXT1 22 /* IRQ22: External Interrupt #1 (GIO1) */
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#define DM320_IRQ_EXT2 23 /* IRQ23: External Interrupt #2 (GIO2) */
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#define DM320_IRQ_EXT3 24 /* IRQ24: External Interrupt #3 (GIO3) */
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#define DM320_IRQ_EXT4 25 /* IRQ25: External Interrupt #4 (GIO4) */
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#define DM320_IRQ_EXT5 26 /* IRQ26: External Interrupt #5 (GIO5) */
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#define DM320_IRQ_EXT6 27 /* IRQ27: External Interrupt #6 (GIO6) */
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#define DM320_IRQ_EXT7 28 /* IRQ28: External Interrupt #7 (GIO7) */
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#define DM320_IRQ_EXT8 29 /* IRQ29: External Interrupt #8 (GIO8) */
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#define DM320_IRQ_EXT9 30 /* IRQ30: External Interrupt #9 (GIO9) */
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#define DM320_IRQ_EXT10 31 /* IRQ31: External Interrupt #10 (GIO10) */
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#define DM320_IRQ_EXT11 32 /* IRQ32: External Interrupt #11 (GIO11) */
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#define DM320_IRQ_EXT12 33 /* IRQ33: External Interrupt #12 (GIO12) */
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#define DM320_IRQ_EXT13 34 /* IRQ34: External Interrupt #13 (GIO13) */
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#define DM320_IRQ_EXT14 35 /* IRQ35: External Interrupt #14 (GIO14) */
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#define DM320_IRQ_EXT15 36 /* IRQ36: External Interrupt #15 (GIO15) */
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#define DM320_IRQ_PREV0 37 /* IRQ37: Preview Engine 0 (Preview Over) */
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#define DM320_IRQ_PREV1 38 /* IRQ38: Preview Engine 1 (Preview Historgram Over) */
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#define DM320_IRQ_WDT 39 /* IRQ39: Watchdog Timer Interrupt */
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#define DM320_IRQ_I2C 40 /* IRQ40: I2C Interrupt */
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#define DM320_IRQ_CLKC 41 /* IRQ41: Clock controller Interrupt (wake up) */
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#define DM320_IRQ_E2ICE 42 /* IRQ42: Embedded ICE Interrupt */
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#define DM320_IRQ_ARMCOMRX 43 /* IRQ43: ARMCOMM Receive Interrupt */
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#define DM320_IRQ_ARMCOMTX 44 /* IRQ44: ARMCOMM Transmit Interrupt */
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#define DM320_IRQ_RSV 45 /* IRQ45: Reserved Interrupt */
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#define DM320_IRQ_SYSTIMER DM320_IRQ_TMR0
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#define NR_IRQS (DM320_IRQ_RSV+1)
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/****************************************************************************
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* Inline functions
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif
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#endif /* __ARCH_ARM_INCLUDE_DM320_IRQ_H */
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