71 lines
3.1 KiB
C
71 lines
3.1 KiB
C
/****************************************************************************
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* arch/arm/include/s32k1xx/chip.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_S32K1XX_CHIP_H
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#define __ARCH_ARM_INCLUDE_S32K1XX_CHIP_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************
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* Pre-processor Prototypes
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****************************************************************************/
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/* NVIC priority levels *****************************************************/
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/* Each priority field holds a priority value. The lower the value, the
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* greater the priority of the corresponding interrupt.
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*/
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#if defined(CONFIG_ARCH_CORTEXM4)
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/* The Cortex-M4F core supports 16 programmable interrupt priority levels. */
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# define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits[7:4] set is minimum priority */
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# define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
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# define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
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# define NVIC_SYSH_PRIORITY_STEP 0x10 /* Steps between priorities */
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#elif defined(CONFIG_ARCH_ARMV6M)
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/* The Cortex-M0+ core supports 4 programmable interrupt priority levels. */
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# define NVIC_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:4] set is minimum priority */
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# define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
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# define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
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# define NVIC_SYSH_PRIORITY_STEP 0x40 /* Steps between priorities */
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#endif
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#endif /* __ARCH_ARM_INCLUDE_S32K1XX_CHIP_H */
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