125 lines
6.2 KiB
C
125 lines
6.2 KiB
C
/****************************************************************************
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* arch/arm/include/tiva/cc13x0_irq.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_TIVA_CC13X0_IRQ_H
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#define __ARCH_ARM_INCLUDE_TIVA_CC13X0_IRQ_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************
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* Pre-processor Prototypes
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****************************************************************************/
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/* IRQ numbers. The IRQ number corresponds vector number and hence map
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* directly to bits in the NVIC. This does, however, waste several words of
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* memory in the IRQ to handle mapping tables.
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*/
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/* External interrupts (vectors >= 16) */
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#define TIVA_IRQ_AON_GPIO_EDGE (16) /* Edge detect event from IOC */
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#define TIVA_IRQ_I2C (17) /* Interrupt event from I2C */
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#define TIVA_IRQ_RFC_CPE_1 (18) /* Combined Interrupt for CPE
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* Generated events */
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#define TIVA_IRQ_AON_RTC (20) /* Event from AON_RTC */
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#define TIVA_IRQ_UART0 (21) /* UART0 combined interrupt */
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#define TIVA_IRQ_AUX_SWEV0 (22) /* AUX software event 0 */
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#define TIVA_IRQ_SSI0 (23) /* SSI0 combined interrupt */
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#define TIVA_IRQ_SSI1 (24) /* SSI1 combined interrupt */
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#define TIVA_IRQ_RFC_CPE_0 (25) /* Combined Interrupt for CPE
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* Generated events */
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#define TIVA_IRQ_RFC_HW (26) /* Combined RFC hardware interrupt */
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#define TIVA_IRQ_RFC_CMD_ACK (27) /* RFC Doorbell Command
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* Acknowledgement Interrupt */
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#define TIVA_IRQ_I2S (28) /* Interrupt event from I2S */
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#define TIVA_IRQ_AUX_SWEV1 (29) /* AUX software event 1 */
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#define TIVA_IRQ_WDT (30) /* Watchdog interrupt event */
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#define TIVA_IRQ_GPT0A (31) /* GPT0A interrupt event */
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#define TIVA_IRQ_GPT0B (32) /* GPT0B interrupt event */
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#define TIVA_IRQ_GPT1A (33) /* GPT1A interrupt event */
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#define TIVA_IRQ_GPT1B (34) /* GPT1B interrupt event */
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#define TIVA_IRQ_GPT2A (35) /* GPT2A interrupt event */
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#define TIVA_IRQ_GPT2B (36) /* GPT2B interrupt event */
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#define TIVA_IRQ_GPT3A (37) /* GPT3A interrupt event */
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#define TIVA_IRQ_GPT3B (38) /* GPT3B interrupt event */
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#define TIVA_IRQ_CRYPTO_RESULT_AVAIL (39) /* CRYPTO result available interrupt
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* event */
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#define TIVA_IRQ_DMA_DONE (40) /* Combined DMA done */
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#define TIVA_IRQ_DMA_ERR (41) /* DMA bus error */
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#define TIVA_IRQ_FLASH (42) /* FLASH controller error event */
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#define TIVA_IRQ_SWEV0 (43) /* Software event 0 */
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#define TIVA_IRQ_AUX (44) /* AUX combined event */
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#define TIVA_IRQ_AON_PROG0 (45) /* AON programmable event 0 */
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#define TIVA_IRQ_PROG0 (46) /* Programmable Interrupt 0 */
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#define TIVA_IRQ_AUX_COMPA (47) /* AUX Compare A event */
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#define TIVA_IRQ_AUX_ADC (48) /* AUX ADC interrupt event */
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#define TIVA_IRQ_TRNG (49) /* TRNG Interrupt event */
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#define NR_IRQS (50) /* Number of interrupt vectors */
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#define TIVA_IRQ_NEXTINT (NR_IRQS - 16)
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/* GPIO IRQs -- Up to 31 interrupts, one for each supported pin */
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#if defined(CONFIG_TIVA_GPIOIRQS)
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# define TIVA_IRQ_DIO_0 (NR_IRQS + 0)
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# define TIVA_IRQ_DIO_1 (NR_IRQS + 1)
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# define TIVA_IRQ_DIO_2 (NR_IRQS + 2)
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# define TIVA_IRQ_DIO_3 (NR_IRQS + 3)
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# define TIVA_IRQ_DIO_4 (NR_IRQS + 4)
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# define TIVA_IRQ_DIO_5 (NR_IRQS + 5)
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# define TIVA_IRQ_DIO_6 (NR_IRQS + 6)
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# define TIVA_IRQ_DIO_7 (NR_IRQS + 7)
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# define TIVA_IRQ_DIO_8 (NR_IRQS + 8)
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# define TIVA_IRQ_DIO_9 (NR_IRQS + 9)
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# define TIVA_IRQ_DIO_10 (NR_IRQS + 10)
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# define TIVA_IRQ_DIO_11 (NR_IRQS + 11)
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# define TIVA_IRQ_DIO_12 (NR_IRQS + 12)
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# define TIVA_IRQ_DIO_13 (NR_IRQS + 13)
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# define TIVA_IRQ_DIO_14 (NR_IRQS + 14)
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# define TIVA_IRQ_DIO_15 (NR_IRQS + 15)
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# define TIVA_IRQ_DIO_16 (NR_IRQS + 16)
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# define TIVA_IRQ_DIO_17 (NR_IRQS + 17)
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# define TIVA_IRQ_DIO_18 (NR_IRQS + 18)
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# define TIVA_IRQ_DIO_19 (NR_IRQS + 19)
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# define TIVA_IRQ_DIO_20 (NR_IRQS + 20)
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# define TIVA_IRQ_DIO_21 (NR_IRQS + 21)
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# define TIVA_IRQ_DIO_22 (NR_IRQS + 22)
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# define TIVA_IRQ_DIO_23 (NR_IRQS + 23)
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# define TIVA_IRQ_DIO_24 (NR_IRQS + 24)
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# define TIVA_IRQ_DIO_25 (NR_IRQS + 25)
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# define TIVA_IRQ_DIO_26 (NR_IRQS + 26)
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# define TIVA_IRQ_DIO_27 (NR_IRQS + 27)
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# define TIVA_IRQ_DIO_28 (NR_IRQS + 28)
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# define TIVA_IRQ_DIO_29 (NR_IRQS + 29)
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# define TIVA_IRQ_DIO_30 (NR_IRQS + 30)
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# define TIVA_IRQ_DIO_31 (NR_IRQS + 31)
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# define _NGPIOIRQS (NR_IRQS + 32)
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#else
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# define _NGPIOIRQS NR_IRQS
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#endif
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#define NR_GPIO_IRQS (_NGPIOTIRQS - NR_IRQS)
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#endif /* __ARCH_ARM_INCLUDE_TIVA_CC13X0_IRQ_H */
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