1005 lines
22 KiB
Plaintext
1005 lines
22 KiB
Plaintext
#
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# For a description of the syntax of this configuration file,
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# see the file kconfig-language.txt in the NuttX tools repository.
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#
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if ARCH_CHIP_IMXRT
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comment "i.MX RT Configuration Options"
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choice
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prompt "i.MX RT Chip Selection"
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default ARCH_CHIP_MIMXRT1052DVL6A
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depends on ARCH_CHIP_IMXRT
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config ARCH_CHIP_MIMXRT1021CAG4A
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bool "MIMXRT1021CAG4A"
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select ARCH_FAMILY_MIMXRT1021C
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config ARCH_CHIP_MIMXRT1021CAF4A
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bool "MIMXRT1021CAF4A"
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select ARCH_FAMILY_MIMXRT1021C
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config ARCH_CHIP_MIMXRT1021DAF5A
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bool "MIMXRT1021DAF5A"
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select ARCH_FAMILY_MIMXRT1021D
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config ARCH_CHIP_MIMXRT1021DAG5A
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bool "MIMXRT1021DAG5A"
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select ARCH_FAMILY_MIMXRT1021D
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config ARCH_CHIP_MIMXRT1051DVL6A
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bool "MIMXRT1051DVL6A"
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select ARCH_FAMILY_MXRT105xDVL6A
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config ARCH_CHIP_MIMXRT1051CVL5A
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bool "MIMXRT1051CVL5A"
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select ARCH_FAMILY_IMIMXRT105xCVL5A
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config ARCH_CHIP_MIMXRT1052DVL6A
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bool "MIMXRT1052DVL6A"
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select ARCH_FAMILY_MXRT105xDVL6A
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config ARCH_CHIP_MIMXRT1052CVL5A
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bool "MIMXRT1052DVL5A"
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select ARCH_FAMILY_MIMXRT1052CVL5A
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config ARCH_CHIP_MIMXRT1061DVL6A
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bool "MIMXRT1061DVL6A"
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select ARCH_FAMILY_MXRT106xDVL6A
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config ARCH_CHIP_MIMXRT1061CVL5A
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bool "MIMXRT1061CVL5A"
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select ARCH_FAMILY_IMIMXRT106xCVL5A
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config ARCH_CHIP_MIMXRT1062DVL6A
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bool "MIMXRT1062DVL6A"
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select ARCH_FAMILY_MXRT106xDVL6A
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config ARCH_CHIP_MIMXRT1062CVL5A
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bool "MIMXRT1062DVL6A"
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select ARCH_FAMILY_MIMXRT1062CVL5A
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endchoice # i.MX RT Chip Selection
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# i.MX RT Families
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config ARCH_FAMILY_MIMXRT1021D
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bool
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default n
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select ARCH_FAMILY_IMXRT102x
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---help---
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i.MX RT1020 Crossover Processors for Consumer Products
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config ARCH_FAMILY_MIMXRT1021C
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bool
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default n
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select ARCH_FAMILY_IMXRT102x
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---help---
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i.MX RT1020 Crossover Processors for Industrial Products
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config ARCH_FAMILY_IMXRT102x
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bool
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default n
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select ARCH_HAVE_FPU
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select ARCH_HAVE_DPFPU # REVISIT
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select ARMV7M_HAVE_ICACHE
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select ARMV7M_HAVE_DCACHE
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select ARMV7M_HAVE_ITCM
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select ARMV7M_HAVE_DTCM
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config ARCH_FAMILY_MXRT105xDVL6A
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bool
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default n
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select ARCH_FAMILY_IMXRT105x
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---help---
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i.MX RT1050 Crossover Processors for Consumer Products
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config ARCH_FAMILY_MIMXRT1052CVL5A
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bool
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default n
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select ARCH_FAMILY_IMXRT105x
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---help---
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i.MX RT1050 Crossover Processors for Industrial Products
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config ARCH_FAMILY_IMXRT105x
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bool
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default n
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select ARCH_HAVE_FPU
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select ARCH_HAVE_DPFPU # REVISIT
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select ARMV7M_HAVE_ICACHE
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select ARMV7M_HAVE_DCACHE
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select ARMV7M_HAVE_ITCM
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select ARMV7M_HAVE_DTCM
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select IMXRT_HAVE_LCD
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config ARCH_FAMILY_MXRT106xDVL6A
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bool
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default n
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select ARCH_FAMILY_IMXRT106x
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---help---
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i.MX RT1060 Crossover Processors for Consumer Products
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config ARCH_FAMILY_MIMXRT1062CVL5A
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bool
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default n
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select ARCH_FAMILY_IMXRT106x
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---help---
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i.MX RT1056 Crossover Processors for Industrial Products
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config ARCH_FAMILY_IMXRT106x
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bool
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default n
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select ARCH_HAVE_FPU
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select ARCH_HAVE_DPFPU # REVISIT
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select ARMV7M_HAVE_ICACHE
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select ARMV7M_HAVE_DCACHE
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select ARMV7M_HAVE_ITCM
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select ARMV7M_HAVE_DTCM
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select IMXRT_HIGHSPEED_GPIO
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select IMXRT_HAVE_LCD
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# Peripheral support
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config IMXRT_USDHC
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bool
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default n
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config IMXRT_HAVE_LPUART
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bool
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default n
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config IMXRT_LPI2C
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bool
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default n
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config IMXRT_LPSPI
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bool
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default n
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config IMXRT_HIGHSPEED_GPIO
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bool
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default n
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config IMXRT_HAVE_LCD
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bool
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default n
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config IMXRT_SEMC_INIT_DONE
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bool
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default n
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menu "i.MX RT Peripheral Selection"
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config IMXRT_EDMA
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bool "eDMA"
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default n
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select ARCH_DMA
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config IMXRT_USBOTG
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bool "USB EHCI"
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default n
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select USBHOST_HAVE_ASYNCH
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select USBHOST_ASYNCH
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config IMXRT_ENET
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bool "Ethernet"
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default n
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select ARCH_HAVE_PHY
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select ARCH_PHY_INTERRUPT
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select ARCH_HAVE_NETDEV_STATISTICS
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config IMXRT_LCD
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bool "LCD controller"
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default n
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depends on IMXRT_HAVE_LCD
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menu "FlexIO Peripherals"
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endmenu # FlexIO Peripherals
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menu "LPUART Peripherals"
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config IMXRT_LPUART1
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bool "LPUART1"
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default n
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select LPUART1_SERIALDRIVER
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select ARCH_HAVE_SERIAL_TERMIOS
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select IMXRT_HAVE_LPUART
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config IMXRT_LPUART2
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bool "LPUART2"
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default n
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select LPUART2_SERIALDRIVER
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select ARCH_HAVE_SERIAL_TERMIOS
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select IMXRT_HAVE_LPUART
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config IMXRT_LPUART3
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bool "LPUART3"
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default n
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select LPUART3_SERIALDRIVER
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select ARCH_HAVE_SERIAL_TERMIOS
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select IMXRT_HAVE_LPUART
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config IMXRT_LPUART4
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bool "LPUART4"
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default n
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select LPUART4_SERIALDRIVER
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select ARCH_HAVE_SERIAL_TERMIOS
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select IMXRT_HAVE_LPUART
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config IMXRT_LPUART5
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bool "LPUART5"
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default n
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select LPUART5_SERIALDRIVER
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select ARCH_HAVE_SERIAL_TERMIOS
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select IMXRT_HAVE_LPUART
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config IMXRT_LPUART6
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bool "LPUART6"
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default n
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select LPUART6_SERIALDRIVER
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select ARCH_HAVE_SERIAL_TERMIOS
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select IMXRT_HAVE_LPUART
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config IMXRT_LPUART7
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bool "LPUART7"
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default n
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select LPUART7_SERIALDRIVER
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select ARCH_HAVE_SERIAL_TERMIOS
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select IMXRT_HAVE_LPUART
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config IMXRT_LPUART8
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bool "LPUART8"
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default n
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select LPUART8_SERIALDRIVER
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select ARCH_HAVE_SERIAL_TERMIOS
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select IMXRT_HAVE_LPUART
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endmenu # LPUART Peripherals
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menu "LPUART Configuration"
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depends on IMXRT_HAVE_LPUART
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config IMXRT_LPUART_INVERT
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bool "Signal Invert Support"
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default n
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depends on IMXRT_HAVE_LPUART
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---help---
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Enable signal inversion UART support. The option enables support for the
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TIOCSINVERT ioctl in the IMXRT serial driver.
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endmenu # LPUART Configuration
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menu "LPI2C Peripherals"
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menuconfig IMXRT_LPI2C1
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bool "LPI2C1"
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default n
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select IMXRT_LPI2C
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if IMXRT_LPI2C1
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config LPI2C1_BUSYIDLE
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int "Bus idle timeout period in clock cycles"
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default 0
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config LPI2C1_FILTSCL
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int "I2C master digital glitch filters for SCL input in clock cycles"
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default 0
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config LPI2C1_FILTSDA
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int "I2C master digital glitch filters for SDA input in clock cycles"
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default 0
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endif # IMXRT_LPI2C1
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menuconfig IMXRT_LPI2C2
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bool "LPI2C2"
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default n
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select IMXRT_LPI2C
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if IMXRT_LPI2C2
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config LPI2C2_BUSYIDLE
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int "Bus idle timeout period in clock cycles"
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default 0
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config LPI2C2_FILTSCL
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int "I2C master digital glitch filters for SCL input in clock cycles"
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default 0
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config LPI2C2_FILTSDA
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int "I2C master digital glitch filters for SDA input in clock cycles"
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default 0
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endif # IMXRT_LPI2C2
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menuconfig IMXRT_LPI2C3
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bool "LPI2C3"
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default n
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select IMXRT_LPI2C
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if IMXRT_LPI2C3
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config LPI2C3_BUSYIDLE
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int "Bus idle timeout period in clock cycles"
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default 0
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config LPI2C3_FILTSCL
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int "I2C master digital glitch filters for SCL input in clock cycles"
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default 0
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config LPI2C3_FILTSDA
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int "I2C master digital glitch filters for SDA input in clock cycles"
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default 0
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endif # IMXRT_LPI2C3
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menuconfig IMXRT_LPI2C4
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bool "LPI2C4"
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default n
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select IMXRT_LPI2C
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if IMXRT_LPI2C4
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config LPI2C4_BUSYIDLE
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int "Bus idle timeout period in clock cycles"
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default 0
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config LPI2C4_FILTSCL
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int "I2C master digital glitch filters for SCL input in clock cycles"
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default 0
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config LPI2C4_FILTSDA
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int "I2C master digital glitch filters for SDA input in clock cycles"
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default 0
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endif # IMXRT_LPI2C4
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endmenu # LPI2C Peripherals
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menu "LPSPI Peripherals"
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menuconfig IMXRT_LPSPI1
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bool "LPSPI1"
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default n
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select IMXRT_LPSPI
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config IMXRT_LPSPI2
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bool "LPSPI2"
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default n
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select IMXRT_LPSPI
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config IMXRT_LPSPI3
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bool "LPSPI3"
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default n
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select IMXRT_LPSPI
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config IMXRT_LPSPI4
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bool "LPSPI4"
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default n
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select IMXRT_LPSPI
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endmenu # LPSPI Peripherals
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config IMXRT_SEMC
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bool "Smart External Memory Controller (SEMC)"
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default n
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config IMXRT_SNVS_LPSRTC
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bool "LP SRTC"
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default n
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select IMXRT_SNVS_HPRTC
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config IMXRT_SNVS_HPRTC
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bool "HP RTC"
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default n
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config IMXRT_USDHC1
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bool "USDHC1"
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default n
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select ARCH_HAVE_SDIO
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select IMXRT_USDHC
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---help---
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Support USDHC host controller 1
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config IMXRT_USDHC2
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bool "USDHC2"
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default n
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select ARCH_HAVE_SDIO
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select IMXRT_USDHC
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---help---
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Support USDHC host controller 2
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endmenu # i.MX RT Peripheral Selection
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menuconfig IMXRT_GPIO_IRQ
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bool "GPIO Interrupt Support"
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default n
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if IMXRT_GPIO_IRQ
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config IMXRT_GPIO1_0_15_IRQ
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bool "GPIO1 Pins 0-15 interrupts"
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default n
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config IMXRT_GPIO1_16_31_IRQ
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bool "GPIO1 Pins 16-31 interrupts"
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default n
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config IMXRT_GPIO2_0_15_IRQ
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bool "GPIO2 Pins 0-15 interrupts"
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default n
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config IMXRT_GPIO2_16_31_IRQ
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bool "GPIO2 Pins 16-31 interrupts"
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default n
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config IMXRT_GPIO3_0_15_IRQ
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bool "GPIO3 Pins 0-15 interrupts"
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default n
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config IMXRT_GPIO3_16_31_IRQ
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bool "GPIO3 Pins 16-31 interrupts"
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default n
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config IMXRT_GPIO4_0_15_IRQ
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bool "GPIO4 Pins 0-15 interrupts"
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default n
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config IMXRT_GPIO4_16_31_IRQ
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bool "GPIO4 Pins 16-31 interrupts"
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default n
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config IMXRT_GPIO5_0_15_IRQ
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bool "GPIO5 Pins 0-15 interrupts"
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default n
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config IMXRT_GPIO5_16_31_IRQ
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bool "GPIO5 Pins 16-31 interrupts"
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default n
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config IMXRT_GPIO6_0_15_IRQ
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bool "GPIO6 Pins 0-15 interrupts"
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default n
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depends on IMXRT_HIGHSPEED_GPIO
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config IMXRT_GPIO6_16_31_IRQ
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bool "GPIO6 Pins 16-31 interrupts"
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default n
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depends on IMXRT_HIGHSPEED_GPIO
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config IMXRT_GPIO7_0_15_IRQ
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bool "GPIO7 Pins 0-15 interrupts"
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default n
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depends on IMXRT_HIGHSPEED_GPIO
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config IMXRT_GPIO7_16_31_IRQ
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bool "GPIO7 Pins 16-31 interrupts"
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default n
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depends on IMXRT_HIGHSPEED_GPIO
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config IMXRT_GPIO8_0_15_IRQ
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bool "GPIO8 Pins 0-15 interrupts"
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default n
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depends on IMXRT_HIGHSPEED_GPIO
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config IMXRT_GPIO8_16_31_IRQ
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bool "GPIO8 Pins 16-31 interrupts"
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default n
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depends on IMXRT_HIGHSPEED_GPIO
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config IMXRT_GPIO9_0_15_IRQ
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bool "GPIO9 Pins 0-15 interrupts"
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default n
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depends on IMXRT_HIGHSPEED_GPIO
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config IMXRT_GPIO9_16_31_IRQ
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bool "GPIO9 Pins 16-31 interrupts"
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default n
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depends on IMXRT_HIGHSPEED_GPIO
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endif # IMXRT_GPIO_IRQ
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menu "Ethernet Configuration"
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depends on IMXRT_ENET
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config MXRT_ENET_NRXBUFFERS
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int "Number Rx buffers"
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default 6
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config IMXRT_ENET_NTXBUFFERS
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int "Number Tx buffers"
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default 2
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config IMXRT_ENET_ENHANCEDBD
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bool # not optional
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default n
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config IMXRT_ENET_NETHIFS
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int # Not optional
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default 1
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config IMXRT_ENET_PHYINIT
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bool "Board-specific PHY Initialization"
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default n
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---help---
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Some boards require specialized initialization of the PHY before it
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can be used. This may include such things as configuring GPIOs,
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resetting the PHY, etc. If CONFIG_IMXRT_ENET_PHYINIT is defined in
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the configuration then the board specific logic must provide
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imxrt_phy_boardinitialize(); The i.MXRT ENET driver will call this
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function one time before it first uses the PHY.
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endmenu # IMXRT_ENET
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menu "Memory Configuration"
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config IMXRT_DTCM
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bool "Enable DTCM"
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default n
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depends on !IMXRT_OCRAM_PRIMARY && EXPERIMENTAL
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config IMXRT_ITCM
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bool "Enable ITCM"
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default n
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depends on !IMXRT_OCRAM_PRIMARY && EXPERIMENTAL
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config IMXRT_SEMC_SDRAM
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bool "External SDRAM installed"
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default n
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depends on IMXRT_SEMC
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if IMXRT_SEMC_SDRAM
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config IMXRT_SDRAM_START
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hex "SDRAM start address"
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default 0x10000000
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config IMXRT_SDRAM_SIZE
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int "SDRAM size (bytes)"
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default 268435456
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endif # IMXRT_SEMC_SDRAM
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config IMXRT_SEMC_SRAM
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bool "External SRAM installed"
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default n
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depends on IMXRT_SEMC
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if IMXRT_SEMC_SRAM
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config IMXRT_SRAM_START
|
|
hex "SRAM start address"
|
|
default 0x10000000
|
|
|
|
config IMXRT_SRAM_SIZE
|
|
int "SRAM size (bytes)"
|
|
default 268435456
|
|
|
|
endif # IMXRT_SRAM_SIZE
|
|
|
|
config IMXRT_SEMC_NOR
|
|
bool "External NOR FLASH installed"
|
|
default n
|
|
depends on IMXRT_SEMC
|
|
|
|
choice
|
|
prompt "i.MX RT Boot Configuration"
|
|
default IMXRT_BOOT_NOR if IMXRT_SEMC_NOR
|
|
default IMXRT_BOOT_SDRAM if IMXRT_SEMC_SDRAM && !IMXRT_SEMC_NOR
|
|
default IMXRT_BOOT_SRAM if IMXRT_SEMC_SRAM && !IMXRT_SEMC_SDRAM && !IMXRT_SEMC_NOR
|
|
default IMXRT_BOOT_OCRAM if !IMXRT_SEMC_SRAM && !IMXRT_SEMC_SDRAM && !IMXRT_SEMC_NOR
|
|
---help---
|
|
The startup code needs to know if the code is running from internal
|
|
OCRAM, external SDRAM, external NOR, or external SDRAM in order to
|
|
initialize properly. Note that the boot device is not known for
|
|
cases where the code is copied into RAM by a bootloader.
|
|
|
|
config IMXRT_BOOT_OCRAM
|
|
bool "Running from internal OCRAM"
|
|
select BOOT_RUNFROMISRAM
|
|
|
|
config IMXRT_BOOT_SDRAM
|
|
bool "Running from external SDRAM"
|
|
select BOOT_RUNFROMSDRAM
|
|
depends on IMXRT_SEMC_SDRAM
|
|
|
|
config IMXRT_BOOT_NOR
|
|
bool "Running from external NOR FLASH"
|
|
select BOOT_RUNFROMFLASH
|
|
depends on IMXRT_SEMC_NOR
|
|
|
|
config IMXRT_BOOT_SRAM
|
|
bool "Running from external SRAM"
|
|
select BOOT_RUNFROMEXTSRAM
|
|
depends on IMXRT_SEMC_SRAM
|
|
|
|
endchoice # i.MX RT Boot Configuration
|
|
|
|
choice
|
|
prompt "i.MX RT Primary RAM"
|
|
default IMXRT_OCRAM_PRIMARY
|
|
---help---
|
|
The primary RAM is the RAM that contains the system BLOB's .data and
|
|
.bss. The unused portion of the primary RAM will automatically be
|
|
added to the system heap.
|
|
|
|
config IMXRT_OCRAM_PRIMARY
|
|
bool "Internal OCRAM primary"
|
|
|
|
config IMXRT_SDRAM_PRIMARY
|
|
bool "External SDRAM primary"
|
|
depends on IMXRT_SEMC_SDRAM
|
|
|
|
config IMXRT_SRAM_PRIMARY
|
|
bool "External SRAM primary"
|
|
depends on IMXRT_SEMC_SRAM
|
|
|
|
endchoice # i.MX RT Primary RAM
|
|
|
|
menu "i.MX RT Heap Configuration"
|
|
|
|
config IMXRT_OCRAM_HEAP
|
|
bool "Add OCRAM to heap"
|
|
depends on !IMXRT_OCRAM_PRIMARY
|
|
---help---
|
|
Select to add the entire OCRAM to the heap
|
|
|
|
config IMXRT_SDRAM_HEAP
|
|
bool "Add SDRAM to heap"
|
|
depends on IMXRT_SEMC_SDRAM && !IMXRT_SDRAM_PRIMARY
|
|
---help---
|
|
Add a region of SDRAM to the heap. A region of SDRAM will be added
|
|
to the heap that starts at (CONFIG_IMXRT_SDRAM_START +
|
|
CONFIG_IMXRT_SDRAM_HEAPOFFSET) and extends up to
|
|
(CONFIG_IMXRT_SDRAM_START + CONFIG_IMXRT_SDRAM_SIZE). Note that the
|
|
START is the actual start of SDRAM but SIZE is not necessarily the
|
|
actual SIZE.
|
|
|
|
config IMXRT_SDRAM_HEAPOFFSET
|
|
hex "SDRAM heap offset"
|
|
default 0x0
|
|
depends on IMXRT_SDRAM_HEAP
|
|
---help---
|
|
Used to reserve memory at the beginning of SDRAM for, as an example,
|
|
a framebuffer.
|
|
|
|
config IMXRT_SRAM_HEAP
|
|
bool "Add SRAM to heap"
|
|
depends on IMXRT_SEMC_SRAM && !IMXRT_SRAM_PRIMARY
|
|
---help---
|
|
Add a region of SRAM to the heap. A region of SDRAM will be added
|
|
to the heap that starts at (CONFIG_IMXRT_SRAM_START +
|
|
CONFIG_IMXRT_SRAM_HEAPOFFSET) and extends up to
|
|
(CONFIG_IMXRT_SRAM_START + CONFIG_IMXRT_SRAM_SIZE). Note that the
|
|
START is the actual start of SRAM but SIZE is not necessarily the
|
|
actual SIZE.
|
|
|
|
config IMXRT_SRAM_HEAPOFFSET
|
|
hex "SRAM heap offset"
|
|
default 0x0
|
|
depends on IMXRT_SRAM_HEAP
|
|
---help---
|
|
Used to reserve memory at the beginning of SRAM for, as an example,
|
|
a framebuffer.
|
|
|
|
endmenu # i.MX RT Heap Configuration
|
|
endmenu # Memory Configuration
|
|
|
|
menu "USDHC Configuration"
|
|
depends on IMXRT_USDHC
|
|
|
|
config IMXRT_USDHC_DMA
|
|
bool "Support DMA data transfers"
|
|
default y
|
|
select SDIO_DMA
|
|
---help---
|
|
Support DMA data transfers.
|
|
Enable SD card DMA data transfers. This is marginally optional.
|
|
For most usages, SD accesses will cause data overruns if used without
|
|
DMA.
|
|
|
|
config IMXRT_USDHC_WIDTH_D1_ONLY
|
|
bool "Use D1 only"
|
|
default n
|
|
---help---
|
|
Select 1-bit transfer mode. Default: 4-bit transfer mode.
|
|
endmenu # USDHC Configuration
|
|
|
|
menu "eDMA Configuration"
|
|
depends on IMXRT_EDMA
|
|
|
|
config IMXRT_EDMA_NTCD
|
|
int "Number of transfer descriptors"
|
|
default 0
|
|
---help---
|
|
Number of pre-allocated transfer descriptors. Needed for scatter-
|
|
gather DMA. Make to be set to zero to disable in-memory TCDs in
|
|
which case only the TCD channel registers will be used and scatter-
|
|
will not be supported.
|
|
|
|
config IMXRT_EDMA_ELINK
|
|
bool "Channeling Linking"
|
|
default n
|
|
---help---
|
|
This option enables optional minor or major loop channel linking:
|
|
|
|
Minor loop channel linking: As the channel completes the minor
|
|
loop, this flag enables linking to another channel. The link target
|
|
channel initiates a channel service request via an internal
|
|
mechanism that sets the TCDn_CSR[START] bit of the specified
|
|
channel.
|
|
|
|
If minor loop channel linking is disabled, this link mechanism is
|
|
suppressed in favor of the major loop channel linking.
|
|
|
|
Major loop channel linking: As the channel completes the minor
|
|
loop, this option enables the linking to another channel. The link
|
|
target channel initiates a channel service request via an internal
|
|
mechanism that sets the TCDn_CSR[START] bit of the linked channel.
|
|
|
|
config IMXRT_EDMA_ERCA
|
|
bool "Round Robin Channel Arbitration"
|
|
default n
|
|
---help---
|
|
Normally, a fixed priority arbitration is used for channel
|
|
selection. If this option is selected, round robin arbitration is
|
|
used for channel selection.
|
|
|
|
config IMXRT_EDMA_HOE
|
|
bool "Halt On Error"
|
|
default y
|
|
---help---
|
|
Any error causes the HALT bit to set. Subsequently, all service
|
|
requests are ignored until the HALT bit is cleared.
|
|
|
|
config IMXRT_EDMA_CLM
|
|
bool "Continuous Link Mode"
|
|
default n
|
|
---help---
|
|
By default, A minor loop channel link made to itself goes through
|
|
channel arbitration before being activated again. If this option is
|
|
selected, a minor loop channel link made to itself does not go
|
|
through channel arbitration before being activated again. Upon minor
|
|
loop completion, the channel activates again if that channel has a
|
|
minor loop channel link enabled and the link channel is itself. This
|
|
effectively applies the minor loop offsets and restarts the next
|
|
minor loop.
|
|
|
|
config IMXRT_EDMA_EMLIM
|
|
bool "Minor Loop Mapping"
|
|
default n
|
|
---help---
|
|
Normally TCD word 2 is a 32-bit NBYTES field. When this option is
|
|
enabled, TCD word 2 is redefined to include individual enable fields,
|
|
an offset field, and the NBYTES field. The individual enable fields
|
|
allow the minor loop offset to be applied to the source address, the
|
|
destination address, or both. The NBYTES field is reduced when either
|
|
offset is enabled.
|
|
|
|
config IMXRT_EDMA_EDBG
|
|
bool "Enable Debug"
|
|
default n
|
|
---help---
|
|
When in debug mode, the DMA stalls the start of a new channel. Executing
|
|
channels are allowed to complete. Channel execution resumes when the
|
|
system exits debug mode or the EDBG bit is cleared
|
|
|
|
endmenu # eDMA Global Configuration
|
|
|
|
if PM
|
|
|
|
config IMXRT_PM_SERIAL_ACTIVITY
|
|
int "PM serial activity"
|
|
default 10
|
|
---help---
|
|
PM activity reported to power management logic on every serial
|
|
interrupt.
|
|
|
|
endif
|
|
|
|
menu "RTC Configuration"
|
|
depends on IMXRT_SNVS_HPRTC
|
|
|
|
config IMXRT_RTC_MAGIC_REG
|
|
int "RTC SNVS GPR"
|
|
default 0
|
|
range 0 3
|
|
---help---
|
|
The BKP register used to store/check the Magic value to determine if
|
|
RTC is already setup
|
|
|
|
config IMXRT_RTC_MAGIC
|
|
hex "RTC Magic 1"
|
|
default 0xfacefeed
|
|
---help---
|
|
Value used as Magic to determine if the RTC is already setup
|
|
|
|
endmenu
|
|
|
|
menu "LCD Configuration"
|
|
depends on IMXRT_LCD
|
|
|
|
config IMXRT_LCD_VIDEO_PLL_FREQ
|
|
int "Video PLL Frequency"
|
|
default 92000000
|
|
range 41500000 1300000000
|
|
---help---
|
|
Frequency of Video PLL.
|
|
|
|
config IMXRT_LCD_VRAMBASE
|
|
hex "Video RAM base address"
|
|
default 0x80000000
|
|
---help---
|
|
Base address of the video RAM frame buffer.
|
|
Default: SDRAM
|
|
|
|
config IMXRT_LCD_REFRESH_FREQ
|
|
int "LCD refesh rate (Hz)"
|
|
default 60
|
|
---help---
|
|
LCD refesh rate (Hz)
|
|
|
|
config IMXRT_LCD_BACKLIGHT
|
|
bool "Enable backlight"
|
|
default y
|
|
---help---
|
|
Enable backlight support. If IMXRT_LCD_BACKLIGHT is selected, then
|
|
the board-specific logic must provide this IMXRT_backlight()
|
|
interface so that the LCD driver can turn the backlight on and off
|
|
as necessary. You should select this option and implement
|
|
IMXRT_backlight() if your board provides GPIO control over the
|
|
backlight. This interface provides only ON/OFF control of the
|
|
backlight. If you want finer control over the backlight level (for
|
|
example, using PWM), then this interface would need to be extended.
|
|
|
|
choice
|
|
prompt "Input Bits per pixel"
|
|
default IMXRT_LCD_INPUT_BPP16
|
|
|
|
config IMXRT_LCD_INPUT_BPP8_LUT
|
|
bool "8 BPP Color Map"
|
|
select FB_CMAP
|
|
|
|
config IMXRT_LCD_INPUT_BPP8
|
|
bool "8 BPP RGB_332"
|
|
|
|
config IMXRT_LCD_INPUT_BPP15
|
|
bool "16 BPP RGB_555"
|
|
|
|
config IMXRT_LCD_INPUT_BPP16
|
|
bool "16 BPP RGB_565"
|
|
|
|
config IMXRT_LCD_INPUT_BPP24
|
|
bool "24 BPP RGB_888"
|
|
|
|
config IMXRT_LCD_INPUT_BPP32
|
|
bool "32 BPP RGB_0888"
|
|
|
|
endchoice
|
|
|
|
config IMXRT_LCD_BGR
|
|
bool "Blue-Green-Red color order"
|
|
default n
|
|
---help---
|
|
This option selects BGR color order vs. default RGB
|
|
|
|
choice
|
|
prompt "Output Bus width"
|
|
default IMXRT_LCD_OUTPUT_16
|
|
|
|
config IMXRT_LCD_OUTPUT_8
|
|
bool "8 Bit LCD Bus"
|
|
|
|
config IMXRT_LCD_OUTPUT_16
|
|
bool "16 Bit LCD Bus"
|
|
|
|
config IMXRT_LCD_OUTPUT_18
|
|
bool "18 Bit LCD Bus"
|
|
|
|
config IMXRT_LCD_OUTPUT_24
|
|
bool "24 Bit LCD Bus"
|
|
|
|
endchoice
|
|
|
|
config IMXRT_LCD_BACKCOLOR
|
|
hex "Initial background color"
|
|
default 0x0
|
|
---help---
|
|
Initial background color
|
|
|
|
config IMXRT_LCD_HWIDTH
|
|
int "Display width (pixels)"
|
|
default 480
|
|
---help---
|
|
Horizontal width the display in pixels
|
|
|
|
config IMXRT_LCD_HPULSE
|
|
int "Horizontal pulse"
|
|
default 41
|
|
|
|
config IMXRT_LCD_HFRONTPORCH
|
|
int "Horizontal front porch"
|
|
default 4
|
|
|
|
config IMXRT_LCD_HBACKPORCH
|
|
int "Horizontal back porch"
|
|
default 8
|
|
|
|
config IMXRT_LCD_VHEIGHT
|
|
int "Display height (rows)"
|
|
default 272
|
|
---help---
|
|
Vertical height of the display in rows
|
|
|
|
config IMXRT_LCD_VPULSE
|
|
int "Vertical pulse"
|
|
default 10
|
|
|
|
config IMXRT_LCD_VFRONTPORCH
|
|
int "Vertical front porch"
|
|
default 4
|
|
|
|
config IMXRT_LCD_VBACKPORCH
|
|
int "Vertical back porch"
|
|
default 2
|
|
|
|
config IMXRT_VSYNC_ACTIVE_HIGH
|
|
bool "V-sync active high"
|
|
default n
|
|
|
|
config IMXRT_HSYNC_ACTIVE_HIGH
|
|
bool "H-sync active high"
|
|
default n
|
|
|
|
config IMXRT_DATAEN_ACTIVE_HIGH
|
|
bool "Data enable active high"
|
|
default y
|
|
|
|
config IMXRT_DATA_RISING_EDGE
|
|
bool "Data clock rising edge"
|
|
default y
|
|
|
|
endmenu # LCD Configuration
|
|
|
|
if IMXRT_USBOTG && USBHOST
|
|
|
|
menu "USB host controller driver (HCD) options"
|
|
|
|
config IMXRT_EHCI_NQHS
|
|
int "Number of Queue Head (QH) structures"
|
|
default 4
|
|
---help---
|
|
Configurable number of Queue Head (QH) structures. The default is
|
|
one per Root hub port plus one for EP0 (4).
|
|
|
|
config IMXRT_EHCI_NQTDS
|
|
int "Number of Queue Element Transfer Descriptor (qTDs)"
|
|
default 6
|
|
---help---
|
|
Configurable number of Queue Element Transfer Descriptor (qTDs).
|
|
The default is one per root hub plus three from EP0 (6).
|
|
|
|
config IMXRT_EHCI_BUFSIZE
|
|
int "Size of one request/descriptor buffer"
|
|
default 128
|
|
---help---
|
|
The size of one request/descriptor buffer in bytes. The TD buffe
|
|
size must be an even number of 32-bit words and must be large enough
|
|
to hangle the largest transfer via a SETUP request.
|
|
|
|
config IMXRT_EHCI_PREALLOCATE
|
|
bool "Preallocate descriptor pool"
|
|
default y
|
|
---help---
|
|
Select this option to pre-allocate EHCI queue and descriptor
|
|
structure pools in .bss. Otherwise, these pools will be
|
|
dynamically allocated using kmm_memalign().
|
|
|
|
endmenu # USB host controller driver (HCD) options
|
|
endif # IMXRT_USBOTG && USBHOST
|
|
|
|
endif # ARCH_CHIP_IMXRT
|
|
|