4c601faf6f
Squashed commit of the following:
arch/arm/src/stm32f0l0: Various changes for a clean compilation. Still does not compile correctly due to missing FLASH latency definitions.
arch/arm/src/stm32f0l0/hardware: Add framework for the STM32 L0. Currently set to same as the STM32F0.
arch/arm/src/stm32f0l0/hardware: Very fragmentary FLASH header register definitions for the STM32 L0.
arch/arm/src/stm32f0l0: Bring in DMA v1. Cannot possibly be functionaly yet due to the limited number for M0 interrupts.
arch/arm/src/stm32f0l0: Add STM32 F0/L0 LSE and backup power domain controls.
arch/arm/src/stm32f0l0/hardware/stm32l0_pwr.h: Add STM32L0 PWR header file.
arch/arm/include/stm32f0l0/chip.h: Clean up WIP chip header file.
arch/arm/include/stm32f0l0/chip.h: WIP.
arm/src/stm32f0l0: Resolve some small differences between F0 and L0 GPIO pin options.
arch/arm/src/stm32f0l0: Better integrate STM32L0 header files.
nuttx/arch/arm/include/stm32f0l0: Add STM32L0 IRQ number definition file.
arch/arm/src/stm32f0l0: Add STM32L0 RCC driver.
arch/arm/src/stm32f0l0/hardware: Adds basic STM32L0 header files.
arch/arm/src/stm32f0l0: Add STM32L0 chip selections.
configs/: Hook new STM32L0 boards into the configuration system.
configs: nucleo boards use as default ST LINK MCO as clock input from MCU and for this HSEBYP must be enabled
configs: add basic support for nucleo-l073rz
configs: add basic support for b-l072z-lrwan1
229 lines
8.8 KiB
C
229 lines
8.8 KiB
C
/****************************************************************************
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* configs/nucleo-l152re/include/board.h
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* include/arch/board/board.h
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Author: Mateusz Szafoni <raiden00@railab.me>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#ifndef __CONFIG_NUCLEOL152RE_INCLUDE_BOARD_H
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#define __CONFIG_NUCLEOL152RE_INCLUDE_BOARD_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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# include <stdbool.h>
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#endif
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#ifdef __KERNEL__
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# include "stm32.h"
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Clocking *****************************************************************/
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/* Four different clock sources can be used to drive the system clock (SYSCLK):
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*
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* - HSI high-speed internal oscillator clock
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* Generated from an internal 16 MHz RC oscillator
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* - HSE high-speed external oscillator clock. 8 MHz from MCO output of ST-LINK.
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* - PLL clock
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* - MSI multispeed internal oscillator clock
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* The MSI clock signal is generated from an internal RC oscillator. Seven frequency
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* ranges are available: 65.536 kHz, 131.072 kHz, 262.144 kHz, 524.288 kHz, 1.048 MHz,
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* 2.097 MHz (default value) and 4.194 MHz.
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*
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* The devices have the following two secondary clock sources
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* - LSI low-speed internal RC clock
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* Drives the watchdog and RTC. Approximately 37KHz
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* - LSE low-speed external oscillator clock
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* Driven by 32.768KHz crystal (X2) on the OSC32_IN and OSC32_OUT pins.
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*/
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#define STM32_BOARD_XTAL 8000000ul
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#define STM32_HSI_FREQUENCY 16000000ul
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#define STM32_LSI_FREQUENCY 37000 /* Approximately 37KHz */
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#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
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#define STM32_LSE_FREQUENCY 32768 /* X2 on board */
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/* PLL Configuration
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*
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* - PLL source is HSE -> 8MHz
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* - PLL multipler is 12 -> 96MHz PLL VCO clock output
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* - PLL output divider 3 -> 32MHz divided down PLL VCO clock output
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*
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* Resulting SYSCLK frequency is 8MHz x 12 / 3 = 32MHz
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*
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* USB/SDIO:
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* If the USB or SDIO interface is used in the application, the PLL VCO
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* clock (defined by STM32_CFGR_PLLMUL) must be programmed to output a 96
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* MHz frequency. This is required to provide a 48 MHz clock to the USB or
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* SDIO (SDIOCLK or USBCLK = PLLVCO/2).
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* SYSCLK
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* The system clock is derived from the PLL VCO divided by the output division factor.
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* Limitations:
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* 96 MHz as PLLVCO when the product is in range 1 (1.8V),
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* 48 MHz as PLLVCO when the product is in range 2 (1.5V),
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* 24 MHz when the product is in range 3 (1.2V).
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* Output division to avoid exceeding 32 MHz as SYSCLK.
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* The minimum input clock frequency for PLL is 2 MHz (when using HSE as PLL source).
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*/
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#if 1
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#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC /* PLL clocked by the HSE */
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#define STM32_HSEBYP_ENABLE 1
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#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */
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#define STM32_CFGR_PLLDIV RCC_CFGR_PLLDIV_3 /* PLLDIV = 3 */
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#define STM32_PLL_FREQUENCY (12*STM32_BOARD_XTAL) /* PLL VCO Frequency is 96MHz */
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#else
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#define STM32_CFGR_PLLSRC 0 /* PLL clocked by the HSI RC */
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#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx6 /* PLLMUL = 6 */
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#define STM32_CFGR_PLLDIV RCC_CFGR_PLLDIV_3 /* PLLDIV = 3 */
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#define STM32_PLL_FREQUENCY (6*STM32_HSI_FREQUENCY) /* PLL VCO Frequency is 96MHz */
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#endif
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/* Use the PLL and set the SYSCLK source to be the divided down PLL VCO output
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* frequency (STM32_PLL_FREQUENCY divided by the PLLDIV value).
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*/
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#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL
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#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL
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#define STM32_SYSCLK_FREQUENCY (STM32_PLL_FREQUENCY/3)
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/* AHB clock (HCLK) is SYSCLK (32MHz) */
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#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
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#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
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#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
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/* APB2 clock (PCLK2) is HCLK (32MHz) */
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#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK
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#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY
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#define STM32_APB2_CLKIN STM32_PCLK2_FREQUENCY
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/* APB1 clock (PCLK1) is HCLK (32MHz) */
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#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK
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#define STM32_PCLK1_FREQUENCY STM32_HCLK_FREQUENCY
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/* TODO: Timers */
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/* LED definitions **********************************************************/
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/* The Nucleo L152RE board has three LEDs. Two of these are controlled by
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* logic on the board and are not available for software control:
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*
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* LD1 COM: LD1 default status is red. LD1 turns to green to indicate that
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* communications are in progress between the PC and the
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* ST-LINK/V2-1.
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* LD3 PWR: red LED indicates that the board is powered.
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*
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* And one can be controlled by software:
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*
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* User LD2: green LED is a user LED connected to the I/O PA5 of the
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* STM32L152RET6.
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*
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* If CONFIG_ARCH_LEDS is not defined, then the user can control the LED in
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* any way. The following definition is used to access the LED.
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*/
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/* LED index values for use with board_userled() */
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#define BOARD_LED1 0 /* User LD2 */
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#define BOARD_NLEDS 1
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/* LED bits for use with board_userled_all() */
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#define BOARD_LED1_BIT (1 << BOARD_LED1)
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/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board
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* the Nucleo L152RE. The following definitions describe how NuttX controls
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* the LED:
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*
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* SYMBOL Meaning LED1 state
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* ------------------ ----------------------- ----------
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* LED_STARTED NuttX has been started OFF
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* LED_HEAPALLOCATE Heap has been allocated OFF
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* LED_IRQSENABLED Interrupts enabled OFF
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* LED_STACKCREATED Idle stack created ON
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* LED_INIRQ In an interrupt No change
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* LED_SIGNAL In a signal handler No change
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* LED_ASSERTION An assertion failed No change
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* LED_PANIC The system has crashed Blinking
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* LED_IDLE STM32 is is sleep mode Not used
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*/
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#define LED_STARTED 0
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#define LED_HEAPALLOCATE 0
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#define LED_IRQSENABLED 0
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#define LED_STACKCREATED 1
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#define LED_INIRQ 2
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#define LED_SIGNAL 2
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#define LED_ASSERTION 2
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#define LED_PANIC 1
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/* Button definitions *******************************************************/
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/* The Nucleo L152RE supports two buttons; only one button is controllable
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* by software:
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*
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* B1 USER: user button connected to the I/O PC13 of the STM32L152RET6.
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* B2 RESET: push button connected to NRST is used to RESET the
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* STM32L152RET6.
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*/
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#define BUTTON_USER 0
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#define NUM_BUTTONS 1
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#define BUTTON_USER_BIT (1 << BUTTON_USER)
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/* Alternate function pin selections ****************************************/
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/* USART */
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/* By default the USART2 is connected to STLINK Virtual COM Port:
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* USART2_RX - PA3
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* USART2_TX - PA2
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*/
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#define GPIO_USART2_RX GPIO_USART2_RX_1 /* PA3 */
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#define GPIO_USART2_TX GPIO_USART2_TX_1 /* PA2 */
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#endif /* __CONFIG_NUCLEO_L152RE_INCLUDE_BOARD_H */
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