191 lines
6.9 KiB
C
191 lines
6.9 KiB
C
/************************************************************************************
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* configs/fire-stm32v2/src/stm32_selectlcd.c
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*
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* Copyright (C) 2012, 2016 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <assert.h>
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#include <debug.h>
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#include <nuttx/irq.h>
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#include <arch/board/board.h>
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#include "chip.h"
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#include "up_arch.h"
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#include "stm32_gpio.h"
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#include "stm32.h"
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#include "fire-stm32v2.h"
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#ifdef CONFIG_STM32_FSMC
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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#ifndef CONFIG_STM32_FSMC
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# warning "FSMC is not enabled"
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#endif
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#if STM32_NGPIO_PORTS < 6
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# error "Required GPIO ports not enabled"
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#endif
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/* 2.4" TFT + Touchscreen. FSMC Bank1
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*
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* --- ------ -------------- -------------------------------------------------------------------
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* PIN NAME SIGNAL NOTES
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* --- ------ -------------- -------------------------------------------------------------------
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*
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* 30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH
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* 31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH
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* 32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH
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* 92 PB6 PB6-I2C1-SCL 2.4" TFT + Touchscreen, AT24C02
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* 93 PB7 PB7-I2C1-SDA 2.4" TFT + Touchscreen, AT24C02
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* 81 PD0 PD0-FSMC_D2 2.4" TFT + Touchscreen
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* 82 PD1 PD1-FSMC_D3 2.4" TFT + Touchscreen
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* 85 PD4 PD4-FSMC_NOE 2.4" TFT + Touchscreen
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* 86 PD5 PD5-FSMC_NWE 2.4" TFT + Touchscreen
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* 88 PD7 PD7-FSMC_NE1 2.4" TFT + Touchscreen
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* 55 PD8 PD8-FSMC_D13 2.4" TFT + Touchscreen
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* 56 PD9 PD9-FSMC_D14 2.4" TFT + Touchscreen
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* 57 PD10 PD10-FSMC_D15 2.4" TFT + Touchscreen
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* 58 PD11 PD11-FSMC_A16 2.4" TFT + Touchscreen
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* 60 PD13 PD13-LCD/LIGHT 2.4" TFT + Touchscreen
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* 61 PD14 PD14-FSMC_D0 2.4" TFT + Touchscreen
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* 62 PD15 PD15-FSMC_D1 2.4" TFT + Touchscreen
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* 98 PE1 PE1-FSMC_NBL1 2.4" TFT + Touchscreen
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* 38 PE7 PE7-FSMC_D4 2.4" TFT + Touchscreen
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* 39 PE8 PE8-FSMC_D5 2.4" TFT + Touchscreen
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* 40 PE9 PE9-FSMC_D6 2.4" TFT + Touchscreen
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* 41 PE10 PE10-FSMC_D7 2.4" TFT + Touchscreen
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* 42 PE11 PE11-FSMC_D8 2.4" TFT + Touchscreen
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* 43 PE12 PE12-FSMC_D9 2.4" TFT + Touchscreen
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* 44 PE13 PE13-FSMC_D10 2.4" TFT + Touchscreen
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* 45 PE14 PE14-FSMC_D11 2.4" TFT + Touchscreen
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* 46 PE15 PE15-FSMC_D12 2.4" TFT + Touchscreen
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*
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* NOTE: SPI and I2C pin configuration is controlled in the SPI and I2C drivers, respectively.
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*/
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static const uint16_t g_lcdconfig[NCOMMON_CONFIG] =
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{
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/* Address Lines: A16 only */
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GPIO_NPS_A16,
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/* Data Lines: D0... D15 */
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GPIO_NPS_D0, GPIO_NPS_D1, GPIO_NPS_D2, GPIO_NPS_D3,
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GPIO_NPS_D4, GPIO_NPS_D5, GPIO_NPS_D6, GPIO_NPS_D7,
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GPIO_NPS_D8, GPIO_NPS_D9, GPIO_NPS_D10, GPIO_NPS_D11,
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GPIO_NPS_D12, GPIO_NPS_D13, GPIO_NPS_D14, GPIO_NPS_D15,
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/* NOE, NWE, NE1, NBL1 */
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GPIO_NPS_NOE, GPIO_NPS_NWE, GPIO_NPS_NE1, GPIO_NPS_NBL1,
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/* Backlight GPIO */
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GPIO_LCD_BACKLIGHT
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};
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#define NLCD_CONFIG (sizeof(g_lcdconfig) / sizeof(uint16_t))
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/************************************************************************************
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* Private Data
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************************************************************************************/
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/************************************************************************************
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* Private Functions
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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/************************************************************************************
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* Name: stm32_selectlcd
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*
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* Description:
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* Initialize to the LCD pin configuration.
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*
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************************************************************************************/
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void stm32_selectlcd(void)
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{
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irqstate_t flags;
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int i;
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/* Configure LCD GPIO pis */
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flags = enter_critical_section();
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for (i = 0; i < NLCD_GPIOS; i++)
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{
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stm32_configgpio(g_lcdconfig[i]);
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}
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/* Enable AHB clocking to the FSMC */
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stm32_fsmc_enable();
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/* Bank1 NOR/SRAM control register configuration */
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putreg32(FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR1);
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/* Bank1 NOR/SRAM timing register configuration */
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putreg32(FSMC_BTR_ADDSET(1)|FSMC_BTR_ADDHLD(0)|FSMC_BTR_DATAST(2)|FSMC_BTR_BUSTURN(0)|
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FSMC_BTR_CLKDIV(0)|FSMC_BTR_DATLAT(0)|FSMC_BTR_ACCMODA, STM32_FSMC_BTR1);
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putreg32(0xffffffff, STM32_FSMC_BWTR4);
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/* Enable the bank by setting the MBKEN bit */
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putreg32(FSMC_BCR_MBKEN | FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR1);
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leave_critical_section(flags);
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}
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#endif /* CONFIG_STM32_FSMC */
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