141 lines
5.3 KiB
Plaintext
141 lines
5.3 KiB
Plaintext
/****************************************************************************
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* boards/xtensa/esp32s2/common/scripts/esp32s2_memory.ld
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* ESP32-S2 Linker Script Memory Layout
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*
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* This file describes the memory layout (memory blocks) as virtual
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* memory addresses.
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*
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* esp32s2_sections.ld contains output sections to link compiler output
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* into these memory blocks.
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*
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****************************************************************************/
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#include <nuttx/config.h>
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#define RAM_IRAM_START 0x40020000
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#define RAM_DRAM_START 0x3ffb0000
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#define DATA_RAM_END 0x3ffe0000 /* 2nd stage bootloader iram_loader_seg
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* starts at SRAM block 14 (reclaimed
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* after app boots)
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*/
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#define IRAM_ORG (RAM_IRAM_START + CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE \
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+ CONFIG_ESP32S2_DATA_CACHE_SIZE)
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#define DRAM_ORG (RAM_DRAM_START + CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE \
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+ CONFIG_ESP32S2_DATA_CACHE_SIZE)
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#define I_D_RAM_SIZE DATA_RAM_END - DRAM_ORG
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#ifdef CONFIG_ESP32S2_FLASH_2M
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# define FLASH_SIZE 0x200000
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#elif defined (CONFIG_ESP32S2_FLASH_4M)
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# define FLASH_SIZE 0x400000
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#elif defined (CONFIG_ESP32S2_FLASH_8M)
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# define FLASH_SIZE 0x800000
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#elif defined (CONFIG_ESP32S2_FLASH_16M)
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# define FLASH_SIZE 0x1000000
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#endif
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MEMORY
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{
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#ifdef CONFIG_ESP32S2_APP_FORMAT_MCUBOOT
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/* The origin values for "metadata" and "ROM" memory regions are the actual
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* load addresses.
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*
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* NOTE: The memory region starting from 0x0 with length represented by
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* CONFIG_ESP32S2_APP_MCUBOOT_HEADER_SIZE is reserved for the MCUboot header,
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* which will be prepended to the binary file by the "imgtool" during the
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* signing of firmware image.
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*/
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metadata (RX) : org = CONFIG_ESP32S2_APP_MCUBOOT_HEADER_SIZE, len = 0x20
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ROM (RX) : org = CONFIG_ESP32S2_APP_MCUBOOT_HEADER_SIZE + 0x20,
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len = FLASH_SIZE - (CONFIG_ESP32S2_APP_MCUBOOT_HEADER_SIZE + 0x20)
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#endif
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/* Below values assume the flash cache is on, and have the blocks this
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* uses subtracted from the length of the various regions. The 'data access
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* port' dram/drom regions map to the same iram/irom regions but are
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* connected to the data port of the CPU and eg allow bytewise access.
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*/
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/* IRAM for CPU */
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iram0_0_seg (RX) : org = IRAM_ORG, len = I_D_RAM_SIZE
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/* Flash mapped instruction data. */
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#ifdef CONFIG_ESP32S2_APP_FORMAT_MCUBOOT
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irom0_0_seg (RX) : org = 0x40080020, len = FLASH_SIZE
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#else
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/* The 0x20 offset is a convenience for the app binary image generation.
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* Flash cache has 64KB pages. The .bin file which is flashed to the chip
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* has a 0x18 byte file header, and each segment has a 0x08 byte segment
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* header. Setting this offset makes it simple to meet the flash cache MMU's
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* constraint that (paddr % 64KB == vaddr % 64KB).
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*/
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irom0_0_seg (RX) : org = 0x40080020, len = FLASH_SIZE - 0x20
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#endif
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/* Shared data RAM, excluding memory reserved for bootloader and ROM
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* bss/data/stack.
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*/
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dram0_0_seg (RW) : org = DRAM_ORG, len = I_D_RAM_SIZE
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/* Flash mapped constant data */
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#ifdef CONFIG_ESP32S2_APP_FORMAT_MCUBOOT
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/* The DROM segment origin is offset by 0x40 for mirroring the actual ROM
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* image layout:
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* 0x0 - 0x1F : MCUboot header
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* 0x20 - 0x3F : Application image metadata section
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* 0x40 onwards: ROM code and data
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* This is required to meet the following constraint from the external
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* flash MMU:
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* VMA % 64KB == LMA % 64KB
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* i.e. the lower 16 bits of both the virtual address (address seen by the
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* CPU) and the load address (physical address of the external flash) must
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* be equal.
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*/
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drom0_0_seg (R) : org = 0x3f000000 + (CONFIG_ESP32S2_APP_MCUBOOT_HEADER_SIZE + 0x20),
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len = FLASH_SIZE - (CONFIG_ESP32S2_APP_MCUBOOT_HEADER_SIZE + 0x20)
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#else
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/* The 0x20 offset is a convenience for the app binary image generation.
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* Flash cache has 64KB pages. The .bin file which is flashed to the chip
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* has a 0x18 byte file header, and each segment has a 0x08 byte segment
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* header. Setting this offset makes it simple to meet the flash cache MMU's
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* constraint that (paddr % 64KB == vaddr % 64KB).
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*/
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drom0_0_seg (R) : org = 0x3f000020, len = FLASH_SIZE - 0x20
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#endif
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/* RTC fast memory (executable). Persists over deep sleep. */
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rtc_iram_seg(RWX) : org = 0x40070000, len = 0x2000
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/* RTC slow memory (data accessible). Persists over deep sleep.
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* Start of RTC slow memory is reserved for ULP co-processor code + data,
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* if enabled.
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*/
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rtc_slow_seg(RW) : org = 0x50000000 + CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM,
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len = 0x2000 - CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM
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/* RTC fast memory (same block as above), viewed from data bus */
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rtc_data_seg(RW) : org = 0x3ff9e000, len = 0x2000
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}
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#if CONFIG_ESP32S2_RUN_IRAM
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REGION_ALIAS("default_rodata_seg", dram0_0_seg);
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REGION_ALIAS("default_code_seg", iram0_0_seg);
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#else
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REGION_ALIAS("default_rodata_seg", drom0_0_seg);
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REGION_ALIAS("default_code_seg", irom0_0_seg);
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#endif /* CONFIG_ESP32S2_RUN_IRAM */
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