5c1c939cdc
Architecture support for STMicroelectronics STMU585xx MCUs. This is based on corresponding code for STM32L5, but has been considerably adjusted. Tested with a B-U585I-IOT02A board and a simple NSH configuration, but only running NuttX in the non-secure world with TrustedFirmware-M. Signed-off-by: Michael Jung <mijung@gmx.net>
83 lines
4.2 KiB
C
83 lines
4.2 KiB
C
/****************************************************************************
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* arch/arm/include/stm32u5/chip.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_STM32U5_CHIP_H
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#define __ARCH_ARM_INCLUDE_STM32U5_CHIP_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************
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* Pre-processor Prototypes
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****************************************************************************/
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#if defined(CONFIG_STM32U5_STM32U585XX)
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# define STM32_SRAM1_SIZE (192*1024) /* 192Kb SRAM1 on AHB bus Matrix */
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# define STM32_SRAM2_SIZE (64*1024) /* 64kB SRAM2 on AHB bus Matrix */
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# define STM32_SRAM3_SIZE (512*1024) /* 512kB SRAM3 on AHB bus Matrix */
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#else
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# error "Unsupported STM32U5 chip"
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#endif
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#if defined(CONFIG_STM32U5_STM32U585XX)
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# define STM32_NFSMC 1 /* Have FSMC memory controller */
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# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
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# define STM32_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */
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# define STM32_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */
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# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM15-17 without DMA */
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# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
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# define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */
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# define STM32_NRNG 1 /* Random number generator (RNG) */
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# define STM32_NUART 2 /* UART 4-5 */
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# define STM32_NUSART 3 /* USART 1-3 */
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# define STM32_NLPUART 1 /* LPUART 1 */
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# define STM32_QSPI 0 /* No QuadSPI1 */
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# define STM32_OCTOSPI 2 /* OCTOSPI1-2 */
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# define STM32_NSPI 3 /* SPI1-3 */
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# define STM32_NI2C 4 /* I2C1-4 */
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# define STM32_NSWPMI 0 /* No SWPMI1 */
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# define STM32_NUSBOTGFS 1 /* USB OTG FS */
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# define STM32_NUSBFS 0 /* No USB FS */
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# define STM32_NCAN 1 /* CAN1 */
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# define STM32_NSAI 2 /* SAI1-2 */
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# define STM32_NSDMMC 1 /* SDMMC interface */
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# define STM32_NDMA 2 /* DMA1-2 */
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# define STM32_NPORTS 9 /* 9 GPIO ports, GPIOA-I */
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# define STM32_NADC 1 /* 12-bit ADC1, up to 20 channels */
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# define STM32_NDAC 2 /* 12-bit DAC1-2 */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NCOMP 2 /* Comparators */
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# define STM32_NOPAMP 2 /* Operational Amplifiers */
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#endif /* CONFIG_STM32U5_STM32U585XX */
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/* NVIC priority levels *****************************************************/
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/* 16 Programmable interrupt levels */
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#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */
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#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
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#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
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#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */
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#endif /* __ARCH_ARM_INCLUDE_STM32U5_CHIP_H */
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