560 lines
22 KiB
ReStructuredText
560 lines
22 KiB
ReStructuredText
===============
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CloudController
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===============
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This README discusses issues unique to NuttX configurations for the CloudController
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development board featuring the STMicro STM32F107VCT MCU.
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Features of the CloudController board include:
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- STM32F107VCT
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- 10/100M PHY (DM9161AEP)
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- USB OTG
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- USART connectos (USART1-2)
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- SPI Flash (W25X16)
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- (3) LEDs (LED1-3)
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- (3) Buttons (KEY1-3, USERKEY2, USERKEY, TEMPER, WAKEUP)
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- 5V/3.3V power conversion
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- SWD
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STM32F107VCT Pin Usage
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======================
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::
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== ==== ============== ===================================================================
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PN NAME SIGNAL NOTES
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== ==== ============== ===================================================================
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**23 PA0 WAKEUP Connected to KEY4. Active low: Closing KEY4 pulls WAKEUP to ground.
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24 PA1 MII_RX_CLK
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RMII_REF_CLK
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25 PA2 MII_MDIO
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26 PA3 315M_VT
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29 PA4 DAC_OUT1 To CON5(CN14)
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30 PA5 DAC_OUT2 To CON5(CN14). JP10
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SPI1_SCK To the SD card, SPI FLASH
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31 PA6 SPI1_MISO To the SD card, SPI FLASH
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32 PA7 SPI1_MOSI To the SD card, SPI FLASH
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67 PA8 MCO To DM9161AEP PHY
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68 PA9 USB_VBUS MINI-USB-AB. JP3
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USART1_TX MAX3232 to CN5
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69 PA10 USB_ID MINI-USB-AB. JP5
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USART1_RX MAX3232 to CN5
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70 PA11 USB_DM MINI-USB-AB
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71 PA12 USB_DP MINI-USB-AB
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72 PA13 TMS/SWDIO
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76 PA14 TCK/SWCLK
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77 PA15 TDI
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== ==== ============== ===================================================================
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== ==== ============== ===================================================================
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PN NAME SIGNAL NOTES
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== ==== ============== ===================================================================
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35 PB0 ADC_IN1 To CON5(CN14)
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36 PB1 ADC_IN2 To CON5(CN14)
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37 PB2 DATA_LE To TFT LCD (CN13)
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BOOT1 JP13
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89 PB3 TDO/SWO
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90 PB4 TRST
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91 PB5 CAN2_RX
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92 PB6 CAN2_TX JP11
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I2C1_SCL
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93 PB7 I2C1_SDA
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95 PB8 USB_PWR Drives USB VBUS
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96 PB9 F_CS To both the TFT LCD (CN13) and to the W25X16 SPI FLASH
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47 PB10 USERKEY Connected to KEY2
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48 PB11 MII_TX_EN Ethernet PHY
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51 PB12 I2S_WS Audio DAC
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MII_TXD0 Ethernet PHY
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52 PB13 I2S_CK Audio DAC
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MII_TXD1 Ethernet PHY
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53 PB14 SD_CD There is confusion here. Schematic is wrong LCD_WR is PB14.
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54 PB15 I2S_DIN Audio DAC
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== ==== ============== ===================================================================
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== ==== ============== ===================================================================
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PN NAME SIGNAL NOTES
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== ==== ============== ===================================================================
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15 PC0 POTENTIO_METER
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16 PC1 MII_MDC Ethernet PHY
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17 PC2 WIRELESS_INT
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18 PC3 WIRELESS_CE To the NRF24L01 2.4G wireless module
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33 PC4 USERKEY2 Connected to KEY1
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34 PC5 TP_INT JP6. To TFT LCD (CN13) module
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MII_INT Ethernet PHY
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63 PC6 I2S_MCK Audio DAC. Active low: Pulled high
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64 PC7 PCM1770_CS Audio DAC. Active low: Pulled high
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65 PC8 LCD_CS TFT LCD (CN13). Active low: Pulled high
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66 PC9 TP_CS TFT LCD (CN13). Active low: Pulled high
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78 PC10 SPI3_SCK To TFT LCD (CN13), the NRF24L01 2.4G wireless module
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79 PC11 SPI3_MISO To TFT LCD (CN13), the NRF24L01 2.4G wireless module
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80 PC12 SPI3_MOSI To TFT LCD (CN13), the NRF24L01 2.4G wireless module
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7 PC13 TAMPER Connected to KEY3
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8 PC14 OSC32_IN Y1 32.768Khz XTAL
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9 PC15 OSC32_OUT Y1 32.768Khz XTAL
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== ==== ============== ===================================================================
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== ==== ============== ===================================================================
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PN NAME SIGNAL NOTES
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== ==== ============== ===================================================================
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81 PD0 CAN1_RX
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82 PD1 CAN1_TX
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83 PD2 LED1 Active low: Pulled high
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84 PD3 LED2 Active low: Pulled high
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85 PD4 LED3 Active low: Pulled high
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86 PD5 485_TX Same as USART2_TX but goes to SP3485
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USART2_TX MAX3232 to CN6
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87 PD6 485_RX Save as USART2_RX but goes to SP3485 (see JP4)
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USART2_RX MAX3232 to CN6
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88 PD7 LED4 Active low: Pulled high
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485_DIR SP3485 read enable (not)
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55 PD8 MII_RX_DV Ethernet PHY
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RMII_CRSDV Ethernet PHY
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56 PD9 MII_RXD0 Ethernet PHY
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57 PD10 MII_RXD1 Ethernet PHY
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58 PD11 SD_CS Active low: Pulled high (See also TFT LCD CN13, pin 32)
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59 PD12 WIRELESS_CS To the NRF24L01 2.4G wireless module
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60 PD13 LCD_RS To TFT LCD (CN13)
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61 PD14 LCD_WR To TFT LCD (CN13). Schematic is wrong LCD_WR is PB14.
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62 PD15 LCD_RD To TFT LCD (CN13)
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== ==== ============== ===================================================================
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== ==== ============== ===================================================================
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PN NAME SIGNAL NOTES
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== ==== ============== ===================================================================
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97 PE0 DB00 To TFT LCD (CN13)
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98 PE1 DB01 To TFT LCD (CN13)
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1 PE2 DB02 To TFT LCD (CN13)
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2 PE3 DB03 To TFT LCD (CN13)
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3 PE4 DB04 To TFT LCD (CN13)
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4 PE5 DB05 To TFT LCD (CN13)
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5 PE6 DB06 To TFT LCD (CN13)
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38 PE7 DB07 To TFT LCD (CN13)
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39 PE8 DB08 To TFT LCD (CN13)
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40 PE9 DB09 To TFT LCD (CN13)
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41 PE10 DB10 To TFT LCD (CN13)
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42 PE11 DB11 To TFT LCD (CN13)
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43 PE12 DB12 To TFT LCD (CN13)
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44 PE13 DB13 To TFT LCD (CN13)
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45 PE14 DB14 To TFT LCD (CN13)
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46 PE15 DB15 To TFT LCD (CN13)
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== ==== ============== ===================================================================
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== ==== ============== ===================================================================
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PN NAME SIGNAL NOTES
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== ==== ============== ===================================================================
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73 N/C
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12 OSC_IN Y2 25Mhz XTAL
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13 OSC_OUT Y2 25Mhz XTAL
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94 BOOT0 JP15 (3.3V or GND)
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14 RESET S5
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6 VBAT JP14 (3.3V or battery)
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49 VSS_1 GND
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74 VSS_2 GND
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99 VSS_3 GND
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27 VSS_4 GND
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10 VSS_5 GND
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19 VSSA VSSA
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20 VREF- VREF-
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== ==== ============== ===================================================================
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LEDs
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====
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The Cloudctrl board has four LEDs labeled LED1, LED2, LED3 and LED4 on the
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board. These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is
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defined. In that case, the usage by the board port is defined in
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include/board.h and src/up_leds.c. The LEDs are used to encode OS-related
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events as follows:
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=================== ======================= ======= ======= ======= ======
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SYMBOL Meaning LED1[1] LED2 LED3 LED4[4]
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=================== ======================= ======= ======= ======= ======
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LED_STARTED NuttX has been started ON OFF OFF OFF
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LED_HEAPALLOCATE Heap has been allocated OFF ON OFF OFF
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LED_IRQSENABLED Interrupts enabled ON ON OFF OFF
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LED_STACKCREATED Idle stack created OFF OFF ON OFF
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LED_INIRQ In an interrupt[2] ON N/C N/C OFF
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LED_SIGNAL In a signal handler[3] N/C ON N/C OFF
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LED_ASSERTION An assertion failed ON ON N/C OFF
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LED_PANIC The system has crashed N/C N/C N/C ON
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LED_IDLE STM32 is is sleep mode
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=================== ======================= ======= ======= ======= ======
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[1] If LED1, LED2, LED3 are statically on, then NuttX probably failed to boot
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and these LEDs will give you some indication of where the failure was
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[2] The normal state is LED1 ON and LED1 faintly glowing. This faint glow
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is because of timer interrupts that result in the LED being illuminated
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on a small proportion of the time.
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[3] LED2 may also flicker normally if signals are processed.
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[4] LED4 may not be available if RS-485 is also used. For RS-485, it will
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then indicate the RS-485 direction.
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Cloudctrl-specific Configuration Options
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============================================
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..
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CONFIG_ARCH - Identifies the arch/ subdirectory. This should be set to:
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CONFIG_ARCH=arm
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CONFIG_ARCH_family - For use in C code:
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CONFIG_ARCH_ARM=y
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CONFIG_ARCH_architecture - For use in C code:
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CONFIG_ARCH_CORTEXM3=y
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CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory
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CONFIG_ARCH_CHIP=stm32
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CONFIG_ARCH_CHIP_name - For use in C code to identify the exact chip:
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CONFIG_ARCH_CHIP_STM32F107VC=y
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CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG - Enables special STM32 clock
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configuration features.
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CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=n
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CONFIG_ARCH_BOARD - Identifies the boards/ subdirectory and
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hence, the board that supports the particular chip or SoC.
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CONFIG_ARCH_BOARD=shenzhou (for the Cloudctrl development board)
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CONFIG_ARCH_BOARD_name - For use in C code
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CONFIG_ARCH_BOARD_SHENZHOU=y
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CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation
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of delay loops
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CONFIG_ENDIAN_BIG - define if big endian (default is little
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endian)
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CONFIG_RAM_SIZE - Describes the installed DRAM (SRAM in this case):
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CONFIG_RAM_SIZE=0x00010000 (64Kb)
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CONFIG_RAM_START - The start address of installed DRAM
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CONFIG_RAM_START=0x20000000
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CONFIG_STM32_CCMEXCLUDE - Exclude CCM SRAM from the HEAP
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CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to boards that
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have LEDs
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CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt
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stack. If defined, this symbol is the size of the interrupt
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stack in bytes. If not defined, the user task stacks will be
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used during interrupt handling.
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CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions
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CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to board architecture.
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Individual subsystems can be enabled:
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AHB
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---
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CONFIG_STM32_DMA1
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CONFIG_STM32_DMA2
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CONFIG_STM32_CRC
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CONFIG_STM32_ETHMAC
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CONFIG_STM32_OTGFS
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CONFIG_STM32_IWDG
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CONFIG_STM32_PWR -- Required for RTC
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APB1 (low speed)
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----------------
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CONFIG_STM32_BKP
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CONFIG_STM32_TIM2
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CONFIG_STM32_TIM3
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CONFIG_STM32_TIM4
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CONFIG_STM32_TIM5
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CONFIG_STM32_TIM6
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CONFIG_STM32_TIM7
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CONFIG_STM32_USART2
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CONFIG_STM32_USART3
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CONFIG_STM32_UART4
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CONFIG_STM32_UART5
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CONFIG_STM32_SPI2
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CONFIG_STM32_SPI3
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CONFIG_STM32_I2C1
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CONFIG_STM32_I2C2
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CONFIG_STM32_CAN1
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CONFIG_STM32_CAN2
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CONFIG_STM32_DAC1
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CONFIG_STM32_DAC2
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CONFIG_STM32_WWDG
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APB2 (high speed)
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-----------------
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CONFIG_STM32_TIM1
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CONFIG_STM32_SPI1
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CONFIG_STM32_USART1
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CONFIG_STM32_ADC1
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CONFIG_STM32_ADC2
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Timer and I2C devices may need to the following to force power to be applied
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unconditionally at power up. (Otherwise, the device is powered when it is
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initialized).
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CONFIG_STM32_FORCEPOWER
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Timer devices may be used for different purposes. One special purpose is
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to generate modulated outputs for such things as motor control. If CONFIG_STM32_TIMn
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is defined (as above) then the following may also be defined to indicate that
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the timer is intended to be used for pulsed output modulation, ADC conversion,
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or DAC conversion. Note that ADC/DAC require two definition: Not only do you have
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to assign the timer (n) for used by the ADC or DAC, but then you also have to
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configure which ADC or DAC (m) it is assigned to.
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CONFIG_STM32_TIMn_PWM Reserve timer n for use by PWM, n=1,..,14
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CONFIG_STM32_TIMn_ADC Reserve timer n for use by ADC, n=1,..,14
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CONFIG_STM32_TIMn_ADCm Reserve timer n to trigger ADCm, n=1,..,14, m=1,..,3
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CONFIG_STM32_TIMn_DAC Reserve timer n for use by DAC, n=1,..,14
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CONFIG_STM32_TIMn_DACm Reserve timer n to trigger DACm, n=1,..,14, m=1,..,2
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For each timer that is enabled for PWM usage, we need the following additional
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configuration settings:
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CONFIG_STM32_TIMx_CHANNEL - Specifies the timer output channel {1,..,4}
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NOTE: The STM32 timers are each capable of generating different signals on
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each of the four channels with different duty cycles. That capability is
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not supported by this driver: Only one output channel per timer.
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JTAG Enable settings (by default JTAG-DP and SW-DP are disabled):
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CONFIG_STM32_JTAG_FULL_ENABLE - Enables full SWJ (JTAG-DP + SW-DP)
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CONFIG_STM32_JTAG_NOJNTRST_ENABLE - Enables full SWJ (JTAG-DP + SW-DP)
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but without JNTRST.
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CONFIG_STM32_JTAG_SW_ENABLE - Set JTAG-DP disabled and SW-DP enabled
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STM32107xxx specific device driver settings
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CONFIG_U[S]ARTn_SERIAL_CONSOLE - selects the USARTn (n=1,2,3) or UART
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m (m=4,5) for the console and ttys0 (default is the USART1).
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CONFIG_U[S]ARTn_RXBUFSIZE - Characters are buffered as received.
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This specific the size of the receive buffer
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CONFIG_U[S]ARTn_TXBUFSIZE - Characters are buffered before
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being sent. This specific the size of the transmit buffer
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CONFIG_U[S]ARTn_BAUD - The configure BAUD of the UART. Must be
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CONFIG_U[S]ARTn_BITS - The number of bits. Must be either 7 or 8.
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CONFIG_U[S]ARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity
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CONFIG_U[S]ARTn_2STOP - Two stop bits
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CONFIG_STM32_SPI_INTERRUPTS - Select to enable interrupt driven SPI
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support. Non-interrupt-driven, poll-waiting is recommended if the
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interrupt rate would be to high in the interrupt driven case.
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CONFIG_STM32_SPIx_DMA - Use DMA to improve SPIx transfer performance.
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Cannot be used with CONFIG_STM32_SPI_INTERRUPT.
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CONFIG_STM32_PHYADDR - The 5-bit address of the PHY on the board
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CONFIG_STM32_MII - Support Ethernet MII interface
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CONFIG_STM32_MII_MCO - Use MCO to clock the MII interface
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CONFIG_STM32_RMII - Support Ethernet RMII interface
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CONFIG_STM32_RMII_MCO - Use MCO to clock the RMII interface
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CONFIG_STM32_AUTONEG - Use PHY autonegotiation to determine speed and mode
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CONFIG_STM32_ETHFD - If CONFIG_STM32_AUTONEG is not defined, then this
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may be defined to select full duplex mode. Default: half-duplex
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CONFIG_STM32_ETH100MBPS - If CONFIG_STM32_AUTONEG is not defined, then this
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may be defined to select 100 MBps speed. Default: 10 Mbps
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CONFIG_STM32_PHYSR - This must be provided if CONFIG_STM32_AUTONEG is
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defined. The PHY status register address may diff from PHY to PHY. This
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configuration sets the address of the PHY status register.
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CONFIG_STM32_PHYSR_SPEED - This must be provided if CONFIG_STM32_AUTONEG is
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defined. This provides bit mask indicating 10 or 100MBps speed.
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CONFIG_STM32_PHYSR_100MBPS - This must be provided if CONFIG_STM32_AUTONEG is
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defined. This provides the value of the speed bit(s) indicating 100MBps speed.
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CONFIG_STM32_PHYSR_MODE - This must be provided if CONFIG_STM32_AUTONEG is
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defined. This provide bit mask indicating full or half duplex modes.
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CONFIG_STM32_PHYSR_FULLDUPLEX - This must be provided if CONFIG_STM32_AUTONEG is
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defined. This provides the value of the mode bits indicating full duplex mode.
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CONFIG_STM32_ETH_PTP - Precision Time Protocol (PTP). Not supported
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but some hooks are indicated with this condition.
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Cloudctrl CAN Configuration
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CONFIG_CAN - Enables CAN support (one or both of CONFIG_STM32_CAN1 or
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CONFIG_STM32_CAN2 must also be defined)
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CONFIG_CAN_FIFOSIZE - The size of the circular buffer of CAN messages.
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Default: 8
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CONFIG_CAN_NPENDINGRTR - The size of the list of pending RTR requests.
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Default: 4
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CONFIG_CAN_LOOPBACK - A CAN driver may or may not support a loopback
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mode for testing. The STM32 CAN driver does support loopback mode.
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CONFIG_STM32_CAN1_BAUD - CAN1 BAUD rate. Required if CONFIG_STM32_CAN1
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is defined.
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CONFIG_STM32_CAN2_BAUD - CAN1 BAUD rate. Required if CONFIG_STM32_CAN2
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is defined.
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CONFIG_STM32_CAN_TSEG1 - The number of CAN time quanta in segment 1.
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Default: 6
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CONFIG_STM32_CAN_TSEG2 - the number of CAN time quanta in segment 2.
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Default: 7
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CONFIG_STM32_CAN_REGDEBUG - If CONFIG_DEBUG_FEATURES is set, this will generate an
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dump of all CAN registers.
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Cloudctrl LCD Hardware Configuration
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The LCD driver supports the following LCDs on the STM324xG_EVAL board:
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AM-240320L8TNQW00H (LCD_ILI9320 or LCD_ILI9321) OR
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AM-240320D5TOQW01H (LCD_ILI9325)
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Configuration options.
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CONFIG_LCD_LANDSCAPE - Define for 320x240 display "landscape"
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support. Default is this 320x240 "landscape" orientation
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For the Cloudctrl board, the edge opposite from the row of buttons
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is used as the top of the display in this orientation.
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CONFIG_LCD_RLANDSCAPE - Define for 320x240 display "reverse
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landscape" support. Default is this 320x240 "landscape"
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orientation
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For the Cloudctrl board, the edge next to the row of buttons
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is used as the top of the display in this orientation.
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CONFIG_LCD_PORTRAIT - Define for 240x320 display "portrait"
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orientation support.
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CONFIG_LCD_RPORTRAIT - Define for 240x320 display "reverse
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portrait" orientation support.
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CONFIG_LCD_RDSHIFT - When reading 16-bit gram data, there appears
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to be a shift in the returned data. This value fixes the offset.
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Default 5.
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The LCD driver dynamically selects the LCD based on the reported LCD
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ID value. However, code size can be reduced by suppressing support for
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individual LCDs using:
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CONFIG_STM32_ILI9320_DISABLE (includes ILI9321)
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CONFIG_STM32_ILI9325_DISABLE
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STM32 USB OTG FS Host Driver Support
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Pre-requisites
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CONFIG_USBHOST - Enable USB host support
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CONFIG_STM32_OTGFS - Enable the STM32 USB OTG FS block
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CONFIG_STM32_SYSCFG - Needed
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CONFIG_SCHED_WORKQUEUE - Worker thread support is required
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Options:
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CONFIG_STM32_OTGFS_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words.
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Default 128 (512 bytes)
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CONFIG_STM32_OTGFS_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO
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in 32-bit words. Default 96 (384 bytes)
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|
CONFIG_STM32_OTGFS_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit
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|
words. Default 96 (384 bytes)
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|
CONFIG_STM32_OTGFS_DESCSIZE - Maximum size of a descriptor. Default: 128
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CONFIG_STM32_OTGFS_SOFINTR - Enable SOF interrupts. Why would you ever
|
|
want to do that?
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|
CONFIG_STM32_USBHOST_REGDEBUG - Enable very low-level register access
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|
debug. Depends on CONFIG_DEBUG_FEATURES.
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|
CONFIG_STM32_USBHOST_PKTDUMP - Dump all incoming and outgoing USB
|
|
packets. Depends on CONFIG_DEBUG_FEATURES.
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|
|
|
Configurations
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|
==============
|
|
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Each Cloudctrl configuration is maintained in a sub-directory and
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|
can be selected as follow::
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|
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tools/configure.sh shenzhou:<subdir>
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|
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Where <subdir> is one of the following:
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|
|
|
nsh
|
|
---
|
|
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|
Configures the NuttShell (nsh) located at apps/examples/nsh. The
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|
Configuration enables both the serial and telnet NSH interfaces.::
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|
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|
CONFIG_ARM_TOOLCHAIN_GNU_EABI=y : GNU EABI toolchain for Windows
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|
CONFIG_NSH_DHCPC=n : DHCP is disabled
|
|
CONFIG_NSH_IPADDR=0x0a000002 : Target IP address 10.0.0.2
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|
CONFIG_NSH_DRIPADDR=0x0a000001 : Host IP address 10.0.0.1
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|
|
|
NOTES:
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|
1. This example assumes that a network is connected. During its
|
|
initialization, it will try to negotiate the link speed. If you have
|
|
no network connected when you reset the board, there will be a long
|
|
delay (maybe 30 seconds?) before anything happens. That is the timeout
|
|
before the networking finally gives up and decides that no network is
|
|
available.
|
|
|
|
2. Enabling the ADC example:
|
|
|
|
The only internal signal for ADC testing is the potentiometer input:
|
|
|
|
ADC1_IN10(PC0) Potentiometer
|
|
|
|
External signals are also available on CON5 CN14:
|
|
|
|
ADC_IN8 (PB0) CON5 CN14 Pin2
|
|
ADC_IN9 (PB1) CON5 CN14 Pin1
|
|
|
|
The signal selection is hard-coded in boards/shenzhou/src/up_adc.c: The
|
|
potentiometer input (only) is selected.
|
|
|
|
These selections will enable sampling the potentiometer input at 100Hz using
|
|
Timer 1:
|
|
|
|
CONFIG_ANALOG=y : Enable analog device support
|
|
CONFIG_ADC=y : Enable generic ADC driver support
|
|
CONFIG_ADC_DMA=n : ADC DMA is not supported
|
|
CONFIG_STM32_ADC1=y : Enable ADC 1
|
|
CONFIG_STM32_TIM1=y : Enable Timer 1
|
|
CONFIG_STM32_TIM1_ADC=y : Use Timer 1 for ADC
|
|
CONFIG_STM32_TIM1_ADC1=y : Allocate Timer 1 to ADC 1
|
|
CONFIG_STM32_ADC1_SAMPLE_FREQUENCY=100 : Set sampling frequency to 100Hz
|
|
CONFIG_STM32_ADC1_TIMTRIG=0 : Trigger on timer output 0
|
|
CONFIG_STM32_FORCEPOWER=y : Apply power to TIM1 a boot up time
|
|
CONFIG_EXAMPLES_ADC=y : Enable the apps/examples/adc built-in
|
|
|
|
nxwm
|
|
----
|
|
|
|
This is a special configuration setup for the NxWM window manager
|
|
UnitTest. The NxWM window manager can be found here::
|
|
|
|
apps/graphics/NxWidgets/nxwm
|
|
|
|
The NxWM unit test can be found at::
|
|
|
|
apps/graphics/NxWidgets/UnitTests/nxwm
|
|
|
|
NOTE: JP6 selects between the touchscreen interrupt and the MII
|
|
interrupt. It should be positioned 1-2 to enable the touchscreen
|
|
interrupt.
|
|
|
|
NOTE: Reading from the LCD is not currently supported by this
|
|
configuration. The hardware will support reading from the LCD
|
|
and drivers/lcd/ssd1289.c also supports reading from the LCD.
|
|
This limits some graphics capabilities.
|
|
|
|
Reading from the LCD is not supported only because it has not
|
|
been test. If you get inspired to test this feature, you can
|
|
turn the LCD read functionality on by setting::
|
|
|
|
-CONFIG_LCD_NOGETRUN=y
|
|
+# CONFIG_LCD_NOGETRUN is not set
|
|
|
|
-CONFIG_NX_WRITEONLY=y
|
|
+# CONFIG_NX_WRITEONLY is not set
|
|
|
|
thttpd
|
|
------
|
|
|
|
This builds the THTTPD web server example using the THTTPD and
|
|
the apps/examples/thttpd application.
|
|
|
|
NOTE: This example can only be built using older GCC toolchains
|
|
due to incompatibilities introduced in later GCC releases.
|