302 lines
9.3 KiB
C
302 lines
9.3 KiB
C
/****************************************************************************
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* arch/arm/src/kinetis/kinetis_start.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <assert.h>
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#include <debug.h>
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#include <nuttx/init.h>
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#include "arm_arch.h"
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#include "arm_internal.h"
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#include "kinetis.h"
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#include "hardware/kinetis_smc.h"
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#include "kinetis_mpuinit.h"
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#include "kinetis_userspace.h"
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#include "nvic.h"
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#include "kinetis_start.h"
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/****************************************************************************
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* Private Function prototypes
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****************************************************************************/
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#ifdef CONFIG_ARCH_FPU
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static inline void kinetis_fpuconfig(void);
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Memory Map ***************************************************************
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* 0x0000:0000 - Beginning of the internal FLASH. Address of vectors.
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* Mapped as boot memory address 0x0000:0000 at reset.
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* 0x07ff:ffff - End of flash region (assuming the max of 2MiB of FLASH).
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* 0x1fff:0000 - Start of internal SRAM and start of .data (_sdata)
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* - End of .data (_edata) and start of .bss (_sbss)
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* - End of .bss (_ebss) and bottom of idle stack
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* - _ebss + CONFIG_IDLETHREAD_STACKSIZE = end of idle stack,
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* start of heap. NOTE that the ARM uses a decrement before
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* store stack so that the correct initial value is the end of
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* the stack + 4;
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* 0x2002:ffff - End of internal SRAM and end of heap.
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*
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* NOTE: ARM EABI requires 64 bit stack alignment.
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*/
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#define HEAP_BASE ((uintptr_t)&_ebss + CONFIG_IDLETHREAD_STACKSIZE)
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/* g_idle_topstack: _sbss is the start of the BSS region as defined by the
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* linker script. _ebss lies at the end of the BSS region. The idle task
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* stack starts at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE.
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* The IDLE thread is the thread that the system boots on and, eventually,
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* becomes the IDLE, do nothing task that runs only when there is nothing
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* else to run. The heap continues from there until the end of memory.
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* g_idle_topstack is a read-only variable the provides this computed
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* address.
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*/
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const uintptr_t g_idle_topstack = HEAP_BASE;
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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#ifdef CONFIG_ARMV7M_STACKCHECK
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/* we need to get r10 set before we can allow instrumentation calls */
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void __start(void) noinstrument_function;
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#endif
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/****************************************************************************
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* Name: kinetis_fpuconfig
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*
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* Description:
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* Configure the FPU. Relative bit settings:
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*
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* CPACR: Enables access to CP10 and CP11
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* CONTROL.FPCA: Determines whether the FP extension is active in the
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* current context:
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* FPCCR.ASPEN: Enables automatic FP state preservation, then the
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* processor sets this bit to 1 on successful completion of any FP
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* instruction.
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* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
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* done, the processor reserves space on the stack for the FP state,
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* but does not save that state information to the stack.
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*
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* Software must not change the value of the ASPEN bit or LSPEN bit either:
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* - the CPACR permits access to CP10 and CP11, that give access to the FP
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* extension, or
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* - the CONTROL.FPCA bit is set to 1
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*
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****************************************************************************/
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#ifdef CONFIG_ARCH_FPU
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#ifndef CONFIG_ARMV7M_LAZYFPU
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static inline void kinetis_fpuconfig(void)
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{
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uint32_t regval;
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/* Set CONTROL.FPCA so that we always get the extended context frame
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* with the volatile FP registers stacked above the basic context.
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*/
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regval = getcontrol();
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regval |= CONTROL_FPCA;
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setcontrol(regval);
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/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
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* with the lazy FP context save behavior. Clear FPCCR.ASPEN since we
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* are going to turn on CONTROL.FPCA for all contexts.
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*/
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regval = getreg32(NVIC_FPCCR);
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regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
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putreg32(regval, NVIC_FPCCR);
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/* Enable full access to CP10 and CP11 */
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regval = getreg32(NVIC_CPACR);
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regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
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putreg32(regval, NVIC_CPACR);
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}
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#else
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static inline void kinetis_fpuconfig(void)
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{
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uint32_t regval;
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/* Clear CONTROL.FPCA so that we do not get the extended context frame
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* with the volatile FP registers stacked in the saved context.
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*/
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regval = getcontrol();
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regval &= ~CONTROL_FPCA;
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setcontrol(regval);
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/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
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* with the lazy FP context save behavior. Clear FPCCR.ASPEN since we
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* are going to keep CONTROL.FPCA off for all contexts.
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*/
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regval = getreg32(NVIC_FPCCR);
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regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
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putreg32(regval, NVIC_FPCCR);
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/* Enable full access to CP10 and CP11 */
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regval = getreg32(NVIC_CPACR);
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regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
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putreg32(regval, NVIC_CPACR);
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}
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#endif
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#else
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# define kinetis_fpuconfig()
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#endif
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: _start
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*
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* Description:
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* This is the reset entry point.
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*
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****************************************************************************/
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void __start(void)
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{
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const uint32_t *src;
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uint32_t *dest;
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#ifdef CONFIG_ARMV7M_STACKCHECK
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/* Set the stack limit before we attempt to call any functions */
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__asm__ volatile("sub r10, sp, %0" : :
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"r"(CONFIG_IDLETHREAD_STACKSIZE - 64) :);
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#endif
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/* Disable the watchdog timer */
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kinetis_wddisable();
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/* Clear .bss. We'll do this inline (vs. calling memset) just to be
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* certain that there are no issues with the state of global variables.
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*/
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for (dest = &_sbss; dest < &_ebss; )
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{
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*dest++ = 0;
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}
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/* Move the initialized data section from his temporary holding spot in
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* FLASH into the correct place in SRAM. The correct place in SRAM is
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* give by _sdata and _edata. The temporary location is in FLASH at the
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* end of all of the other read-only data (.text, .rodata) at _eronly.
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*/
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for (src = &_eronly, dest = &_sdata; dest < &_edata; )
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{
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*dest++ = *src++;
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}
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/* Copy any necessary code sections from FLASH to RAM. The correct
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* destination in SRAM is given by _sramfuncs and _eramfuncs. The
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* temporary location is in flash after the data initialization code
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* at _framfuncs
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*/
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#ifdef CONFIG_ARCH_RAMFUNCS
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for (src = &_framfuncs, dest = &_sramfuncs; dest < &_eramfuncs; )
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{
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*dest++ = *src++;
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}
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#endif
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/* Perform clock and Kinetis module initialization (This depends on
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* RAM functions having been copied to RAM).
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*/
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kinetis_clockconfig();
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/* Configure the uart and perform early serial initialization so that we
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* can get debug output as soon as possible (This depends on clock
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* configuration).
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*/
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kinetis_fpuconfig();
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kinetis_lowsetup();
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#ifdef USE_EARLYSERIALINIT
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kinetis_earlyserialinit();
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#endif
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/* For the case of the separate user-/kernel-space build, perform whatever
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* platform specific initialization of the user memory is required.
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* Normally this just means initializing the user space .data and .bss
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* segments.
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*/
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#ifdef CONFIG_BUILD_PROTECTED
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kinetis_userspace();
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#else
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# ifdef KINETIS_MPU
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/* Disable the MPU so that all master may access all buses */
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kinetis_mpudisable();
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# endif
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#endif
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/* Initialize other on-board resources */
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kinetis_boardinitialize();
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/* Show reset status */
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_warn("Reset status: %02x:%02x\n",
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getreg8(KINETIS_SMC_SRSH), getreg8(KINETIS_SMC_SRSL));
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/* Then start NuttX */
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nx_start();
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/* Shouldn't get here */
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for (; ; );
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}
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