260 lines
6.5 KiB
NASM
260 lines
6.5 KiB
NASM
;**************************************************************************
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; arch/z80/src/ez80/ez80f91_init.asm
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;
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; Copyright (C) 2008 Gregory Nutt. All rights reserved.
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; Author: Gregory Nutt <gnutt@nuttx.org>
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions
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; are met:
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;
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; 1. Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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; 2. Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in
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; the documentation and/or other materials provided with the
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; distribution.
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; 3. Neither the name NuttX nor the names of its contributors may be
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; used to endorse or promote products derived from this software
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; without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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; FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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; COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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; BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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; OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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; AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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; LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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; ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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; POSSIBILITY OF SUCH DAMAGE.
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;
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;**************************************************************************
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;**************************************************************************
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; Included Files
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;**************************************************************************
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include "ez80F91.inc"
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;**************************************************************************
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; Constants
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;**************************************************************************
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;PLL_DIV_L EQU %5C
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;PLL_DIV_H EQU %5D
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;PLL_CTL0 EQU %5E
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;PLL_CTL1 EQU %5F
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OSC EQU 0
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PLL EQU 1
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RTC EQU 2
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CLK_MUX_OSC EQU %00
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CLK_MUX_PLL EQU %01
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CLK_MUX_RTC EQU %02
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CHRP_CTL_0 EQU %00
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CHRP_CTL_1 EQU %40
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CHRP_CTL_2 EQU %80
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CHRP_CTL_3 EQU %C0
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LDS_CTL_0 EQU %00
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LDS_CTL_1 EQU %04
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LDS_CTL_2 EQU %08
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LDS_CTL_3 EQU %0C
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LCK_STATUS EQU %20
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INT_LOCK EQU %10
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INT_UNLOCK EQU %08
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INT_LOCK_EN EQU %04
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INT_UNLOCK_EN EQU %02
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PLL_ENABLE EQU %01
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;**************************************************************************
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; Global symbols used
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;**************************************************************************
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; Exported symbols
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xdef _ez80_init
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xdef _ez80_initsysclk
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; Imported symbols
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xref __CS0_LBR_INIT_PARAM
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xref __CS0_UBR_INIT_PARAM
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xref __CS0_CTL_INIT_PARAM
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xref __CS1_LBR_INIT_PARAM
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xref __CS1_UBR_INIT_PARAM
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xref __CS1_CTL_INIT_PARAM
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xref __CS2_LBR_INIT_PARAM
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xref __CS2_UBR_INIT_PARAM
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xref __CS2_CTL_INIT_PARAM
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xref __CS3_LBR_INIT_PARAM
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xref __CS3_UBR_INIT_PARAM
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xref __CS3_CTL_INIT_PARAM
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xref __CS0_BMC_INIT_PARAM
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xref __CS1_BMC_INIT_PARAM
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xref __CS2_BMC_INIT_PARAM
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xref __CS3_BMC_INIT_PARAM
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xref __FLASH_CTL_INIT_PARAM
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xref __FLASH_ADDR_U_INIT_PARAM
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xref __RAM_CTL_INIT_PARAM
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xref __RAM_ADDR_U_INIT_PARAM
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xref _SYS_CLK_SRC
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xref _SYS_CLK_FREQ
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xref _OSC_FREQ
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xref _OSC_FREQ_MULT
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xref __PLL_CTL0_INIT_PARAM
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;**************************************************************************
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; Chip-specific initialization logic
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;**************************************************************************
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; Minimum default initialization for eZ80F91
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define .STARTUP, space = ROM
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segment .STARTUP
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.assume ADL = 1
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_ez80_init:
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; Disable internal peripheral interrupt sources
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ld a, %ff
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out0 (PA_DDR), a ; GPIO
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out0 (PB_DDR), a
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out0 (PC_DDR), a
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out0 (PD_DDR), a
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ld a, %00
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out0 (PA_ALT1), a
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out0 (PB_ALT1), a
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out0 (PC_ALT1), a
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out0 (PD_ALT1), a
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out0 (PA_ALT2), a
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out0 (PB_ALT2), a
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out0 (PC_ALT2), a
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out0 (PD_ALT2), a
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out0 (PLL_CTL1), a ; PLL
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out0 (TMR0_IER), a ; timers
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out0 (TMR1_IER), a
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out0 (TMR2_IER), a
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out0 (TMR3_IER), a
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out0 (UART0_IER), a ; UARTs
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out0 (UART1_IER), a
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out0 (I2C_CTL), a ; I2C
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out0 (EMAC_IEN), a ; EMAC
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out0 (FLASH_IRQ), a ; Flash
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ld a, %04
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out0 (SPI_CTL), a ; SPI
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in0 a, (RTC_CTRL) ; RTC,
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and a, %be
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out0 (RTC_CTRL), a
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; Configure external memory/io
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ld a, __CS0_LBR_INIT_PARAM
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out0 (CS0_LBR), a
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ld a, __CS0_UBR_INIT_PARAM
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out0 (CS0_UBR), a
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ld a, __CS0_BMC_INIT_PARAM
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out0 (CS0_BMC), a
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ld a, __CS0_CTL_INIT_PARAM
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out0 (CS0_CTL), a
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ld a, __CS1_LBR_INIT_PARAM
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out0 (CS1_LBR), a
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ld a, __CS1_UBR_INIT_PARAM
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out0 (CS1_UBR), a
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ld a, __CS1_BMC_INIT_PARAM
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out0 (CS1_BMC), a
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ld a, __CS1_CTL_INIT_PARAM
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out0 (CS1_CTL), a
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ld a, __CS2_LBR_INIT_PARAM
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out0 (CS2_LBR), a
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ld a, __CS2_UBR_INIT_PARAM
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out0 (CS2_UBR), a
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ld a, __CS2_BMC_INIT_PARAM
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out0 (CS2_BMC), a
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ld a, __CS2_CTL_INIT_PARAM
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out0 (CS2_CTL), a
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ld a, __CS3_LBR_INIT_PARAM
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out0 (CS3_LBR), a
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ld a, __CS3_UBR_INIT_PARAM
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out0 (CS3_UBR), a
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ld a, __CS3_BMC_INIT_PARAM
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out0 (CS3_BMC), a
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ld a, __CS3_CTL_INIT_PARAM
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out0 (CS3_CTL), a
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; Enable internal memory
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ld a, __FLASH_ADDR_U_INIT_PARAM
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out0 (FLASH_ADDR_U), a
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ld a, __FLASH_CTL_INIT_PARAM
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out0 (FLASH_CTRL), a
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ld a, __RAM_ADDR_U_INIT_PARAM
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out0 (RAM_ADDR_U), a
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ld a, __RAM_CTL_INIT_PARAM
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out0 (RAM_CTL), a
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ret
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;*****************************************************************************
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; eZ80F91 System Clock Initialization
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;*****************************************************************************
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_ez80_initsysclk:
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; check if the PLL should be used
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ld a, (_ez80_sysclksrc)
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cp a, PLL
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jr nz, _ez80_initsysclkdone
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; Load PLL divider
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ld a, (_ez80_oscfreqmult) ;CR 6202
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out0 (PLL_DIV_L), a
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ld a, (_ez80_oscfreqmult+1)
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out0 (PLL_DIV_H), a
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; Set charge pump and lock criteria
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ld a, __PLL_CTL0_INIT_PARAM
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and a, %CC ; mask off reserved and clock source bits
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out0 (PLL_CTL0), a
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; Enable PLL
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in0 a, (PLL_CTL1)
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set 0, a
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out0 (PLL_CTL1), a
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; Wait for PLL to lock
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_ez80_initsysclkwait:
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in0 a, (PLL_CTL1)
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and a, LCK_STATUS
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cp a, LCK_STATUS
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jr nz, _ez80_initsysclkwait
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; Select PLL as system clock source
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ld a, __PLL_CTL0_INIT_PARAM
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set 0, a
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out0 (PLL_CTL0), a
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_ez80_initsysclkdone:
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ret
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;_ez80_oscfreq:
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; dl _OSC_FREQ
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_ez80_oscfreqmult:
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dw _OSC_FREQ_MULT
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;_ez80_sysclkfreq:
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; dl _SYS_CLK_FREQ
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_ez80_sysclksrc:
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db _SYS_CLK_SRC
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end
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