ea532cb11a
arch/arm64: add initial support for ZYNQ MPSOC arch/arm64: add initial support for ZYNQ MPSOC
72 lines
2.6 KiB
C
72 lines
2.6 KiB
C
/****************************************************************************
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* arch/arm64/include/zynq-mpsoc/chip.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM64_INCLUDE_ZYNQ_MPSOC_CHIP_H
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#define __ARCH_ARM64_INCLUDE_ZYNQ_MPSOC_CHIP_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Number of bytes in x kibibytes/mebibytes/gibibytes */
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#define KB(x) ((x) << 10)
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#define MB(x) (KB(x) << 10)
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#define GB(x) (MB(UINT64_C(x)) << 10)
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/* XilinX ZYNQ_MPSOC Generic Interrupt Controller v2: Distributor & Redist */
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#define CONFIG_GICD_BASE 0xf9010000
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#define CONFIG_GICR_BASE 0xf9020000
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#define CONFIG_GICR_OFFSET 0x20000
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/* XilinX ZYNQ_MPSOC Memory Map: RAM and Device I/O */
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#define CONFIG_RAMBANK1_ADDR 0x00000000
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#define CONFIG_RAMBANK1_SIZE MB(2047)
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#define CONFIG_DEVICEIO_BASEADDR 0xE0000000
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#define CONFIG_DEVICEIO_SIZE MB(512)
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/* U-Boot loads NuttX at this address (kernel_addr_r) */
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#define CONFIG_LOAD_BASE 0x02080000
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#define MPID_TO_CLUSTER_ID(mpid) ((mpid) & ~0xff)
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/****************************************************************************
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* Assembly Macros
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****************************************************************************/
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#ifdef __ASSEMBLY__
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.macro get_cpu_id xreg0
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mrs \xreg0, mpidr_el1
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ubfx \xreg0, \xreg0, #0, #8
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.endm
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_ARM64_INCLUDE_ZYNQ_MPSOC_CHIP_H */
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