c3b406826e
Squashed commit of the following:
Change all remaining occurrences of SAMDL to SAMD2L2.
configs/: Change all remaining occurrences of SAMDL to SAMD2L2
configs/: Change all occurrences of CONFIG_SAMDL_* to CONFIG_SAMD2L2_*
arch/arm/src and include: Rename all directories from samdl to samd2l2. Change all configuration variable names and other usage from SAMDL to SAMD2L2.
994 lines
44 KiB
C
994 lines
44 KiB
C
/************************************************************************************
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* arch/arm/include/samd2l2/chip.h
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*
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* Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_SAMD2L2_CHIP_H
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#define __ARCH_ARM_INCLUDE_SAMD2L2_CHIP_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Get customizations for each supported chip */
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/* SAMD20 Family ********************************************************************/
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/* FEATURE SAM D20J SAM D20G SAM D20E
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* ------------------- ------------------ ------------------ --------
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* No. of pins 64 48 32
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* Flash 256/128/64/32/16KB 256/128/64/32/16KB 256/128/64/32/16KB
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* SRAM 32/16/8/4/2KB 32/16/8/4/2KB 32/16/8/4/2KB
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* Max. Freq. 48MHz 48MHz 48MHz
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* Event channels 8 8 8
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* Timer/counters 8 6 6
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* TC output channels 2 2 2
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* SERCOM 6 6 4
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* ADC channels 20 14 10
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* Comparators 2 2 2
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* DAC channels 1 1 1
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* RTC Yes Yes Yes
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* RTC alarms 1 1 1
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* RTC compare 1 32-bit/2 16-bit 1 32-bit/2 16-bit 1 32-bit/2 16-bit
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* External interrupts 16 16 16
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* PTC X an Y 16x16 12x10 10x6
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* Packages QFN/TQFP QFN/TQFP QFN/TQFP
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* Oscillators XOSC32, XOSC, OSC32K, OSCULP32K, OSC8M, and DFLL48M
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* SW Debug interface Yes Yes Yes
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* Watchdog timer Yes Yes Yes
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*/
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#if defined(CONFIG_ARCH_CHIP_SAMD20E14)
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# define SAMD20 1 /* SAMD20 family */
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# define SAMD20E 1 /* SAMD20E */
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# undef SAMD20G
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# undef SAMD20J
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/* Internal memory */
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# define SAMD2L2_FLASH_SIZE (16*1024) /* 16KB */
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# define SAMD2L2_SRAM0_SIZE (2*1024) /* 2KB */
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# define SAMD2L2_LPRAM_SIZE (0*1024) /* None */
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#elif defined(CONFIG_ARCH_CHIP_SAMD20E15)
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# define SAMD20 1 /* SAMD20 family */
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# define SAMD20E 1 /* SAMD20E */
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# undef SAMD20G
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# undef SAMD20J
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/* Internal memory */
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# define SAMD2L2_FLASH_SIZE (32*1024) /* 32KB */
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# define SAMD2L2_SRAM0_SIZE (4*1024) /* 4KB */
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# define SAMD2L2_LPRAM_SIZE (0*1024) /* None */
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#elif defined(CONFIG_ARCH_CHIP_SAMD20E16)
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# define SAMD20 1 /* SAMD20 family */
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# define SAMD20E 1 /* SAMD20E */
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# undef SAMD20G
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# undef SAMD20J
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/* Internal memory */
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# define SAMD2L2_FLASH_SIZE (64*1024) /* 64KB */
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# define SAMD2L2_SRAM0_SIZE (8*1024) /* 8KB */
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# define SAMD2L2_LPRAM_SIZE (0*1024) /* None */
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#elif defined(CONFIG_ARCH_CHIP_SAMD20E17)
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# define SAMD20 1 /* SAMD20 family */
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# define SAMD20E 1 /* SAMD20E */
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# undef SAMD20G
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# undef SAMD20J
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/* Internal memory */
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# define SAMD2L2_FLASH_SIZE (128*1024) /* 128KB */
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# define SAMD2L2_SRAM0_SIZE (16*1024) /* 16KB */
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# define SAMD2L2_LPRAM_SIZE (0*1024) /* None */
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#elif defined(CONFIG_ARCH_CHIP_SAMD20E18)
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# define SAMD20 1 /* SAMD20 family */
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# define SAMD20E 1 /* SAMD20E */
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# undef SAMD20G
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# undef SAMD20J
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/* Internal memory */
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# define SAMD2L2_FLASH_SIZE (256*1024) /* 256KB */
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# define SAMD2L2_SRAM0_SIZE (32*1024) /* 32KB */
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# define SAMD2L2_LPRAM_SIZE (0*1024) /* None */
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#elif defined(CONFIG_ARCH_CHIP_SAMD20G14)
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# define SAMD20 1 /* SAMD20 family */
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# undef SAMD20E
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# define SAMD20G 1 /* SAMD20G */
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# undef SAMD20J
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/* Internal memory */
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# define SAMD2L2_FLASH_SIZE (16*1024) /* 16KB */
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# define SAMD2L2_SRAM0_SIZE (2*1024) /* 2KB */
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# define SAMD2L2_LPRAM_SIZE (0*1024) /* None */
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#elif defined(CONFIG_ARCH_CHIP_SAMD20G15)
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# define SAMD20 1 /* SAMD20 family */
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# undef SAMD20E
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# define SAMD20G 1 /* SAMD20G */
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# undef SAMD20J
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/* Internal memory */
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# define SAMD2L2_FLASH_SIZE (32*1024) /* 32KB */
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# define SAMD2L2_SRAM0_SIZE (4*1024) /* 4KB */
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# define SAMD2L2_LPRAM_SIZE (0*1024) /* None */
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#elif defined(CONFIG_ARCH_CHIP_SAMD20G16)
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# define SAMD20 1 /* SAMD20 family */
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# undef SAMD20E
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# define SAMD20G 1 /* SAMD20G */
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# undef SAMD20J
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/* Internal memory */
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# define SAMD2L2_FLASH_SIZE (64*1024) /* 64KB */
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# define SAMD2L2_SRAM0_SIZE (8*1024) /* 8KB */
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# define SAMD2L2_LPRAM_SIZE (0*1024) /* None */
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#elif defined(CONFIG_ARCH_CHIP_SAMD20G17)
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# define SAMD20 1 /* SAMD20 family */
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# undef SAMD20E
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# define SAMD20G 1 /* SAMD20G */
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# undef SAMD20J
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/* Internal memory */
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# define SAMD2L2_FLASH_SIZE (128*1024) /* 128KB */
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# define SAMD2L2_SRAM0_SIZE (16*1024) /* 16KB */
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# define SAMD2L2_LPRAM_SIZE (0*1024) /* None */
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#elif defined(CONFIG_ARCH_CHIP_SAMD20G18)
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# define SAMD20 1 /* SAMD20 family */
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# undef SAMD20E
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# define SAMD20G 1 /* SAMD20G */
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# undef SAMD20J
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/* Internal memory */
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# define SAMD2L2_FLASH_SIZE (256*1024) /* 256KB */
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# define SAMD2L2_SRAM0_SIZE (32*1024) /* 32KB */
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# define SAMD2L2_LPRAM_SIZE (0*1024) /* None */
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#elif defined(CONFIG_ARCH_CHIP_SAMD20J14)
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# define SAMD20 1 /* SAMD20 family */
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# undef SAMD20E
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# undef SAMD20G
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# define SAMD20J 1 /* SAMD20J */
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/* Internal memory */
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# define SAMD2L2_FLASH_SIZE (16*1024) /* 16KB */
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# define SAMD2L2_SRAM0_SIZE (2*1024) /* 2KB */
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# define SAMD2L2_LPRAM_SIZE (0*1024) /* None */
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#elif defined(CONFIG_ARCH_CHIP_SAMD20J15)
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# define SAMD20 1 /* SAMD20 family */
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# undef SAMD20E
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# undef SAMD20G
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# define SAMD20J 1 /* SAMD20J */
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/* Internal memory */
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# define SAMD2L2_FLASH_SIZE (32*1024) /* 32KB */
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# define SAMD2L2_SRAM0_SIZE (4*1024) /* 4KB */
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# define SAMD2L2_LPRAM_SIZE (0*1024) /* None */
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#elif defined(CONFIG_ARCH_CHIP_SAMD20J16)
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# define SAMD20 1 /* SAMD20 family */
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# undef SAMD20E
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# undef SAMD20G
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# define SAMD20J 1 /* SAMD20J */
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/* Internal memory */
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# define SAMD2L2_FLASH_SIZE (64*1024) /* 64KB */
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# define SAMD2L2_SRAM0_SIZE (8*1024) /* 8KB */
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# define SAMD2L2_LPRAM_SIZE (0*1024) /* None */
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#elif defined(CONFIG_ARCH_CHIP_SAMD20J17)
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# define SAMD20 1 /* SAMD20 family */
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# undef SAMD20E
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# undef SAMD20G
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# define SAMD20J 1 /* SAMD20J */
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/* Internal memory */
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# define SAMD2L2_FLASH_SIZE (128*1024) /* 128KB */
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# define SAMD2L2_SRAM0_SIZE (16*1024) /* 16KB */
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# define SAMD2L2_LPRAM_SIZE (0*1024) /* None */
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#elif defined(CONFIG_ARCH_CHIP_SAMD20J18)
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# define SAMD20 1 /* SAMD20 family */
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# undef SAMD20E
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# undef SAMD20G
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# define SAMD20J 1 /* SAMD20J */
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/* Internal memory */
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# define SAMD2L2_FLASH_SIZE (256*1024) /* 256KB */
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# define SAMD2L2_SRAM0_SIZE (32*1024) /* 32KB */
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# define SAMD2L2_LPRAM_SIZE (0*1024) /* None */
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#else
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# undef SAMD20 /* Not SAMD20 family */
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# undef SAMD20E
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# undef SAMD20G
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# undef SAMD20J
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#endif
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/* SAMD20 Peripherals */
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#if defined(SAMD20E)
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# define SAMD2L2_NEVENTS 8 /* 8 event channels */
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# define SAMD2L2_NTC 6 /* 6 Timer/counters */
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# define SAMD2L2_NTCOUT 2 /* 2 TC output channels */
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# define SAMD2L2_NTCC 0 /* No TC control channels */
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# define SAMD2L2_NTCCOUT 0 /* No TCC output channels */
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# define SAMD2L2_NDMACHAN 0 /* No DMA channels */
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# define SAMD2L2_NUSBIF 0 /* No USB interface */
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# define SAMD2L2_NAES 0 /* No AES engine */
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# define SAMD2L2_NCCL 0 /* No Counfigurable Custom Logic */
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# define SAMD2L2_NTRNG 0 /* No True random number generator */
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# define SAMD2L2_NSERCOM 4 /* 4 SERCOM */
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# define SAMD2L2_NI2S 0 /* No I2S */
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# define SAMD2L2_NADC 10 /* 10 ADC channels */
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# define SAMD2L2_NCMP 2 /* 2 Comparators */
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# define SAMD2L2_NDAC 1 /* 1 DAC channel */
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# define SAMD2L2_NOPAMP 0 /* No OpAmps */
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# define SAMD2L2_RTC 1 /* Have RTC */
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# define SAMD2L2_NALARMS 1 /* 1 RTC alarm */
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# define SAMD2L2_NRTCMP 1 /* RTC compare: 1 32-bit/2 16-bit */
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# define SAMD2L2_NEXTINT 16 /* 16 External interrupts */
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# define SAMD2L2_NPTCX 10 /* PTC X */
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# define SAMD2L2_NPTCY 6 /* PTC Y */
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# define SAMD2L2_WDT 1 /* Have watchdog timer */
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#elif defined(SAMD20G)
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# define SAMD2L2_NEVENTS 8 /* 8 event channels */
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# define SAMD2L2_NTC 6 /* 6 Timer/counters */
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# define SAMD2L2_NTCOUT 2 /* 2 TC output channels */
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# define SAMD2L2_NTCC 0 /* No TC control channels */
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# define SAMD2L2_NTCCOUT 0 /* No TCC output channels */
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# define SAMD2L2_NDMACHAN 0 /* No DMA channels */
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# define SAMD2L2_NUSBIF 0 /* No USB interface */
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# define SAMD2L2_NAES 0 /* No AES engine */
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# define SAMD2L2_NCCL 0 /* No Counfigurable Custom Logic */
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# define SAMD2L2_NTRNG 0 /* No True random number generator */
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# define SAMD2L2_NSERCOM 6 /* 6 SERCOM */
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# define SAMD2L2_NI2S 0 /* No I2S */
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# define SAMD2L2_NADC 15 /* 14 ADC channels */
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# define SAMD2L2_NCMP 2 /* 2 Comparators */
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# define SAMD2L2_NDAC 1 /* 1 DAC channel */
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# define SAMD2L2_NOPAMP 0 /* No OpAmps */
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# define SAMD2L2_RTC 1 /* Have RTC */
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# define SAMD2L2_NALARMS 1 /* 1 RTC alarm */
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# define SAMD2L2_NRTCMP 1 /* RTC compare: 1 32-bit/2 16-bit */
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# define SAMD2L2_NEXTINT 16 /* 16 External interrupts */
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# define SAMD2L2_NPTCX 12 /* PTC X */
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# define SAMD2L2_NPTCY 10 /* PTC Y */
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# define SAMD2L2_WDT 1 /* Have watchdog timer */
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#elif defined(SAMD20J)
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# define SAMD2L2_NEVENTS 8 /* 8 event channels */
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# define SAMD2L2_NTC 8 /* 8 Timer/counters */
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# define SAMD2L2_NTCOUT 2 /* 2 TC output channels */
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# define SAMD2L2_NTCC 0 /* No TC control channels */
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# define SAMD2L2_NTCCOUT 0 /* No TCC output channels */
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# define SAMD2L2_NDMACHAN 0 /* No DMA channels */
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# define SAMD2L2_NUSBIF 0 /* No USB interface */
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# define SAMD2L2_NAES 0 /* No AES engine */
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# define SAMD2L2_NCCL 0 /* No Counfigurable Custom Logic */
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# define SAMD2L2_NTRNG 0 /* No True random number generator */
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# define SAMD2L2_NSERCOM 6 /* 6 SERCOM */
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# define SAMD2L2_NI2S 0 /* No I2S */
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# define SAMD2L2_NADC 20 /* 20 ADC channels */
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# define SAMD2L2_NCMP 2 /* 2 Comparators */
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# define SAMD2L2_NDAC 1 /* 1 DAC channel */
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# define SAMD2L2_NOPAMP 0 /* No OpAmps */
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# define SAMD2L2_RTC 1 /* Have RTC */
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# define SAMD2L2_NALARMS 1 /* 1 RTC alarm */
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# define SAMD2L2_NRTCMP 1 /* RTC compare: 1 32-bit/2 16-bit */
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# define SAMD2L2_NEXTINT 16 /* 16 External interrupts */
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# define SAMD2L2_NPTCX 16 /* PTC X */
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# define SAMD2L2_NPTCY 16 /* PTC Y */
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# define SAMD2L2_WDT 1 /* Have watchdog timer */
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#endif
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/* SAMD21 Family ********************************************************************/
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/* FEATURE SAM D21J SAM D21G SAM D21E
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* ------------------- ------------------ ------------------ --------
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* No. of pins 64 48 32
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* Flash 256/128/64/32/16KB 256/128/64/32KB 256/128/64/32KB
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* SRAM 32/16/8/4/2KB 32/16/8/4/2KB 32/16/8/4KB
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* Max. Freq. 48MHz 48MHz 48MHz
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* Event channels 12 12 12
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* Timer/counters 5 3 3
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* TC output channels 2 2 2
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* T/C Control 3 3 3
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* TCC output channels 2 2 2
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* TCC waveform output 8/4/2 8/4/2 6/4/2
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* DMA channels 12 12 12
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* USB interface 1 1 1
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* SERCOM 6 6 4
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* I2S 1 1 1
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* ADC channels 20 14 10
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* Comparators 2 2 2
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* DAC channels 1 1 1
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* RTC Yes Yes Yes
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* RTC alarms 1 1 1
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* RTC compare 1 32-bit/2 16-bit 1 32-bit/2 16-bit 1 32-bit/2 16-bit
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* External interrupts 16 16 16
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* PTC X an Y 16x16 12x10 10x6
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* Packages QFN/TQFP QFN/TQFP/WLCSP QFN/TQFP/UFBGA
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* Oscillators XOSC32, XOSC, OSC32K, OSCULP32K, OSC8M, DFLL48M, and FDPLL96M
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* SW Debug interface Yes Yes Yes
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* Watchdog timer Yes Yes Yes
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*/
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#if defined(CONFIG_ARCH_CHIP_SAMD21E15A) || defined(CONFIG_ARCH_CHIP_SAMD21E15B)
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# define SAMD21 1 /* SAMD21 family */
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# define SAMD21E 1 /* SAMD21E */
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# undef SAMD21G
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# undef SAMD21J
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/* Internal memory */
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# define SAMD2L2_FLASH_SIZE (32*1024) /* 32KB */
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# define SAMD2L2_SRAM0_SIZE (4*1024) /* 4KB */
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# define SAMD2L2_LPRAM_SIZE (0*1024) /* None */
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# if defined(CONFIG_ARCH_CHIP_SAMD21E15A)
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# define SAMD2L2_FLASHRWW_SIZE (0*1024) /* None */
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# else
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# define SAMD2L2_FLASHRWW_SIZE (1*1024) /* 1KB */
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# endif
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#elif defined(CONFIG_ARCH_CHIP_SAMD21E16A) || defined(CONFIG_ARCH_CHIP_SAMD21E16B)
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# define SAMD21 1 /* SAMD21 family */
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# define SAMD21E 1 /* SAMD21E */
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# undef SAMD21G
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# undef SAMD21J
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/* Internal memory */
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# define SAMD2L2_FLASH_SIZE (64*1024) /* 64KB */
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# define SAMD2L2_SRAM0_SIZE (8*1024) /* 8KB */
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# define SAMD2L2_LPRAM_SIZE (0*1024) /* None */
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# if defined(CONFIG_ARCH_CHIP_SAMD21E16A)
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# define SAMD2L2_FLASHRWW_SIZE (0*1024) /* None */
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# else
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# define SAMD2L2_FLASHRWW_SIZE (2*1024) /* 2KB */
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# endif
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#elif defined(CONFIG_ARCH_CHIP_SAMD21E17A)
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# define SAMD21 1 /* SAMD21 family */
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# define SAMD21E 1 /* SAMD21E */
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# undef SAMD21G
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# undef SAMD21J
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/* Internal memory */
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# define SAMD2L2_FLASH_SIZE (128*1024) /* 128KB */
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# define SAMD2L2_FLASHRWW_SIZE (0*1024) /* None */
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# define SAMD2L2_SRAM0_SIZE (16*1024) /* 16KB */
|
|
# define SAMD2L2_LPRAM_SIZE (0*1024) /* None */
|
|
|
|
#elif defined(CONFIG_ARCH_CHIP_SAMD21E18A)
|
|
|
|
# define SAMD21 1 /* SAMD21 family */
|
|
# define SAMD21E 1 /* SAMD21E */
|
|
# undef SAMD21G
|
|
# undef SAMD21J
|
|
|
|
/* Internal memory */
|
|
|
|
# define SAMD2L2_FLASH_SIZE (256*1024) /* 256KB */
|
|
# define SAMD2L2_FLASHRWW_SIZE (0*1024) /* None */
|
|
# define SAMD2L2_SRAM0_SIZE (32*1024) /* 32KB */
|
|
# define SAMD2L2_LPRAM_SIZE (0*1024) /* None */
|
|
|
|
#elif defined(CONFIG_ARCH_CHIP_SAMD21G15A) || defined(CONFIG_ARCH_CHIP_SAMD21G15B)
|
|
|
|
# define SAMD21 1 /* SAMD21 family */
|
|
# undef SAMD21E
|
|
# define SAMD21G 1 /* SAMD21G */
|
|
# undef SAMD21J
|
|
|
|
/* Internal memory */
|
|
|
|
# define SAMD2L2_FLASH_SIZE (32*1024) /* 32KB */
|
|
# define SAMD2L2_SRAM0_SIZE (4*1024) /* 4KB */
|
|
# define SAMD2L2_LPRAM_SIZE (0*1024) /* None */
|
|
|
|
# if defined(CONFIG_ARCH_CHIP_SAMD21G15A)
|
|
# define SAMD2L2_FLASHRWW_SIZE (0*1024) /* None */
|
|
# else
|
|
# define SAMD2L2_FLASHRWW_SIZE (1*1024) /* 1KB */
|
|
# endif
|
|
|
|
#elif defined(CONFIG_ARCH_CHIP_SAMD21G16A) || defined(CONFIG_ARCH_CHIP_SAMD21G16B)
|
|
|
|
# define SAMD21 1 /* SAMD21 family */
|
|
# undef SAMD21E
|
|
# define SAMD21G 1 /* SAMD21G */
|
|
# undef SAMD21J
|
|
|
|
/* Internal memory */
|
|
|
|
# define SAMD2L2_FLASH_SIZE (64*1024) /* 64KB */
|
|
# define SAMD2L2_SRAM0_SIZE (8*1024) /* 8KB */
|
|
# define SAMD2L2_LPRAM_SIZE (0*1024) /* None */
|
|
|
|
# if defined(CONFIG_ARCH_CHIP_SAMD21G16A)
|
|
# define SAMD2L2_FLASHRWW_SIZE (0*1024) /* None */
|
|
# else
|
|
# define SAMD2L2_FLASHRWW_SIZE (2*1024) /* 2KB */
|
|
# endif
|
|
|
|
#elif defined(CONFIG_ARCH_CHIP_SAMD21G17A)
|
|
|
|
# define SAMD21 1 /* SAMD21 family */
|
|
# undef SAMD21E
|
|
# define SAMD21G 1 /* SAMD21G */
|
|
# undef SAMD21J
|
|
|
|
/* Internal memory */
|
|
|
|
# define SAMD2L2_FLASH_SIZE (128*1024) /* 128KB */
|
|
# define SAMD2L2_FLASHRWW_SIZE (0*1024) /* None */
|
|
# define SAMD2L2_SRAM0_SIZE (16*1024) /* 16KB */
|
|
# define SAMD2L2_LPRAM_SIZE (0*1024) /* None */
|
|
|
|
#elif defined(CONFIG_ARCH_CHIP_SAMD21G18A)
|
|
|
|
# define SAMD21 1 /* SAMD21 family */
|
|
# undef SAMD21E
|
|
# define SAMD21G 1 /* SAMD21G */
|
|
# undef SAMD21J
|
|
|
|
/* Internal memory */
|
|
|
|
# define SAMD2L2_FLASH_SIZE (256*1024) /* 256KB */
|
|
# define SAMD2L2_FLASHRWW_SIZE (0*1024) /* None */
|
|
# define SAMD2L2_SRAM0_SIZE (32*1024) /* 32KB */
|
|
# define SAMD2L2_LPRAM_SIZE (0*1024) /* None */
|
|
|
|
#elif defined(CONFIG_ARCH_CHIP_SAMD21J15A) || defined(CONFIG_ARCH_CHIP_SAMD21J15B)
|
|
|
|
# define SAMD21 1 /* SAMD21 family */
|
|
# undef SAMD21E
|
|
# undef SAMD21G
|
|
# define SAMD21J 1 /* SAMD21J */
|
|
|
|
/* Internal memory */
|
|
|
|
# define SAMD2L2_FLASH_SIZE (32*1024) /* 32KB */
|
|
# define SAMD2L2_SRAM0_SIZE (4*1024) /* 4KB */
|
|
# define SAMD2L2_LPRAM_SIZE (0*1024) /* None */
|
|
|
|
# if defined(CONFIG_ARCH_CHIP_SAMD21J15A)
|
|
# define SAMD2L2_FLASHRWW_SIZE (0*1024) /* None */
|
|
# else
|
|
# define SAMD2L2_FLASHRWW_SIZE (1*1024) /* 1KB */
|
|
# endif
|
|
|
|
#elif defined(CONFIG_ARCH_CHIP_SAMD21J16A) || defined(CONFIG_ARCH_CHIP_SAMD21J16B)
|
|
|
|
# define SAMD21 1 /* SAMD21 family */
|
|
# undef SAMD21E
|
|
# undef SAMD21G
|
|
# define SAMD21J 1 /* SAMD21J */
|
|
|
|
/* Internal memory */
|
|
|
|
# define SAMD2L2_FLASH_SIZE (64*1024) /* 64KB */
|
|
# define SAMD2L2_SRAM0_SIZE (8*1024) /* 8KB */
|
|
# define SAMD2L2_LPRAM_SIZE (0*1024) /* None */
|
|
|
|
# if defined(CONFIG_ARCH_CHIP_SAMD21J16A)
|
|
# define SAMD2L2_FLASHRWW_SIZE (0*1024) /* None */
|
|
# else
|
|
# define SAMD2L2_FLASHRWW_SIZE (2*1024) /* 2KB */
|
|
# endif
|
|
|
|
#elif defined(CONFIG_ARCH_CHIP_SAMD21J17A)
|
|
|
|
# define SAMD21 1 /* SAMD21 family */
|
|
# undef SAMD21E
|
|
# undef SAMD21G
|
|
# define SAMD21J 1 /* SAMD21J */
|
|
|
|
/* Internal memory */
|
|
|
|
# define SAMD2L2_FLASH_SIZE (128*1024) /* 128KB */
|
|
# define SAMD2L2_FLASHRWW_SIZE (0*1024) /* None */
|
|
# define SAMD2L2_SRAM0_SIZE (16*1024) /* 16KB */
|
|
# define SAMD2L2_LPRAM_SIZE (0*1024) /* None */
|
|
|
|
#elif defined(CONFIG_ARCH_CHIP_SAMD21J18A)
|
|
|
|
# define SAMD21 1 /* SAMD21 family */
|
|
# undef SAMD21E
|
|
# undef SAMD21G
|
|
# define SAMD21J 1 /* SAMD21J */
|
|
|
|
/* Internal memory */
|
|
|
|
# define SAMD2L2_FLASH_SIZE (256*1024) /* 256KB */
|
|
# define SAMD2L2_FLASHRWW_SIZE (0*1024) /* None */
|
|
# define SAMD2L2_SRAM0_SIZE (32*1024) /* 32KB */
|
|
# define SAMD2L2_LPRAM_SIZE (0*1024) /* None */
|
|
|
|
#else
|
|
|
|
# undef SAMD21 /* Not SAMD21 family */
|
|
# undef SAMD21E
|
|
# undef SAMD21G
|
|
# undef SAMD21J
|
|
|
|
#endif
|
|
|
|
#if defined(SAMD21E)
|
|
# define SAMD2L2_NEVENTS 12 /* 12 event channels */
|
|
# define SAMD2L2_NTC 3 /* 3 Timer/counters */
|
|
# define SAMD2L2_NTCOUT 2 /* 2 TC output channels */
|
|
# define SAMD2L2_NTCC 3 /* 3 TC control channels */
|
|
# define SAMD2L2_NTCCOUT 2 /* 2 TCC output channels */
|
|
# define SAMD2L2_TCC_NWAVEFORMS 8 /* Each TCC has a different number of outputs */
|
|
# define SAMD2L2_NDMACHAN 12 /* 12 DMA channels */
|
|
# define SAMD2L2_NUSBIF 1 /* 1 USB interface */
|
|
# define SAMD2L2_NAES 1 /* 1 AES engine */
|
|
# define SAMD2L2_NCCL 4 /* 4 Counfigurable Custom Logic */
|
|
# define SAMD2L2_NTRNG 1 /* 1 True random number generator */
|
|
# define SAMD2L2_NSERCOM 4 /* 4 SERCOM */
|
|
# define SAMD2L2_NI2S 1 /* 1 I2S */
|
|
# define SAMD2L2_NADC 10 /* 10 ADC channels */
|
|
# define SAMD2L2_NCMP 2 /* 2 Comparators */
|
|
# define SAMD2L2_NDAC 1 /* 1 DAC channel */
|
|
# define SAMD2L2_NOPAMP 3 /* 3 OpAmps */
|
|
# define SAMD2L2_RTC 1 /* Have RTC */
|
|
# define SAMD2L2_NALARMS 1 /* 1 RTC alarm */
|
|
# define SAMD2L2_NRTCMP 1 /* RTC compare: 1 32-bit/2 16-bit */
|
|
# define SAMD2L2_NEXTINT 16 /* 16 External interrupts */
|
|
# define SAMD2L2_NPTCX 10 /* 10x6 */
|
|
# define SAMD2L2_NPTCY 6 /* 10x6*/
|
|
# define SAMD2L2_WDT 1 /* Have watchdog timer */
|
|
#elif defined(SAMD21G)
|
|
# define SAMD2L2_NEVENTS 12 /* 12 event channels */
|
|
# define SAMD2L2_NTC 3 /* 3 Timer/counters */
|
|
# define SAMD2L2_NTCOUT 2 /* 2 TC output channels */
|
|
# define SAMD2L2_NTCC 3 /* 3 TC control channels */
|
|
# define SAMD2L2_NTCCOUT 2 /* 2 TCC output channels */
|
|
# define SAMD2L2_TCC_NWAVEFORMS 8 /* Each TCC has a different number of outputs */
|
|
# define SAMD2L2_NDMACHAN 12 /* 12 DMA channels */
|
|
# define SAMD2L2_NUSBIF 1 /* 1 USB interface */
|
|
# define SAMD2L2_NAES 1 /* 1 AES engine */
|
|
# define SAMD2L2_NCCL 4 /* 4 Counfigurable Custom Logic */
|
|
# define SAMD2L2_NTRNG 1 /* 1 True random number generator */
|
|
# define SAMD2L2_NSERCOM 6 /* 6 SERCOM */
|
|
# define SAMD2L2_NI2S 1 /* 1 I2S */
|
|
# define SAMD2L2_NADC 14 /* 14 ADC channels */
|
|
# define SAMD2L2_NCMP 2 /* 2 Comparators */
|
|
# define SAMD2L2_NDAC 1 /* 1 DAC channel */
|
|
# define SAMD2L2_NOPAMP 3 /* 3 OpAmps */
|
|
# define SAMD2L2_RTC 1 /* Have RTC */
|
|
# define SAMD2L2_NALARMS 1 /* 1 RTC alarm */
|
|
# define SAMD2L2_NRTCMP 1 /* RTC compare: 1 32-bit/2 16-bit */
|
|
# define SAMD2L2_NEXTINT 16 /* 16 External interrupts */
|
|
# define SAMD2L2_NPTCX 12 /* 12x10 */
|
|
# define SAMD2L2_NPTCY 10 /* 12x10 */
|
|
# define SAMD2L2_WDT 1 /* Have watchdog timer */
|
|
#elif defined(SAMD21J)
|
|
# define SAMD2L2_NEVENTS 12 /* 12 event channels */
|
|
# define SAMD2L2_NTC 5 /* 5 Timer/counters */
|
|
# define SAMD2L2_NTCOUT 2 /* 2 TC output channels */
|
|
# define SAMD2L2_NTCC 3 /* 3 TC control channels */
|
|
# define SAMD2L2_NTCCOUT 2 /* 2 TCC output channels */
|
|
# define SAMD2L2_TCC_NWAVEFORMS 8 /* Each TCC has a different number of outputs */
|
|
# define SAMD2L2_NDMACHAN 12 /* 12 DMA channels */
|
|
# define SAMD2L2_NUSBIF 1 /* 1 USB interface */
|
|
# define SAMD2L2_NAES 1 /* 1 AES engine */
|
|
# define SAMD2L2_NCCL 4 /* 4 Counfigurable Custom Logic */
|
|
# define SAMD2L2_NTRNG 1 /* 1 True random number generator */
|
|
# define SAMD2L2_NSERCOM 6 /* 6 SERCOM */
|
|
# define SAMD2L2_NI2S 1 /* 1 I2S */
|
|
# define SAMD2L2_NADC 20 /* 20 ADC channels */
|
|
# define SAMD2L2_NCMP 2 /* 2 Comparators */
|
|
# define SAMD2L2_NDAC 1 /* 1 DAC channel */
|
|
# define SAMD2L2_NOPAMP 3 /* 3 OpAmps */
|
|
# define SAMD2L2_RTC 1 /* Have RTC */
|
|
# define SAMD2L2_NALARMS 1 /* 1 RTC alarm */
|
|
# define SAMD2L2_NRTCMP 1 /* RTC compare: 1 32-bit/2 16-bit */
|
|
# define SAMD2L2_NEXTINT 16 /* 16 External interrupts */
|
|
# define SAMD2L2_NPTCX 16 /* 16x16 */
|
|
# define SAMD2L2_NPTCY 16 /* 16x16*/
|
|
# define SAMD2L2_WDT 1 /* Have watchdog timer */
|
|
#endif
|
|
|
|
/* SAML21 Family ********************************************************************/
|
|
/* FEATURE SAM L21J SAM L21G SAM L21E
|
|
* ------------------- ------------------ ------------------ --------
|
|
* No. of pins 64 48 32
|
|
* Flash 256/128/64KB 256/128/64KB 256/128/64/32KB
|
|
* Flash RWW 8/4/2KB 8/4/2KB 8/4/2/1KB
|
|
* SRAM 32/16/8KB 32/16/8KB 32/16/8/4KB
|
|
* Max. Freq. 48MHz 48MHz 48MHz
|
|
* Event channels 12 12 12
|
|
* Timer/counters 5 3 3
|
|
* TC output channels 2 2 2
|
|
* T/C Control 3 3 3
|
|
* TCC output channels 2 2 2
|
|
* TCC waveform output 8/4/2 8/4/2 6/4/2
|
|
* DMA channels 16 16 16
|
|
* USB interface 1 1 1
|
|
* AES engine 1 1 1
|
|
* CCLs 4 4 4
|
|
* TRNG 1 1 1
|
|
* SERCOM 6 6 4
|
|
* ADC channels 20 14 10
|
|
* Comparators 2 2 2
|
|
* DAC channels 2 2 2
|
|
* OPAMP 3 3 3
|
|
* RTC Yes Yes Yes
|
|
* RTC alarms 1 1 1
|
|
* RTC compare 1 32-bit/2 16-bit 1 32-bit/2 16-bit 1 32-bit/2 16-bit
|
|
* External interrupts 16 16 16
|
|
* PTC X an Y 12x16 8x12 6x10
|
|
* 16x12 12x8 10x6
|
|
* Packages QFN/TQFP QFN/TQFP QFN/TQFP
|
|
* Oscillators XOSC32, XOSC, OSC32K, OSCULP32K, OSC16M, DFLL48M, and FDPLL96M
|
|
* SW Debug interface Yes Yes Yes
|
|
* Watchdog timer Yes Yes Yes
|
|
*/
|
|
|
|
#if defined(CONFIG_ARCH_CHIP_SAML21E15)
|
|
|
|
# define SAML21 1 /* SAML21 family */
|
|
# define SAML21E 1 /* SAML21E */
|
|
# undef SAML21G
|
|
# undef SAML21J
|
|
|
|
/* Internal memory */
|
|
|
|
# define SAMD2L2_FLASH_SIZE (32*1024) /* 32KB */
|
|
# define SAMD2L2_FLASHRWW_SIZE (1*1024) /* 1KB */
|
|
# define SAMD2L2_SRAM0_SIZE (4*1024) /* 4KB */
|
|
# define SAMD2L2_LPRAM_SIZE (2*1024) /* 2KB */
|
|
|
|
/* TCC waveform outputs */
|
|
|
|
# define SAMD2L2_TCC_NWAVEFORMS 2 /* 2 TCC waveform outputs */
|
|
|
|
#elif defined(CONFIG_ARCH_CHIP_SAML21E16)
|
|
|
|
# define SAML21 1 /* SAML21 family */
|
|
# define SAML21E 1 /* SAML21E */
|
|
# undef SAML21G
|
|
# undef SAML21J
|
|
|
|
/* Internal memory */
|
|
|
|
# define SAMD2L2_FLASH_SIZE (64*1024) /* 64KB */
|
|
# define SAMD2L2_FLASHRWW_SIZE (2*1024) /* 2KB */
|
|
# define SAMD2L2_SRAM0_SIZE (8*1024) /* 8KB */
|
|
# define SAMD2L2_LPRAM_SIZE (4*1024) /* 4KB */
|
|
|
|
/* TCC waveform outputs */
|
|
|
|
# define SAMD2L2_TCC_NWAVEFORMS 2 /* 2 TCC waveform outputs */
|
|
|
|
#elif defined(CONFIG_ARCH_CHIP_SAML21E17)
|
|
|
|
# define SAML21 1 /* SAML21 family */
|
|
# define SAML21E 1 /* SAML21E */
|
|
# undef SAML21G
|
|
# undef SAML21J
|
|
|
|
/* Internal memory */
|
|
|
|
# define SAMD2L2_FLASH_SIZE (128*1024) /* 128KB */
|
|
# define SAMD2L2_FLASHRWW_SIZE (4*1024) /* 4KB */
|
|
# define SAMD2L2_SRAM0_SIZE (16*1024) /* 16KB */
|
|
# define SAMD2L2_LPRAM_SIZE (8*1024) /* 8KB */
|
|
|
|
/* TCC waveform outputs */
|
|
|
|
# define SAMD2L2_TCC_NWAVEFORMS 4 /* 4 TCC waveform outputs */
|
|
|
|
#elif defined(CONFIG_ARCH_CHIP_SAML21E18)
|
|
|
|
# define SAML21 1 /* SAML21 family */
|
|
# define SAML21E 1 /* SAML21E */
|
|
# undef SAML21G
|
|
# undef SAML21J
|
|
|
|
/* Internal memory */
|
|
|
|
# define SAMD2L2_FLASH_SIZE (256*1024) /* 256KB */
|
|
# define SAMD2L2_FLASHRWW_SIZE (8*1024) /* 8KB */
|
|
# define SAMD2L2_SRAM0_SIZE (32*1024) /* 32KB */
|
|
# define SAMD2L2_LPRAM_SIZE (8*1024) /* 8KB */
|
|
|
|
/* TCC waveform outputs */
|
|
|
|
# define SAMD2L2_TCC_NWAVEFORMS 6 /* 6 TCC waveform outputs */
|
|
|
|
#elif defined(CONFIG_ARCH_CHIP_SAML21G16)
|
|
|
|
# define SAML21 1 /* SAML21 family */
|
|
# undef SAML21E
|
|
# define SAML21G 1 /* SAML21G */
|
|
# undef SAML21J
|
|
|
|
/* Internal memory */
|
|
|
|
# define SAMD2L2_FLASH_SIZE (64*1024) /* 64KB */
|
|
# define SAMD2L2_FLASHRWW_SIZE (2*1024) /* 2KB */
|
|
# define SAMD2L2_SRAM0_SIZE (8*1024) /* 8KB */
|
|
# define SAMD2L2_LPRAM_SIZE (4*1024) /* 4KB */
|
|
|
|
/* TCC waveform outputs */
|
|
|
|
# define SAMD2L2_TCC_NWAVEFORMS 2 /* 2 TCC waveform outputs */
|
|
|
|
#elif defined(CONFIG_ARCH_CHIP_SAML21G17)
|
|
|
|
# define SAML21 1 /* SAML21 family */
|
|
# undef SAML21E
|
|
# define SAML21G 1 /* SAML21G */
|
|
# undef SAML21J
|
|
|
|
/* Internal memory */
|
|
|
|
# define SAMD2L2_FLASH_SIZE (128*1024) /* 128KB */
|
|
# define SAMD2L2_FLASHRWW_SIZE (4*1024) /* 4KB */
|
|
# define SAMD2L2_SRAM0_SIZE (16*1024) /* 16KB */
|
|
# define SAMD2L2_LPRAM_SIZE (8*1024) /* 8KB */
|
|
|
|
/* TCC waveform outputs */
|
|
|
|
# define SAMD2L2_TCC_NWAVEFORMS 4 /* 4 TCC waveform outputs */
|
|
|
|
#elif defined(CONFIG_ARCH_CHIP_SAML21G18)
|
|
|
|
# define SAML21 1 /* SAML21 family */
|
|
# undef SAML21E
|
|
# define SAML21G 1 /* SAML21G */
|
|
# undef SAML21J
|
|
|
|
/* Internal memory */
|
|
|
|
# define SAMD2L2_FLASH_SIZE (256*1024) /* 256KB */
|
|
# define SAMD2L2_FLASHRWW_SIZE (8*1024) /* 8KB */
|
|
# define SAMD2L2_SRAM0_SIZE (32*1024) /* 32KB */
|
|
# define SAMD2L2_LPRAM_SIZE (8*1024) /* 8KB */
|
|
|
|
/* TCC waveform outputs */
|
|
|
|
# define SAMD2L2_TCC_NWAVEFORMS 8 /* 8 TCC waveform outputs */
|
|
|
|
#elif defined(CONFIG_ARCH_CHIP_SAML21J16)
|
|
|
|
# define SAML21 1 /* SAML21 family */
|
|
# undef SAML21E
|
|
# undef SAML21G
|
|
# define SAML21J 1 /* SAML21J */
|
|
|
|
/* Internal memory */
|
|
|
|
# define SAMD2L2_FLASH_SIZE (64*1024) /* 64KB */
|
|
# define SAMD2L2_FLASHRWW_SIZE (2*1024) /* 2KB */
|
|
# define SAMD2L2_SRAM0_SIZE (8*1024) /* 8KB */
|
|
# define SAMD2L2_LPRAM_SIZE (8*1024) /* 4KB */
|
|
|
|
/* TCC waveform outputs */
|
|
|
|
# define SAMD2L2_TCC_NWAVEFORMS 2 /* 2 TCC waveform outputs */
|
|
|
|
#elif defined(CONFIG_ARCH_CHIP_SAML21J17)
|
|
|
|
# define SAML21 1 /* SAML21 family */
|
|
# undef SAML21E
|
|
# undef SAML21G
|
|
# define SAML21J 1 /* SAML21J */
|
|
|
|
/* Internal memory */
|
|
|
|
# define SAMD2L2_FLASH_SIZE (128*1024) /* 128KB */
|
|
# define SAMD2L2_FLASHRWW_SIZE (4*1024) /* 4KB */
|
|
# define SAMD2L2_SRAM0_SIZE (16*1024) /* 16KB */
|
|
# define SAMD2L2_LPRAM_SIZE (8*1024) /* 8KB */
|
|
|
|
/* TCC waveform outputs */
|
|
|
|
# define SAMD2L2_TCC_NWAVEFORMS 4 /* 4 TCC waveform outputs */
|
|
|
|
#elif defined(CONFIG_ARCH_CHIP_SAML21J18)
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# define SAML21 1 /* SAML21 family */
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# undef SAML21E
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# undef SAML21G
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# define SAML21J 1 /* SAML21J */
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/* Internal memory */
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# define SAMD2L2_FLASH_SIZE (256*1024) /* 256KB */
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# define SAMD2L2_FLASHRWW_SIZE (8*1024) /* 8KB */
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# define SAMD2L2_SRAM0_SIZE (32*1024) /* 32KB */
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# define SAMD2L2_LPRAM_SIZE (8*1024) /* 8KB */
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/* TCC waveform outputs */
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# define SAMD2L2_TCC_NWAVEFORMS 8 /* 8 TCC waveform outputs */
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#else
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# undef SAML21 /* Not SAML21 family */
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# undef SAML21E
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# undef SAML21G
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# undef SAML21J
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#endif
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#if defined(SAML21E)
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# define SAMD2L2_NEVENTS 12 /* 12 event channels */
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# define SAMD2L2_NTC 3 /* 3 Timer/counters */
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# define SAMD2L2_NTCOUT 2 /* 2 TC output channels */
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# define SAMD2L2_NTCC 3 /* 3 TC control channels */
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# define SAMD2L2_NTCCOUT 2 /* 2 TCC output channels */
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# define SAMD2L2_NDMACHAN 16 /* 16 DMA channels */
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# define SAMD2L2_NUSBIF 1 /* 1 USB interface */
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# define SAMD2L2_NAES 1 /* 1 AES engine */
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# define SAMD2L2_NCCL 4 /* 4 Counfigurable Custom Logic */
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# define SAMD2L2_NTRNG 1 /* 1 True random number generator */
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# define SAMD2L2_NSERCOM 4 /* 4 SERCOM */
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# define SAMD2L2_NI2S 0 /* No I2S */
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# define SAMD2L2_NADC 10 /* 10 ADC channels */
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# define SAMD2L2_NCMP 2 /* 2 Comparators */
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# define SAMD2L2_NDAC 2 /* 2 DAC channels */
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# define SAMD2L2_NOPAMP 3 /* 3 OpAmps */
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# define SAMD2L2_RTC 1 /* Have RTC */
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# define SAMD2L2_NALARMS 1 /* 1 RTC alarm */
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# define SAMD2L2_NRTCMP 1 /* RTC compare: 1 32-bit/2 16-bit */
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# define SAMD2L2_NEXTINT 16 /* 16 External interrupts */
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# define SAMD2L2_NPTCX 10 /* PTC X 6 or 10 */
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# define SAMD2L2_NPTCY 10 /* PTC Y 6 or 10*/
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# define SAMD2L2_WDT 1 /* Have watchdog timer */
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#elif defined(SAML21G)
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# define SAMD2L2_NEVENTS 12 /* 12 event channels */
|
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# define SAMD2L2_NTC 3 /* 3 Timer/counters */
|
|
# define SAMD2L2_NTCOUT 2 /* 2 TC output channels */
|
|
# define SAMD2L2_NTCC 3 /* 3 TC control channels */
|
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# define SAMD2L2_NTCCOUT 2 /* 2 TCC output channels */
|
|
# define SAMD2L2_NDMACHAN 16 /* 16 DMA channels */
|
|
# define SAMD2L2_NUSBIF 1 /* 1 USB interface */
|
|
# define SAMD2L2_NAES 1 /* 1 AES engine */
|
|
# define SAMD2L2_NCCL 4 /* 4 Counfigurable Custom Logic */
|
|
# define SAMD2L2_NTRNG 1 /* 1 True random number generator */
|
|
# define SAMD2L2_NSERCOM 6 /* 6 SERCOM */
|
|
# define SAMD2L2_NI2S 0 /* No I2S */
|
|
# define SAMD2L2_NADC 14 /* 14 ADC channels */
|
|
# define SAMD2L2_NCMP 2 /* 2 Comparators */
|
|
# define SAMD2L2_NDAC 2 /* 2 DAC channels */
|
|
# define SAMD2L2_NOPAMP 3 /* 3 OpAmps */
|
|
# define SAMD2L2_RTC 1 /* Have RTC */
|
|
# define SAMD2L2_NALARMS 1 /* 1 RTC alarm */
|
|
# define SAMD2L2_NRTCMP 1 /* RTC compare: 1 32-bit/2 16-bit */
|
|
# define SAMD2L2_NEXTINT 16 /* 16 External interrupts */
|
|
# define SAMD2L2_NPTCX 12 /* PTC X 8 or 12 */
|
|
# define SAMD2L2_NPTCY 12 /* PTC Y 8 or 12*/
|
|
# define SAMD2L2_WDT 1 /* Have watchdog timer */
|
|
#elif defined(SAML21J)
|
|
# define SAMD2L2_NEVENTS 12 /* 12 event channels */
|
|
# define SAMD2L2_NTC 5 /* 5 Timer/counters */
|
|
# define SAMD2L2_NTCOUT 2 /* 2 TC output channels */
|
|
# define SAMD2L2_NTCC 3 /* 3 TC control channels */
|
|
# define SAMD2L2_NTCCOUT 2 /* 2 TCC output channels */
|
|
# define SAMD2L2_NDMACHAN 16 /* 16 DMA channels */
|
|
# define SAMD2L2_NUSBIF 1 /* 1 USB interface */
|
|
# define SAMD2L2_NAES 1 /* 1 AES engine */
|
|
# define SAMD2L2_NCCL 4 /* 4 Counfigurable Custom Logic */
|
|
# define SAMD2L2_NTRNG 1 /* 1 True random number generator */
|
|
# define SAMD2L2_NSERCOM 6 /* 6 SERCOM */
|
|
# define SAMD2L2_NI2S 0 /* No I2S */
|
|
# define SAMD2L2_NADC 20 /* 20 ADC channels */
|
|
# define SAMD2L2_NCMP 2 /* 2 Comparators */
|
|
# define SAMD2L2_NDAC 2 /* 2 DAC channels */
|
|
# define SAMD2L2_NOPAMP 3 /* 3 OpAmps */
|
|
# define SAMD2L2_RTC 1 /* Have RTC */
|
|
# define SAMD2L2_NALARMS 1 /* 1 RTC alarm */
|
|
# define SAMD2L2_NRTCMP 1 /* RTC compare: 1 32-bit/2 16-bit */
|
|
# define SAMD2L2_NEXTINT 16 /* 16 External interrupts */
|
|
# define SAMD2L2_NPTCX 16 /* PTC X 12 or 16 */
|
|
# define SAMD2L2_NPTCY 16 /* PTC Y 12 or 16*/
|
|
# define SAMD2L2_WDT 1 /* Have watchdog timer */
|
|
#endif
|
|
|
|
/* NVIC priority levels *************************************************************/
|
|
/* Each priority field holds a priority value, 0-3. The lower the value, the greater
|
|
* the priority of the corresponding interrupt. The processor implements only
|
|
* bits[7:6] of each field, bits[5:0] read as zero and ignore writes.
|
|
*/
|
|
|
|
#define NVIC_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:6] set is minimum priority */
|
|
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
|
|
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
|
|
#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Five bits of interrupt priority used */
|
|
|
|
/************************************************************************************
|
|
* Public Types
|
|
************************************************************************************/
|
|
|
|
/************************************************************************************
|
|
* Public Data
|
|
************************************************************************************/
|
|
|
|
/************************************************************************************
|
|
* Public Functions
|
|
************************************************************************************/
|
|
|
|
#endif /* __ARCH_ARM_INCLUDE_SAMD2L2_CHIP_H */
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