zhuyanlin b99ba04a8c arch:xtensa: Add SYS_flush_context syscall ... This syscall do nothing as flush context was done in interrupt handler. Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>		2022-05-11 10:48:53 +02:00
..
esp32	xtensa/esp32: Add support to TWAI/CANBus controller	2022-04-06 15:09:46 +03:00
esp32s2	xtensa/esp32s2: Sync IRQ management API with ESP32 and ESP32-S3	2022-03-08 11:36:32 -03:00
esp32s3	xtensa/esp32s3: Add support for GPIO pin interrupts	2022-03-23 07:23:51 +09:00
lx6
lx7	xtensa: Add initial support for ESP32-S3	2022-01-27 13:46:50 -03:00
xtensa	arch/xtensa/src/common/xtensa_coproc.S: Use the first allocated memory	2022-05-04 01:39:07 +08:00
.gitignore
arch.h
elf.h
inttypes.h
irq.h	arch/xtensa: Replace the xcp context with stack context to improve context switching	2022-04-29 02:51:41 +08:00
limits.h
loadstore.h
setjmp.h
simcall.h
spinlock.h
stdarg.h
syscall.h	arch:xtensa: Add SYS_flush_context syscall	2022-05-11 10:48:53 +02:00
types.h