b3b53a6dd4
Master configs/nucleo-f334r8: add example for the SPWM generation (custom STM32 PWM usage) arch/arm/src/stm32/stm32_pwm: fix compilation errors if the upper-half PWM logic is not enabled include/nuttx/drivers/pwm.h: remove dependency on CONFIG_PWM for the upper-half PWM header. This allows compilation for the lower-level PWM drivers even if the upper-half PWM logic is not used. arch/arm/src/stm32/stm32_tim.c: fix compilation error if there is no TIM8 configs/nucleo-f334r8/highpri: remove the upper-half ADC from configuration configs/nucleo-f302r8/highpri: remove the upper-half ADC from configuration configs/stm32f429i-disco/highpri: remove the upper-half ADC from configuration Approved-by: GregoryN <gnutt@nuttx.org>
351 lines
12 KiB
C
351 lines
12 KiB
C
/****************************************************************************
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* configs/nucleo-f334r8/include/board.h
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* include/arch/board/board.h
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*
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* Copyright (C) 2017 Gregory Nutt. All rights reserved.
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* Author: Mateusz Szafoni <raiden00@railab.me>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#ifndef __CONFIG_NUCLEO_F334R8_INCLUDE_BOARD_H
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#define __CONFIG_NUCLEO_F334R8_INCLUDE_BOARD_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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# include <stdbool.h>
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#endif
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#ifdef __KERNEL__
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# include "stm32.h"
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Clocking *****************************************************************/
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/* HSI - Internal 8 MHz RC Oscillator
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* LSI - 32 KHz RC
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* HSE - 8 MHz from MCO output of ST-LINK
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* LSE - 32.768 kHz
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*/
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#define STM32_BOARD_XTAL 8000000ul
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#define STM32_HSI_FREQUENCY 8000000ul
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#define STM32_LSI_FREQUENCY 32000 /* Between 30kHz and 60kHz */
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#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
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#define STM32_LSE_FREQUENCY 32768 /* X2 on board */
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/* PLL source is HSE/1, PLL multipler is 9: PLL frequency is 8MHz (XTAL) x 9 = 72MHz */
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#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC
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#define STM32_CFGR_PLLXTPRE 0
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#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9
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#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL)
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/* Use the PLL and set the SYSCLK source to be the PLL */
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#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL
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#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL
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#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY
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/* AHB clock (HCLK) is SYSCLK (72MHz) */
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#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
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#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY
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#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY
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/* APB2 clock (PCLK2) is HCLK (72MHz) */
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#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK
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#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY
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#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY)
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/* APB2 timers 1, 8, 15-17 and HRTIM1 will receive PCLK2. */
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/* Timers driven from APB2 will be PCLK2 */
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#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY)
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#define STM32_APB1_TIM15_CLKIN (STM32_PCLK2_FREQUENCY)
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#define STM32_APB1_TIM16_CLKIN (STM32_PCLK2_FREQUENCY)
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#define STM32_APB1_TIM17_CLKIN (STM32_PCLK2_FREQUENCY)
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#define STM32_APB1_THRTIM1_CLKIN (STM32_PCLK2_FREQUENCY)
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/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */
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#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2
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#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2)
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/* APB1 timers 2-7 will be twice PCLK1 */
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#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY)
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/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
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* otherwise frequency is 2xAPBx.
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* Note: TIM1,8 are on APB2, others on APB1
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*/
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#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM17_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
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#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
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#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
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#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
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#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
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#define BOARD_HRTIM1_FREQUENCY STM32_HCLK_FREQUENCY
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/* LED definitions **********************************************************/
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/* The Nucleo F334R8 board has three LEDs. Two of these are controlled by
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* logic on the board and are not available for software control:
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*
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* LD1 COM: LD1 default status is red. LD1 turns to green to indicate that
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* communications are in progress between the PC and the
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* ST-LINK/V2-1.
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* LD3 PWR: red LED indicates that the board is powered.
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*
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* And one can be controlled by software:
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*
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* User LD2: green LED is a user LED connected to the I/O PA5 of the
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* STM32F334R8.
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*
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* If CONFIG_ARCH_LEDS is not defined, then the user can control the LED in
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* any way. The following definition is used to access the LED.
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*/
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/* LED index values for use with board_userled() */
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#define BOARD_LED1 0 /* User LD2 */
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#define BOARD_NLEDS 1
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/* LED bits for use with board_userled_all() */
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#define BOARD_LED1_BIT (1 << BOARD_LED1)
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/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board
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* the Nucleo F334R8. The following definitions describe how NuttX controls
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* the LED:
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*
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* SYMBOL Meaning LED1 state
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* ------------------ ----------------------- ----------
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* LED_STARTED NuttX has been started OFF
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* LED_HEAPALLOCATE Heap has been allocated OFF
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* LED_IRQSENABLED Interrupts enabled OFF
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* LED_STACKCREATED Idle stack created ON
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* LED_INIRQ In an interrupt No change
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* LED_SIGNAL In a signal handler No change
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* LED_ASSERTION An assertion failed No change
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* LED_PANIC The system has crashed Blinking
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* LED_IDLE STM32 is is sleep mode Not used
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*/
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#define LED_STARTED 0
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#define LED_HEAPALLOCATE 0
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#define LED_IRQSENABLED 0
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#define LED_STACKCREATED 1
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#define LED_INIRQ 2
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#define LED_SIGNAL 2
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#define LED_ASSERTION 2
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#define LED_PANIC 1
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/* Button definitions *******************************************************/
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/* The Nucleo F334R8 supports two buttons; only one button is controllable
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* by software:
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*
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* B1 USER: user button connected to the I/O PC13 of the STM32F334R8.
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* B2 RESET: push button connected to NRST is used to RESET the
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* STM32F334R8.
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*/
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#define BUTTON_USER 0
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#define NUM_BUTTONS 1
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#define BUTTON_USER_BIT (1 << BUTTON_USER)
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/* Alternate function pin selections ****************************************/
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/* CAN */
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#define GPIO_CAN1_RX GPIO_CAN_RX_2
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#define GPIO_CAN1_TX GPIO_CAN_TX_2
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/* I2C */
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#define GPIO_I2C1_SCL GPIO_I2C1_SCL_3
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#define GPIO_I2C1_SDA GPIO_I2C1_SDA_3
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/* SPI */
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#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1
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#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1
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#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1
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/* TIM */
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#define GPIO_TIM2_CH2OUT GPIO_TIM2_CH2OUT_2
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#define GPIO_TIM2_CH3OUT GPIO_TIM2_CH3OUT_3
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#define GPIO_TIM3_CH1OUT GPIO_TIM3_CH1OUT_2
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#define GPIO_TIM3_CH2OUT GPIO_TIM3_CH2OUT_4
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#define GPIO_TIM4_CH1OUT GPIO_TIM4_CH1OUT_2
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/* USART */
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/* By default the USART2 is connected to STLINK Virtual COM Port:
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* USART2_RX - PA3
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* USART2_TX - PA4
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*/
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#define GPIO_USART2_RX GPIO_USART2_RX_1 /* PA3 */
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#define GPIO_USART2_TX GPIO_USART2_TX_1 /* PA4 */
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#define GPIO_USART1_RX GPIO_USART1_RX_1 /* PA10 */
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#define GPIO_USART1_TX GPIO_USART1_TX_1 /* PA9 */
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/* COMP */
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/* OPAMP */
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#define OPAMP2_VMSEL OPAMP2_VMSEL_PC5
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#define OPAMP2_VPSEL OPAMP2_VPSEL_PB14
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/* Configuration specific to high priority interrupts example:
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* - HRTIM Timer A trigger for ADC if DMA transfer and HRTIM
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* - TIM1 CC1 trigger for ADC if DMA transfer and TIM1 PWM
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* - ADC DMA transfer on DMA1_CH1
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*/
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#ifdef CONFIG_NUCLEOF334R8_HIGHPRI
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#if defined(CONFIG_STM32_HRTIM1) && defined(CONFIG_STM32_ADC1_DMA)
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/* HRTIM - ADC trigger */
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#define HRTIM_TIMA_PRESCALER HRTIM_PRESCALER_128
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#define HRTIM_TIMA_MODE HRTIM_MODE_CONT
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#define HRTIM_TIMA_UPDATE 0
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#define HRTIM_TIMA_RESET 0
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#define HRTIM_ADC_TRG1 HRTIM_ADCTRG13_APER
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#endif /* CONFIG_STM32_HRTIM1 && CONFIG_STM32_ADC1_DMA*/
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#if defined(CONFIG_STM32_TIM1_PWM) && defined(CONFIG_STM32_ADC1_DMA)
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/* TIM1 - ADC trigger */
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#define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC1
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#endif /* CONFIG_STM32_TIM1_PWM && CONFIG_STM32_ADC1_DMA */
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#endif /* CONFIG_NUCLEOF334R8_HIGHPRI */
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#ifdef CONFIG_NUCLEOF334R8_SPWM
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# ifdef CONFIG_NUCLEOF334R8_SPWM_USE_TIM1
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/* TIM1 PWM configuration ***************************************************/
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# define PWM_TIM1_NCHANNELS 4
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# define GPIO_TIM1_CH1OUT GPIO_TIM1_CH1OUT_1 /* TIM1 CH1 - PA8 */
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# define GPIO_TIM1_CH1NOUT GPIO_TIM1_CH1N_3 /* TIM1 CH1N - PA7 */
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/* TIM1 CH2 - PA9 */
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# define GPIO_TIM1_CH2NOUT GPIO_TIM1_CH2N_2 /* TIM1 CH2N - PB0 */
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# define GPIO_TIM1_CH3OUT GPIO_TIM1_CH3OUT_1 /* TIM1 CH3 - PA10 */
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# define GPIO_TIM1_CH3NOUT GPIO_TIM1_CH3N_2 /* TIM1 CH3N - PB1 */
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# define GPIO_TIM1_CH4OUT GPIO_TIM1_CH4OUT_1 /* TIM1 CH4 - PA11 */
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# endif
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# ifdef CONFIG_NUCLEOF334R8_SPWM_USE_HRTIM1
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/* HRTIM configuration ******************************************************/
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# define HRTIM_MASTER_PRESCALER HRTIM_PRESCALER_128
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# define HRTIM_MASTER_MODE HRTIM_MODE_CONT
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# define HRTIM_TIMA_PRESCALER HRTIM_PRESCALER_128
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# define HRTIM_TIMA_MODE (HRTIM_MODE_CONT | HRTIM_MODE_PRELOAD)
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# define HRTIM_TIMA_CH1_SET HRTIM_OUT_SET_PER
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# define HRTIM_TIMA_CH1_RST HRTIM_OUT_RST_CMP1
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# define HRTIM_TIMA_UPDATE HRTIM_UPDATE_MSTU
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# define HRTIM_TIMA_RESET 0
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# define HRTIM_TIMB_PRESCALER HRTIM_PRESCALER_128
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# define HRTIM_TIMB_MODE (HRTIM_MODE_CONT | HRTIM_MODE_PRELOAD)
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# define HRTIM_TIMB_CH1_SET HRTIM_OUT_SET_PER
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# define HRTIM_TIMB_CH1_RST HRTIM_OUT_RST_CMP1
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# define HRTIM_TIMB_UPDATE HRTIM_UPDATE_MSTU
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# define HRTIM_TIMB_RESET 0
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# define HRTIM_TIMC_PRESCALER HRTIM_PRESCALER_128
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# define HRTIM_TIMC_MODE (HRTIM_MODE_CONT | HRTIM_MODE_PRELOAD)
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# define HRTIM_TIMC_CH1_SET HRTIM_OUT_SET_PER
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# define HRTIM_TIMC_CH1_RST HRTIM_OUT_RST_CMP1
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# define HRTIM_TIMC_UPDATE HRTIM_UPDATE_MSTU
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# define HRTIM_TIMC_RESET 0
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# define HRTIM_TIMD_PRESCALER HRTIM_PRESCALER_128
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# define HRTIM_TIMD_MODE (HRTIM_MODE_CONT | HRTIM_MODE_PRELOAD)
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# define HRTIM_TIMD_CH1_SET HRTIM_OUT_SET_PER
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# define HRTIM_TIMD_CH1_RST HRTIM_OUT_RST_CMP1
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# define HRTIM_TIMD_UPDATE HRTIM_UPDATE_MSTU
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# define HRTIM_TIMD_RESET 0
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# define HRTIM_TIME_PRESCALER HRTIM_PRESCALER_128
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# define HRTIM_TIME_MODE (HRTIM_MODE_CONT | HRTIM_MODE_PRELOAD)
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# define HRTIM_TIME_CH1_SET HRTIM_OUT_SET_PER
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# define HRTIM_TIME_CH1_RST HRTIM_OUT_RST_CMP1
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# define HRTIM_TIME_UPDATE HRTIM_UPDATE_MSTU
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# define HRTIM_TIME_RESET 0
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# define HRTIM_MASTER_IRQ HRTIM_IRQ_MCMP1
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# endif
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#endif /* CONFIG_NUCLEOF334R8_SPWM */
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/* DMA channels *************************************************************/
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/* ADC */
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#define ADC1_DMA_CHAN DMACHAN_ADC1 /* DMA1_CH1 */
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#endif /* __CONFIG_NUCLEO_F334R8_INCLUDE_BOARD_H */
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