258 lines
8.0 KiB
C
258 lines
8.0 KiB
C
/****************************************************************************
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* arch/ceva/include/xm6/irq.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* This file should never be included directed but, rather, only indirectly
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* through nuttx/irq.h
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*/
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#ifndef __ARCH_CEVA_INCLUDE_XM6_IRQ_H
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#define __ARCH_CEVA_INCLUDE_XM6_IRQ_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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#endif
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/* Included implementation-dependent register save structure layouts */
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#include <arch/xm6/reg.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Configuration ************************************************************/
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/* If this is kernel build, how many nested system calls should we support? */
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#ifndef CONFIG_SYS_NNEST
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# define CONFIG_SYS_NNEST 2
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#endif
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/* Alternate register names *************************************************/
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#define REG_A0 REG_R0
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#define REG_A1 REG_R1
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#define REG_A2 REG_R2
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#define REG_A3 REG_R3
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#define REG_A4 REG_R4
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#define REG_A5 REG_R5
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#define REG_A6 REG_R6
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#define REG_FP REG_R8
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#define REG_LR REG_RETREG
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#define REG_PC REG_RETREGI
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#define REG_OM REG_MODC /* Operation Mode */
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/* MODA: IRQ enable/disable */
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#define REG_MODA_DEFAULT 0x07f0
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#define REG_MODA_ENABLE 0x07f0
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#define REG_MODA_DISABLE 0x0010
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/* MODC: Operation mode */
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#define REG_OM_DEFAULT 0x20 /* PI and Supervisor */
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/* Note: this is POM field not OM field */
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#define REG_OM_KERNEL 0x00 /* Supervisor Mode */
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#define REG_OM_USER 0x08 /* User0 Mode */
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#define REG_OM_MASK 0x18 /* Mode Mask */
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/* First Level Interrupt (vectors 0-15) */
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#define IRQ_RESET 0x00 /* Vector 0: Reset(not handler as an IRQ) */
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#define IRQ_BOOT 0x01 /* Vector 1: Boot(not handler as an IRQ) */
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#define IRQ_TRAP 0x02 /* Vector 2: Software Interrupt */
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#define IRQ_TRAPE 0x03 /* Vector 3: Emulation Software Interrupt */
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#define IRQ_BI 0x03 /* Vector 3: Breakpoint Interrupt */
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#define IRQ_NMI 0x04 /* Vector 4: Non-Maskable Interrupt */
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#define IRQ_INT0 0x05 /* Vector 5: Maskable Interrupt 0 */
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#define IRQ_INT1 0x06 /* Vector 6: Maskable Interrupt 1 */
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#define IRQ_INT2 0x07 /* Vector 7: Maskable Interrupt 2 */
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#define IRQ_INT3 0x08 /* Vector 8: Maskable Interrupt 3 */
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#define IRQ_INT4 0x09 /* Vector 9: Maskable Interrupt 4 */
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#define IRQ_VINT 0x0a /* Vector 10: Vectored Interrupt */
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#define IRQ_TRAP0 0x0b /* Vector 11: Software Interrupt 0 */
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#define IRQ_TRAP1 0x0c /* Vector 12: Software Interrupt 1 */
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#define IRQ_TRAP2 0x0d /* Vector 13: Software Interrupt 2 */
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#define IRQ_TRAP3 0x0e /* Vector 14: Software Interrupt 3 */
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#define IRQ_PABP 0x03 /* Vector 3: Program Address Breakpoint */
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/* Second Level interrupts (vectors >= 16).
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* These definitions are chip-specific.
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*/
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#define IRQ_VINT_FIRST 16 /* Vector number of the first VINT interrupt */
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/****************************************************************************
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* Public Types
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****************************************************************************/
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#ifndef __ASSEMBLY__
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/* This structure represents the return state from a system call */
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#ifdef CONFIG_LIB_SYSCALL
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struct xcpt_syscall_s
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{
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uint32_t saved_pc;
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uint32_t saved_om;
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};
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#endif
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/* The following structure is included in the TCB and defines the complete
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* state of the thread.
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*/
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struct xcptcontext
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{
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#ifndef CONFIG_DISABLE_SIGNALS
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/* The following function pointer is non-zero if there
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* are pending signals to be processed.
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*/
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void *sigdeliver; /* Actual type is sig_deliver_t */
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/* These are saved copies of the context used during
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* signal processing.
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*/
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uint32_t *saved_regs;
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# ifdef CONFIG_BUILD_PROTECTED
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/* This is the saved address to use when returning from a user-space
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* signal handler.
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*/
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uint32_t sigreturn;
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# endif
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#endif
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#ifdef CONFIG_LIB_SYSCALL
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/* The following array holds the return address and operation mode
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* needed to return from each nested system call.
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*/
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uint8_t nsyscalls;
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struct xcpt_syscall_s syscall[CONFIG_SYS_NNEST];
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#endif
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/* Register save area with XCPTCONTEXT_SIZE, only valid when:
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* 1.The task isn't running or
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* 2.The task is interrupted
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* otherwise task is running, and regs contain the stale value.
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*/
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uint32_t *regs;
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};
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#endif
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/****************************************************************************
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* Inline functions
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****************************************************************************/
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#ifndef __ASSEMBLY__
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/* Name: up_irq_save, up_irq_restore, and friends.
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*
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* NOTE: This function should never be called from application code and,
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* as a general rule unless you really know what you are doing, this
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* function should not be called directly from operation system code either:
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* Typically, the wrapper functions, enter_critical_section() and
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* leave_critical section(), are probably what you really want.
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*/
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/* Get/set the MODA register, here is the irq related bits:
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* Bit [4] Interrupt enable (RW)
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* Bit [5] Interrupt mask for INT0 (RW)
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* Bit [6] Interrupt mask for INT1 (RW)
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* Bit [7] Interrupt mask for INT2 (RW)
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* Bit [8] Interrupt mask for INT3 (RW)
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* Bit [9] Interrupt mask for INT4 (RW)
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* Bit [10] Interrupt mask for VINT (RW)
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* Bit [11] Interrupt pending for INT0 (RO)
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* Bit [12] Interrupt pending for INT1 (RO)
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* Bit [13] Interrupt pending for INT2 (RO)
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* Bit [14] Interrupt pending for INT3 (RO)
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* Bit [15] Interrupt pending for INT4 (RO)
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* Bit [16] Interrupt pending for INTV (RO)
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* All writable bits are clear by hardware during reset.
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*
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* We manipulate the individual mask bits instead of global enable bit since:
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* 1.Global IE not only mask INTX request but also mask TRAPX instruction.
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* 2.Hardware always enable global IE after the interrupt return.
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* Both behavior don't match the nuttx requirement.
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*/
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static inline uint32_t getmoda(void)
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{
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uint32_t moda;
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__asm__ __volatile__("mov moda.ui, %0.ui\nnop #0x02" : "=r"(moda));
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return moda;
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}
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static inline void setmoda(uint32_t moda)
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{
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__asm__ __volatile__("nop #0x04\nnop\nmovp %0.ui, moda.ui" : : "r"(moda));
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}
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/* Return the current value of the stack pointer */
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static inline uint32_t up_getsp(void)
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{
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uint32_t sp;
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__asm__ __volatile__("mov sp.ui, %0.ui" : "=r"(sp));
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return sp;
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}
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static inline void up_irq_disable(void)
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{
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setmoda(REG_MODA_DISABLE);
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}
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static inline irqstate_t up_irq_save(void)
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{
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irqstate_t flags = getmoda();
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up_irq_disable();
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return flags;
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}
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static inline void up_irq_enable(void)
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{
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setmoda(REG_MODA_ENABLE);
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}
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static inline void up_irq_restore(irqstate_t flags)
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{
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setmoda(flags);
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}
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_CEVA_INCLUDE_XM6_IRQ_H */
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