Ville Juven c2b69cc2c9 RISC-V: mtimer register via SBI when S-mode is in use ... Cannot access the memory mapped registers directly when the kernel runs in S-mode, must forward the access to SBI.		2022-04-14 16:43:34 +08:00
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include	RISC-V: Combine 3 variables that depend on CPU amount into one	2022-04-12 01:59:35 +08:00
src	RISC-V: mtimer register via SBI when S-mode is in use	2022-04-14 16:43:34 +08:00
Kconfig	arch/riscv: Move toolchain config to arch/risc-v/Kconfig like xtensa	2022-04-12 21:01:14 +03:00