516 lines
20 KiB
C
516 lines
20 KiB
C
/****************************************************************************
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* boards/arm/samd2l2/samd20-xplained/include/board.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __BOARDS_ARM_SAMD2L2_SAMD20_XPLAINED_INCLUDE_BOARD_H
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#define __BOARDS_ARM_SAMD2L2_SAMD20_XPLAINED_INCLUDE_BOARD_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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# ifdef CONFIG_SAMD2L2_GPIOIRQ
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# include <arch/irq.h>
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# endif
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Clocking *****************************************************************/
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/* Overview
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*
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* OSC8M Output = 8MHz
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* `- GCLK1 Input = 8MHz Prescaler = 1 output = 8MHz
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* `- DFLL Input = 8MHz Multiplier = 6 output = 48MHz
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* `- GCLK0 Input = 48MHz Prescaler = 1 output = 48MHz
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* `- PM Input = 48Mhz CPU divider = 1 CPU frequency = 48MHz
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* APBA divider = 1 APBA frequency = 48MHz
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* APBB divider = 1 APBB frequency = 48MHz
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* APBC divider = 1 APBC frequency = 48MHz
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*
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* The SAMD20 Xplained Pro has one on-board crystal:
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*
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* XC101 32.768KHz XOSC32
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*
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* REVISIT: Not currently used, may want to use as GCLK1 source with
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* DFLL multiplier of ((48000000+16384)/32768) = 1465 which would yield
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* a clock of 48,005,120 MHz.
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*/
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/* XOSC Configuration -- Not available
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*
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* BOARD_XOSC_ENABLE - Boolean (defined / not defined)
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* BOARD_XOSC_FREQUENCY - In Hz
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* BOARD_XOSC_STARTUPTIME - See SYSCTRL_XOSC_STARTUP_* definitions
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* BOARD_XOSC_ISCRYSTAL - Boolean (defined / not defined)
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* BOARD_XOSC_AMPGC - Boolean (defined / not defined)
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* BOARD_XOSC_ONDEMAND - Boolean (defined / not defined)
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* BOARD_XOSC_RUNINSTANDBY - Boolean (defined / not defined)
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*/
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#undef BOARD_XOSC_ENABLE
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#define BOARD_XOSC_FREQUENCY 12000000UL
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#define BOARD_XOSC_STARTUPTIME SYSCTRL_XOSC_STARTUP_1S
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#define BOARD_XOSC_ISCRYSTAL 1
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#define BOARD_XOSC_AMPGC 1
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#define BOARD_XOSC_ONDEMAND 1
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#undef BOARD_XOSC_RUNINSTANDBY
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/* XOSC32 Configuration -- Not used
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*
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* BOARD_XOSC32K_ENABLE - Boolean (defined / not defined)
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* BOARD_XOSC32K_FREQUENCY - In Hz
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* BOARD_XOSC32K_STARTUPTIME - See SYSCTRL_XOSC32K_STARTUP_* definitions
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* BOARD_XOSC32K_ISCRYSTAL - Boolean (defined / not defined)
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* BOARD_XOSC32K_AAMPEN - Boolean (defined / not defined)
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* BOARD_XOSC32K_EN1KHZ - Boolean (defined / not defined)
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* BOARD_XOSC32K_EN32KHZ - Boolean (defined / not defined)
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* BOARD_XOSC32K_ONDEMAND - Boolean (defined / not defined)
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* BOARD_XOSC32K_RUNINSTANDBY - Boolean (defined / not defined)
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*/
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#undef BOARD_XOSC32K_ENABLE
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#define BOARD_XOSC32K_FREQUENCY 32768 /* 32.768KHz XTAL */
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#define BOARD_XOSC32K_STARTUPTIME SYSCTRL_XOSC32K_STARTUP_2S
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#define BOARD_XOSC32K_ISCRYSTAL 1
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#define BOARD_XOSC32K_AAMPEN 1
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#undef BOARD_XOSC32K_EN1KHZ
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#define BOARD_XOSC32K_EN32KHZ 1
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#define BOARD_XOSC32K_ONDEMAND 1
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#undef BOARD_XOSC32K_RUNINSTANDBY
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/* OSC32 Configuration -- not used
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*
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* BOARD_OSC32K_ENABLE - Boolean (defined / not defined)
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* BOARD_OSC32K_FREQUENCY - In Hz
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* BOARD_OSC32K_STARTUPTIME - See SYSCTRL_OSC32K_STARTUP_* definitions
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* BOARD_OSC32K_EN1KHZ - Boolean (defined / not defined)
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* BOARD_OSC32K_EN32KHZ - Boolean (defined / not defined)
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* BOARD_OSC32K_ONDEMAND - Boolean (defined / not defined)
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* BOARD_OSC32K_RUNINSTANDBY - Boolean (defined / not defined)
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*/
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#undef BOARD_OSC32K_ENABLE
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#define BOARD_OSC32K_FREQUENCY 32768 /* 32.768kHz internal oscillator */
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#define BOARD_OSC32K_STARTUPTIME SYSCTRL_OSC32K_STARTUP_4MS
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#define BOARD_OSC32K_EN1KHZ 1
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#define BOARD_OSC32K_EN32KHZ 1
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#define BOARD_OSC32K_ONDEMAND 1
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#undef BOARD_OSC32K_RUNINSTANDBY
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/* OSC8M Configuration -- always enabled
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*
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* BOARD_OSC8M_PRESCALER - See SYSCTRL_OSC8M_PRESC_DIV* definitions
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* BOARD_OSC8M_ONDEMAND - Boolean (defined / not defined)
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* BOARD_OSC8M_RUNINSTANDBY - Boolean (defined / not defined)
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*/
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#define BOARD_OSC8M_PRESCALER SYSCTRL_OSC8M_PRESC_DIV1
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#define BOARD_OSC8M_ONDEMAND 1
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#undef BOARD_OSC8M_RUNINSTANDBY
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#define BOARD_OSC8M_FREQUENCY 8000000 /* 8MHz high-accuracy internal oscillator */
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/* OSCULP32K Configuration -- not used. */
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#define BOARD_OSCULP32K_FREQUENCY 32000 /* 32kHz ultra-low-power internal oscillator */
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/* Digital Frequency Locked Loop configuration. In closed-loop mode, the
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* DFLL output frequency (Fdfll) is given by:
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*
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* Fdfll = DFLLmul * Frefclk
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* = 6 * 8000000 = 48MHz
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*
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* Where the reference clock is Generic Clock Channel 0 output of GLCK1.
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* GCLCK1 provides OSC8M, undivided.
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*
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* When operating in open-loop mode, the output frequency of the DFLL will
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* be determined by the values written to the DFLL Coarse Value bit group
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* and the DFLL Fine Value bit group in the DFLL Value register.
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*
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* BOARD_DFLL_OPENLOOP - Boolean (defined / not defined)
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* BOARD_DFLL_TRACKAFTERFINELOCK - Boolean (defined / not defined)
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* BOARD_DFLL_KEEPLOCKONWAKEUP - Boolean (defined / not defined)
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* BOARD_DFLL_ENABLECHILLCYCLE - Boolean (defined / not defined)
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* BOARD_DFLL_QUICKLOCK - Boolean (defined / not defined)
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* BOARD_DFLL_ONDEMAND - Boolean (defined / not defined)
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*
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* Closed loop mode only:
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* BOARD_DFLL_GCLKGEN - GCLK index
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* BOARD_DFLL_MULTIPLIER - Value
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* BOARD_DFLL_MAXCOARSESTEP - Value
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* BOARD_DFLL_MAXFINESTEP - Value
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*
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* BOARD_DFLL_FREQUENCY - The resulting frequency
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*/
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#define BOARD_DFLL_ENABLE 1
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#define BOARD_DFLL_OPENLOOP 1
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#undef BOARD_DFLL_ONDEMAND
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#undef BOARD_DFLL_RUNINSTANDBY
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/* DFLL closed loop mode configuration */
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#define BOARD_DFLL_SRCGCLKGEN 1
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#define BOARD_DFLL_MULTIPLIER 6
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#define BOARD_DFLL_QUICKLOCK 1
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#define BOARD_DFLL_TRACKAFTERFINELOCK 1
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#define BOARD_DFLL_KEEPLOCKONWAKEUP 1
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#define BOARD_DFLL_ENABLECHILLCYCLE 1
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#define BOARD_DFLL_MAXCOARSESTEP (0x1f / 4)
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#define BOARD_DFLL_MAXFINESTEP (0xff / 4)
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#define BOARD_DFLL_FREQUENCY (48000000)
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/* GCLK Configuration
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*
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* Global enable/disable.
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*
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* BOARD_GCLK_ENABLE - Boolean (defined / not defined)
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*
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* For n=1-7:
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* BOARD_GCLKn_ENABLE - Boolean (defined / not defined)
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*
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* For n=0-8:
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* BOARD_GCLKn_RUN_IN_STANDBY - Boolean (defined / not defined)
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* BOARD_GCLKn_CLOCK_SOURCE - See GCLK_GENCTRL_SRC_* definitions
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* BOARD_GCLKn_PRESCALER - Value
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* BOARD_GCLKn_OUTPUT_ENABLE - Boolean (defined / not defined)
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*/
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#define BOARD_GCLK_ENABLE 1
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/* GCLK generator 0 (Main Clock) - Source is the DFLL */
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#undef BOARD_GCLK0_RUN_IN_STANDBY
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#define BOARD_GCLK0_CLOCK_SOURCE GCLK_GENCTRL_SRC_DFLL48M
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#define BOARD_GCLK0_PRESCALER 1
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#undef BOARD_GCLK0_OUTPUT_ENABLE
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#define BOARD_GCLK0_FREQUENCY (BOARD_DFLL_FREQUENCY / BOARD_GCLK0_PRESCALER)
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/* Configure GCLK generator 1 - Drives the DFLL */
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#define BOARD_GCLK1_ENABLE 1
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#undef BOARD_GCLK1_RUN_IN_STANDBY
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#define BOARD_GCLK1_CLOCK_SOURCE GCLK_GENCTRL_SRC_OSC8M
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#define BOARD_GCLK1_PRESCALER 1
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#undef BOARD_GCLK1_OUTPUT_ENABLE
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#define BOARD_GCLK1_FREQUENCY (BOARD_OSC8M_FREQUENCY / BOARD_GCLK1_PRESCALER)
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/* Configure GCLK generator 2 (RTC) */
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#undef BOARD_GCLK2_ENABLE
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#undef BOARD_GCLK2_RUN_IN_STANDBY
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#define BOARD_GCLK2_CLOCK_SOURCE GCLK_GENCTRL_SRC_OSC32K
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#define BOARD_GCLK2_PRESCALER 32
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#undef BOARD_GCLK2_OUTPUT_ENABLE
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#define BOARD_GCLK2_FREQUENCY (BOARD_OSC8M_FREQUENCY / BOARD_GCLK2_PRESCALER)
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/* Configure GCLK generator 3 */
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#undef BOARD_GCLK3_ENABLE
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#undef BOARD_GCLK3_RUN_IN_STANDBY
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#define BOARD_GCLK3_CLOCK_SOURCE GCLK_GENCTRL_SRC_OSC8M
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#define BOARD_GCLK3_PRESCALER 1
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#undef BOARD_GCLK3_OUTPUT_ENABLE
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#define BOARD_GCLK3_FREQUENCY (BOARD_OSC8M_FREQUENCY / BOARD_GCLK3_PRESCALER)
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/* Configure GCLK generator 4 */
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#undef BOARD_GCLK4_ENABLE
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#undef BOARD_GCLK4_RUN_IN_STANDBY
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#define BOARD_GCLK4_CLOCK_SOURCE GCLK_GENCTRL_SRC_OSC8M
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#define BOARD_GCLK4_PRESCALER 1
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#undef BOARD_GCLK4_OUTPUT_ENABLE
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#define BOARD_GCLK4_FREQUENCY (BOARD_OSC8M_FREQUENCY / BOARD_GCLK4_PRESCALER)
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/* Configure GCLK generator 5 */
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#undef BOARD_GCLK5_ENABLE
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#undef BOARD_GCLK5_RUN_IN_STANDBY
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#define BOARD_GCLK5_CLOCK_SOURCE GCLK_GENCTRL_SRC_OSC8M
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#define BOARD_GCLK5_PRESCALER 1
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#undef BOARD_GCLK5_OUTPUT_ENABLE
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#define BOARD_GCLK5_FREQUENCY (BOARD_OSC8M_FREQUENCY / BOARD_GCLK5_PRESCALER)
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/* Configure GCLK generator 6 */
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#undef BOARD_GCLK6_ENABLE
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#undef BOARD_GCLK6_RUN_IN_STANDBY
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#define BOARD_GCLK6_CLOCK_SOURCE GCLK_GENCTRL_SRC_OSC8M
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#define BOARD_GCLK6_PRESCALER 1
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#undef BOARD_GCLK6_OUTPUT_ENABLE
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#define BOARD_GCLK6_FREQUENCY (BOARD_OSC8M_FREQUENCY / BOARD_GCLK6_PRESCALER)
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/* Configure GCLK generator 7 */
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#undef BOARD_GCLK7_ENABLE
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#undef BOARD_GCLK7_RUN_IN_STANDBY
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#define BOARD_GCLK7_CLOCK_SOURCE GCLK_GENCTRL_SRC_OSC8M
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#define BOARD_GCLK7_PRESCALER 1
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#undef BOARD_GCLK7_OUTPUT_ENABLE
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#define BOARD_GCLK7_FREQUENCY (BOARD_OSC8M_FREQUENCY / BOARD_GCLK7_PRESCALER)
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/* The source of the main clock is always GCLK_MAIN.
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* Also called GCLKGEN[0], this is the clock feeding the Power Manager.
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* The Power Manager, in turn, generates main clock which is divided
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* down to produce the CPU, AHB, and APB clocks.
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*
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* The main clock is initially OSC8M divided by 8.
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*/
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#define BOARD_GCLK_MAIN_FREQUENCY BOARD_GCLK0_FREQUENCY
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/* Main clock dividers
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*
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* BOARD_CPU_DIVIDER - See PM_CPUSEL_CPUDIV_* definitions
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* BOARD_CPU_FREQUENCY - In Hz
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* BOARD_CPU_FAILDECT - Boolean (defined / not defined)
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* BOARD_APBA_DIVIDER - See M_APBASEL_APBADIV_* definitions
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* BOARD_APBA_FREQUENCY - In Hz
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* BOARD_APBB_DIVIDER - See M_APBBSEL_APBBDIV_* definitions
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* BOARD_APBB_FREQUENCY - In Hz
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* BOARD_APBC_DIVIDER - See M_APBCSEL_APBCDIV_* definitions
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* BOARD_APBC_FREQUENCY - In Hz
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*/
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#define BOARD_CPU_FAILDECT 1
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#define BOARD_CPU_DIVIDER PM_CPUSEL_CPUDIV_1
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#define BOARD_APBA_DIVIDER PM_APBASEL_APBADIV_1
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#define BOARD_APBB_DIVIDER PM_APBBSEL_APBBDIV_1
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#define BOARD_APBC_DIVIDER PM_APBCSEL_APBCDIV_1
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/* Resulting frequencies */
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#define BOARD_MCK_FREQUENCY (BOARD_GCLK_MAIN_FREQUENCY)
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#define BOARD_CPU_FREQUENCY (BOARD_MCK_FREQUENCY)
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#define BOARD_PBA_FREQUENCY (BOARD_MCK_FREQUENCY)
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#define BOARD_PBB_FREQUENCY (BOARD_MCK_FREQUENCY)
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#define BOARD_PBC_FREQUENCY (BOARD_MCK_FREQUENCY)
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#define BOARD_PBD_FREQUENCY (BOARD_MCK_FREQUENCY)
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/* FLASH wait states
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*
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* Vdd Range Wait states Maximum Operating Frequency
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* ------------- -------------- ---------------------------
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* 1.62V to 2.7V 0 14 MHz
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* 1 28 MHz
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* 2 42 MHz
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* 3 48 MHz
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* 2.7V to 3.63V 0 24 MHz
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* 1 48 MHz
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*/
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#if 0 /* REVISIT -- should not be necessary */
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# define BOARD_FLASH_WAITSTATES 1
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#else
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# define BOARD_FLASH_WAITSTATES 2
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#endif
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/* SERCOM definitions *******************************************************/
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/* This is the source clock generator for the GCLK_SERCOM_SLOW clock that
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* is common to all SERCOM modules.
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*/
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#define BOARD_SERCOM05_SLOW_GCLKGEN 0
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/* SERCOM0 SPI is available on EXT1
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*
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* PIN PORT SERCOM FUNCTION
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* --- ------------------ -----------
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* 15 PA5 SERCOM0 PAD1 SPI SS
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* 16 PA6 SERCOM0 PAD2 SPI MOSI
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* 17 PA4 SERCOM0 PAD0 SPI MISO
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* 18 PA7 SERCOM0 PAD3 SPI SCK
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*/
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#define BOARD_SERCOM0_GCLKGEN 0
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#define BOARD_SERCOM0_SLOW_GCLKGEN BOARD_SERCOM05_SLOW_GCLKGEN
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#define BOARD_SERCOM0_MUXCONFIG (SPI_CTRLA_DOPO_DOPAD231 | SPI_CTRLA_DIPAD0)
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#define BOARD_SERCOM0_PINMAP_PAD0 PORT_SERCOM0_PAD0_2 /* SPI_MISO */
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#define BOARD_SERCOM0_PINMAP_PAD1 0 /* microSD_SS */
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#define BOARD_SERCOM0_PINMAP_PAD2 PORT_SERCOM0_PAD2_2 /* SPI_MOSI */
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#define BOARD_SERCOM0_PINMAP_PAD3 PORT_SERCOM0_PAD3_2 /* SPI_SCK */
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#define BOARD_SERCOM0_FREQUENCY BOARD_GCLK0_FREQUENCY
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/* SERCOM1 SPI is available on EXT2
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*
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* PIN PORT SERCOM FUNCTION
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* --- ------------------ -----------
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* 15 PA17 SERCOM1 PAD1 SPI SS
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* 16 PA18 SERCOM1 PAD2 SPI MOSI
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* 17 PA16 SERCOM1 PAD0 SPI MISO
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* 18 PA19 SERCOM1 PAD3 SPI SCK
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*/
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#define BOARD_SERCOM1_GCLKGEN 0
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#define BOARD_SERCOM1_SLOW_GCLKGEN BOARD_SERCOM05_SLOW_GCLKGEN
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#define BOARD_SERCOM1_MUXCONFIG (SPI_CTRLA_DOPO_DOPAD231 | SPI_CTRLA_DIPAD0)
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#define BOARD_SERCOM1_PINMAP_PAD0 PORT_SERCOM1_PAD0_1 /* SPI_MISO */
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#define BOARD_SERCOM1_PINMAP_PAD1 0 /* microSD_SS */
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#define BOARD_SERCOM1_PINMAP_PAD2 PORT_SERCOM1_PAD2_1 /* SPI_MOSI */
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#define BOARD_SERCOM1_PINMAP_PAD3 PORT_SERCOM1_PAD3_1 /* SPI_SCK */
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#define BOARD_SERCOM1_FREQUENCY BOARD_GCLK0_FREQUENCY
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/* The SAMD20 Xplained Pro contains an Embedded Debugger (EDBG) that can be
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* used to program and debug the ATSAMD20J18A using Serial Wire Debug (SWD).
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* The Embedded debugger also include a Virtual COM port interface over
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* SERCOM3. Virtual COM port connections:
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*
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* PA24 SERCOM3 / USART TXD
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* PA25 SERCOM3 / USART RXD
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*/
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#define BOARD_SERCOM3_GCLKGEN 0
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#define BOARD_SERCOM3_SLOW_GCLKGEN BOARD_SERCOM05_SLOW_GCLKGEN
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#define BOARD_SERCOM3_MUXCONFIG (USART_CTRLA_RXPAD3 | USART_CTRLA_TXPAD2)
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#define BOARD_SERCOM3_PINMAP_PAD0 0
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#define BOARD_SERCOM3_PINMAP_PAD1 0
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#define BOARD_SERCOM3_PINMAP_PAD2 PORT_SERCOM3_PAD2_1 /* USART TX */
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#define BOARD_SERCOM3_PINMAP_PAD3 PORT_SERCOM3_PAD3_1 /* USART RX */
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#define BOARD_SERCOM3_FREQUENCY BOARD_GCLK0_FREQUENCY
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/* The SERCOM4 USART is available on connectors EXT1, EXT2, and EXT3
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*
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* PIN EXT1 EXT2 EXT3 GPIO Function
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* ---- ---- ---- ---- ------------------
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* 13 PB09 PB13 PB11 SERCOM4 / USART RX
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* 14 PB08 PB12 PB12 SERCOM4 / USART TX
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* 19 GND GND GND N/A
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* 20 VCC VCC VCC N/A
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*
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* If you have a TTL to RS-232 converter then this is the most convenient
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* serial console to use (because you don't lose the console device each time
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* you lose the USB connection). It is the default in all of the SAMD20
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|
* configurations.
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|
*/
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|
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#define BOARD_SERCOM4_GCLKGEN 0
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#define BOARD_SERCOM4_SLOW_GCLKGEN BOARD_SERCOM05_SLOW_GCLKGEN
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#if defined(CONFIG_SAMD20_XPLAINED_USART4_EXT1)
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# define BOARD_SERCOM4_MUXCONFIG (USART_CTRLA_RXPAD1 | USART_CTRLA_TXPAD0)
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# define BOARD_SERCOM4_PINMAP_PAD0 PORT_SERCOM4_PAD0_3 /* USART TX */
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# define BOARD_SERCOM4_PINMAP_PAD1 PORT_SERCOM4_PAD1_3 /* USART RX */
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# define BOARD_SERCOM4_PINMAP_PAD2 0
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# define BOARD_SERCOM4_PINMAP_PAD3 0
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#elif defined(CONFIG_SAMD20_XPLAINED_USART4_EXT2)
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# define BOARD_SERCOM4_MUXCONFIG (USART_CTRLA_RXPAD1 | USART_CTRLA_TXPAD0)
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# define BOARD_SERCOM4_PINMAP_PAD0 PORT_SERCOM4_PAD0_1 /* USART TX */
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# define BOARD_SERCOM4_PINMAP_PAD1 PORT_SERCOM4_PAD1_1 /* USART RX */
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# define BOARD_SERCOM4_PINMAP_PAD2 0
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|
# define BOARD_SERCOM4_PINMAP_PAD3 0
|
|
#else /* if defined(CONFIG_SAMD20_XPLAINED_USART4_EXT3) */
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|
# define BOARD_SERCOM4_MUXCONFIG (USART_CTRLA_RXPAD3 | USART_CTRLA_TXPAD2)
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|
# define BOARD_SERCOM4_PINMAP_PAD0 0
|
|
# define BOARD_SERCOM4_PINMAP_PAD1 0
|
|
# define BOARD_SERCOM4_PINMAP_PAD2 PORT_SERCOM4_PAD2_3 /* USART TX */
|
|
# define BOARD_SERCOM4_PINMAP_PAD3 PORT_SERCOM4_PAD3_3 /* USART RX */
|
|
#endif
|
|
|
|
#define BOARD_SERCOM4_FREQUENCY BOARD_GCLK0_FREQUENCY
|
|
|
|
/* SERCOM5 SPI is available on EXT3
|
|
*
|
|
* PIN PORT SERCOM FUNCTION
|
|
* --- ------------------ -----------
|
|
* 15 PB17 SERCOM5 PAD1 SPI SS
|
|
* 16 PB22 SERCOM5 PAD2 SPI MOSI
|
|
* 17 PB16 SERCOM5 PAD0 SPI MISO
|
|
* 18 PB23 SERCOM5 PAD3 SPI SCK
|
|
*/
|
|
|
|
#define BOARD_SERCOM5_GCLKGEN 0
|
|
#define BOARD_SERCOM5_SLOW_GCLKGEN BOARD_SERCOM05_SLOW_GCLKGEN
|
|
#define BOARD_SERCOM5_MUXCONFIG (SPI_CTRLA_DOPO_DOPAD231 | SPI_CTRLA_DIPAD0)
|
|
#define BOARD_SERCOM5_PINMAP_PAD0 PORT_SERCOM5_PAD0_1 /* SPI_MISO */
|
|
#define BOARD_SERCOM5_PINMAP_PAD1 0 /* microSD_SS */
|
|
#define BOARD_SERCOM5_PINMAP_PAD2 PORT_SERCOM5_PAD2_4 /* SPI_MOSI */
|
|
#define BOARD_SERCOM5_PINMAP_PAD3 PORT_SERCOM5_PAD3_4 /* SPI_SCK */
|
|
|
|
#define BOARD_SERCOM5_FREQUENCY BOARD_GCLK0_FREQUENCY
|
|
|
|
/* LED definitions **********************************************************/
|
|
|
|
/* There are three LEDs on board the SAMD20 Xplained Pro board: The EDBG
|
|
* controls two of the LEDs, a power LED and a status LED. There is only
|
|
* one user controllable LED, a yellow LED labelled STATUS near the SAMD20
|
|
* USB connector.
|
|
*
|
|
* This LED is controlled by PC07 and the LED can be activated by driving
|
|
* the PA14 to GND.
|
|
*/
|
|
|
|
/* LED index values for use with board_userled() */
|
|
|
|
#define BOARD_STATUS_LED 0
|
|
#define BOARD_NLEDS 1
|
|
|
|
/* LED bits for use with board_userled_all() */
|
|
|
|
#define BOARD_STATUS LED_BIT (1 << BOARD_STATUS_LED)
|
|
|
|
/* When CONFIG_ARCH_LEDS is defined in the NuttX configuration, NuttX will
|
|
* control the LED as defined below. Thus if the LED is statically on,
|
|
* NuttX has successfully booted and is, apparently, running normally.
|
|
* If the LED is flashing at approximately 2Hz,
|
|
* then a fatal error has been detected and the system has halted.
|
|
*/
|
|
|
|
#define LED_STARTED 0 /* STATUS LED=OFF */
|
|
#define LED_HEAPALLOCATE 0 /* STATUS LED=OFF */
|
|
#define LED_IRQSENABLED 0 /* STATUS LED=OFF */
|
|
#define LED_STACKCREATED 1 /* STATUS LED=ON */
|
|
#define LED_INIRQ 2 /* STATUS LED=no change */
|
|
#define LED_SIGNAL 2 /* STATUS LED=no change */
|
|
#define LED_ASSERTION 2 /* STATUS LED=no change */
|
|
#define LED_PANIC 3 /* STATUS LED=flashing */
|
|
|
|
/* Button definitions *******************************************************/
|
|
|
|
/* Mechanical buttons:
|
|
*
|
|
* The SAMD20 Xplained Pro contains two mechanical buttons.
|
|
* One button is the RESET button connected to the SAMD20 reset line and
|
|
* the other is a generic user configurable button.
|
|
* When a button is pressed it will drive the I/O line to GND.
|
|
*
|
|
* PA15 SW0
|
|
*/
|
|
|
|
/* The SAMD20 Xplained Pro supports one button: */
|
|
|
|
#define BUTTON_SW0 0
|
|
#define NUM_BUTTONS 1
|
|
|
|
#define BUTTON_SW0_BIT (1 << BUTTON_SW0)
|
|
|
|
#endif /* __BOARDS_ARM_SAMD2L2_SAMD20_XPLAINED_INCLUDE_BOARD_H */
|