Tiago Medicci Serrano 0ddb64555a esp32s3/irq: Allow IRAM ISRs to run during SPI flash operation ... This commit provides an interface to register ISRs that run from IRAM and keeps track of the non-IRAM interrupts. It enables, for instance, to avoid disabling all the interrupts during a SPI flash operation: IRAM-enabled ISRs are, then, able to run during these operations.		2023-10-05 11:25:43 +08:00
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esp32	Fix nuttx coding style	2023-07-14 01:16:06 +08:00
esp32s2	xtensa/esp32s2: Add support to TWAI/CANBus controller	2023-09-28 09:35:08 +08:00
esp32s3	esp32s3/irq: Allow IRAM ISRs to run during SPI flash operation	2023-10-05 11:25:43 +08:00
lx6
lx7
xtensa	Indent the define statement by two spaces	2023-05-21 09:52:08 -03:00
.gitignore
arch.h	mempool:Add mail_info support for multiple pools	2023-06-08 23:56:40 +08:00
elf.h
inttypes.h
irq.h	xtensa: Define COMMON_CTX_REGS for chips without FPU (e.g. ESP32-S2)	2022-10-27 23:28:47 +08:00
limits.h	arch: Define WCHAR_[MIN|MAX] in arch/include/limits.h	2022-06-03 22:25:49 +03:00
loadstore.h
setjmp.h
simcall.h
spinlock.h
stdarg.h
syscall.h	xtensa: Add missing input operand on sys_call6 inline ASM	2022-05-18 15:46:57 +02:00
types.h