Huang Qi
d0210c1174
riscv_tcbinfo: Fix register ordering for PC
...
X0 is always 0 but still should be transfered to the client, but it don't existed in thread context, use any other register for it, and its value will be omitted by gdb client.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-07-08 21:13:25 +08:00
..
2024-06-14 19:50:00 +08:00
2024-07-05 13:17:02 +08:00
2024-05-11 17:57:59 +02:00
2024-06-28 02:31:40 +08:00
2024-07-08 21:13:25 +08:00
2024-06-28 17:52:56 +08:00
2024-06-25 18:40:27 -03:00
2024-07-04 18:24:50 -03:00
2024-07-04 18:24:50 -03:00
2024-06-14 19:50:00 +08:00
2024-06-14 19:50:00 +08:00
2024-06-14 19:50:00 +08:00
2024-05-11 17:57:59 +02:00
2024-06-18 10:50:49 +08:00
2024-06-19 15:32:19 +08:00
2024-05-31 10:21:44 +08:00
2024-06-18 10:50:49 +08:00
2024-06-28 21:30:53 +08:00
2023-11-21 04:04:47 -08:00
2024-06-14 19:52:00 +08:00
2024-06-14 19:50:00 +08:00
2024-06-18 00:13:35 +08:00
2020-05-23 18:00:40 +01:00
2024-03-15 16:21:23 +08:00
2024-04-25 09:48:59 -03:00