f643edbe41
This patch includes bare minimum support for nucleo-wl55jc board. It compiles and nsh shell is working properly on virtual com port over USB. 3 onboard leds with userled driver are working. Signed-off-by: Michał Łyszczek <michal.lyszczek@bofc.pl>
222 lines
8.0 KiB
C
222 lines
8.0 KiB
C
/****************************************************************************
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* boards/arm/stm32wl5/nucleo-wl55jc/include/board.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __BOARDS_ARM_STM32WL5_NUCLEO_WL55JC_INCLUDE_BOARD_H
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#define __BOARDS_ARM_STM32WL5_NUCLEO_WL55JC_INCLUDE_BOARD_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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#endif
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/* Clocking *****************************************************************/
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/* nucleo-wl55jc has installed 32Mhz HSE oscillator */
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#define STM32WL5_XTAL_FREQ 32000000ul
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/* Use the HSE */
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#define STM32WL5_BOARD_USEHSE 1
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/* HSE source is a TCXO crystal which needs to be first powered on */
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#define STM32WL5_BOARD_USETCXO
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/* Prescaler common to all PLL inputs */
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#define STM32WL5_PLLCFG_PLLM RCC_PLLCFG_PLLM(2) /* 32MHz / 2 = 16MHz */
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/* 'main' PLL config; we use this to generate our system clock */
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/* disable unused pll clocks */
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#define STM32WL5_PLLCFG_PLLP 0
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#undef STM32WL5_PLLCFG_PLLP_ENABLED
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#define STM32WL5_PLLCFG_PLLQ 0
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#undef STM32WL5_PLLCFG_PLLQ_ENABLED
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/* further multiplicate source for system clock */
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#define STM32WL5_PLLCFG_PLLN RCC_PLLCFG_PLLN(6) /* 16MHz * 6 = 96MHz */
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#define STM32WL5_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) /* 96MHz / 2 = 48MHz */
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#define STM32WL5_PLLCFG_PLLR_ENABLED
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/* Resulting system clock is 48MHz */
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#define STM32WL5_SYSCLK_FREQUENCY 48000000ul
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/* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */
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#define STM32WL5_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
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#define STM32WL5_HCLK_FREQUENCY STM32WL5_SYSCLK_FREQUENCY
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/* Configure the HCLK3 divisor (for flash and sram2) */
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#define STM32WL5_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK3 = SYSCLK / 1 */
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#define STM32WL5_HCLK3_FREQUENCY STM32WL5_SYSCLK_FREQUENCY
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/* Configure the APB1 prescaler */
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#define STM32WL5_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */
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#define STM32WL5_PCLK1_FREQUENCY (STM32WL5_HCLK_FREQUENCY / 1)
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/* The timer clock frequencies are automatically defined by hardware.
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* If the APB prescaler equals 1, the timer clock frequencies are set to the
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* same frequency as that of the APB domain. Otherwise they are set to twice.
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*/
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#define STM32WL5_APB1_TIM2_CLKIN (STM32WL5_PCLK1_FREQUENCY)
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/* Configure the APB2 prescaler */
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#define STM32WL5_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */
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#define STM32WL5_PCLK2_FREQUENCY (STM32WL5_HCLK_FREQUENCY / 1)
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/* The timer clock frequencies are automatically defined by hardware.
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* If the APB prescaler equals 1, the timer clock frequencies are set to the
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* same frequency as that of the APB domain. Otherwise they are set to twice.
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*/
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#define STM32WL5_APB2_TIM1_CLKIN STM32WL5_PCLK2_FREQUENCY
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#define STM32WL5_APB2_TIM16_CLKIN STM32WL5_PCLK2_FREQUENCY
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#define STM32WL5_APB2_TIM17_CLKIN STM32WL5_PCLK2_FREQUENCY
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/* The timer clock frequencies are automatically defined by hardware. If the
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* APB prescaler equals 1, the timer clock frequencies are set to the same
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* frequency as that of the APB domain. Otherwise they are set to twice.
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* Note: TIM1,15,16 are on APB2, others on APB1
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*/
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#define BOARD_TIM1_FREQUENCY STM32WL5_HCLK_FREQUENCY
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#define BOARD_TIM2_FREQUENCY STM32WL5_HCLK_FREQUENCY
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#define BOARD_TIM16_FREQUENCY STM32WL5_HCLK_FREQUENCY
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#define BOARD_TIM17_FREQUENCY STM32WL5_HCLK_FREQUENCY
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#define BOARD_LPTIM1_FREQUENCY STM32WL5_HCLK_FREQUENCY
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#define BOARD_LPTIM2_FREQUENCY STM32WL5_HCLK_FREQUENCY
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#define BOARD_LPTIM3_FREQUENCY STM32WL5_HCLK_FREQUENCY
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Alternate function pin selections ****************************************/
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/* USART1:
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* RXD: PB7 (D0 on arduino pinout)
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* TXD: PB6 (D1 on arduino pinout)
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*/
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#define GPIO_USART1_RX GPIO_USART1_RX_2 /* PB7 */
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#define GPIO_USART1_TX GPIO_USART1_TX_2 /* PB6 */
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/* LPUART1
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* Connected to virtual com port
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*/
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#define GPIO_LPUART1_RX GPIO_LPUART1_RX_1 /* PA3 */
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#define GPIO_LPUART1_TX GPIO_LPUART1_TX_1 /* PA2 */
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/* LEDs
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*
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* The Nucleo wl55jc board provides 3 user leds
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* PB15 - blue LED
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* PB11 - red LED
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* PB9 - green LED
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*
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* - When the I/O is HIGH value, the LED is on.
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* - When the I/O is LOW, the LED is off.
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*/
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/* LED index values for use with board_userled() */
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#define BOARD_LED_BLUE 0
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#define BOARD_LED_GREEN 1
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#define BOARD_LED_RED 2
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#define BOARD_NLEDS 3
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/* LED bits for use with board_userled_all() */
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#define BOARD_LED_BLUE_BIT (1 << BOARD_LED_BLUE)
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#define BOARD_LED_GREEN_BIT (1 << BOARD_LED_GREEN)
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#define BOARD_LED_RED_BIT (1 << BOARD_LED_RED)
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/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is
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* defined. In that case, the usage by the board port is defined in
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* include/board.h and src/stm32_autoleds.c. The LEDs are used to encode
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* OS-related events as follows:
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*
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* SYMBOL Val Meaning LED state
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* BLUE GREEN RED
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* ----------------- --- ----------------------- ---- ----- ----
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*/
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#define LED_STARTED 1 /* NuttX has been started ON OFF OFF */
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#define LED_HEAPALLOCATE 2 /* Heap has been allocated OFF ON OFF */
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#define LED_IRQSENABLED 3 /* Interrupts enabled ON ON OFF */
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#define LED_STACKCREATED 4 /* Idle stack created OFF OFF ON */
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#define LED_INIRQ 5 /* In an interrupt GLOW N/C N/C */
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#define LED_SIGNAL 6 /* In a signal handler GLOW N/C N/C */
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#define LED_ASSERTION 7 /* An assertion failed GLOW N/C N/C */
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#define LED_PANIC 8 /* The system has crashed ON ON ON */
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#undef LED_IDLE /* MCU is is sleep mode Not used */
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/****************************************************************************
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* Public Data
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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/****************************************************************************
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* Name: stm32wl5_board_initialize
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*
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* Description:
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* All STM32WL5 architectures must provide the following entry point.
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* This entry point is called early in the initialization -- after all
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* memory has been configured and mapped but before any devices have been
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* initialized.
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*
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****************************************************************************/
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void stm32wl5_board_initialize(void);
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#undef EXTERN
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#if defined(__cplusplus)
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __BOARDS_ARM_STM32WL5_NUCLEO_WL55JC_INCLUDE_BOARD_H */
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