1055 lines
32 KiB
C
1055 lines
32 KiB
C
/****************************************************************************
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* arch/arm/src/stm32/stm32f40xxx_dma.c
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*
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* Copyright (C) 2011-2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <semaphore.h>
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#include <debug.h>
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#include <errno.h>
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#include <nuttx/irq.h>
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#include <nuttx/arch.h>
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#include <arch/irq.h>
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#include "up_arch.h"
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#include "up_internal.h"
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#include "sched/sched.h"
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#include "chip.h"
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#include "stm32_dma.h"
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#include "stm32.h"
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/* This file supports only the STM32 F4 family (an probably the F2 family
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* as well?)
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*/
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#if defined(CONFIG_STM32_STM32F40XX)
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#define DMA1_NSTREAMS 8
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#if STM32_NDMA > 1
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# define DMA2_NSTREAMS 8
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# define DMA_NSTREAMS (DMA1_NSTREAMS+DMA2_NSTREAMS)
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#else
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# define DMA_NSTREAMS DMA1_NSTREAMS
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#endif
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#ifndef CONFIG_DMA_PRI
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# define CONFIG_DMA_PRI NVIC_SYSH_PRIORITY_DEFAULT
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#endif
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/* Convert the DMA stream base address to the DMA register block address */
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#define DMA_BASE(ch) (ch & 0xfffffc00)
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/****************************************************************************
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* Private Types
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****************************************************************************/
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/* This structure descibes one DMA channel */
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struct stm32_dma_s
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{
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uint8_t stream; /* DMA stream number (0-7) */
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uint8_t irq; /* DMA stream IRQ number */
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uint8_t shift; /* ISR/IFCR bit shift value */
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uint8_t channel; /* DMA channel number (0-7) */
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sem_t sem; /* Used to wait for DMA channel to become available */
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uint32_t base; /* DMA register channel base address */
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dma_callback_t callback; /* Callback invoked when the DMA completes */
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void *arg; /* Argument passed to callback function */
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};
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/* This array describes the state of each DMA */
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static struct stm32_dma_s g_dma[DMA_NSTREAMS] =
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{
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{
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.stream = 0,
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.irq = STM32_IRQ_DMA1S0,
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.shift = DMA_INT_STREAM0_SHIFT,
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.base = STM32_DMA1_BASE + STM32_DMA_OFFSET(0),
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},
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{
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.stream = 1,
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.irq = STM32_IRQ_DMA1S1,
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.shift = DMA_INT_STREAM1_SHIFT,
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.base = STM32_DMA1_BASE + STM32_DMA_OFFSET(1),
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},
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{
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.stream = 2,
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.irq = STM32_IRQ_DMA1S2,
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.shift = DMA_INT_STREAM2_SHIFT,
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.base = STM32_DMA1_BASE + STM32_DMA_OFFSET(2),
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},
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{
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.stream = 3,
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.irq = STM32_IRQ_DMA1S3,
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.shift = DMA_INT_STREAM3_SHIFT,
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.base = STM32_DMA1_BASE + STM32_DMA_OFFSET(3),
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},
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{
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.stream = 4,
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.irq = STM32_IRQ_DMA1S4,
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.shift = DMA_INT_STREAM4_SHIFT,
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.base = STM32_DMA1_BASE + STM32_DMA_OFFSET(4),
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},
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{
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.stream = 5,
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.irq = STM32_IRQ_DMA1S5,
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.shift = DMA_INT_STREAM5_SHIFT,
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.base = STM32_DMA1_BASE + STM32_DMA_OFFSET(5),
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},
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{
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.stream = 6,
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.irq = STM32_IRQ_DMA1S6,
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.shift = DMA_INT_STREAM6_SHIFT,
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.base = STM32_DMA1_BASE + STM32_DMA_OFFSET(6),
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},
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{
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.stream = 7,
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.irq = STM32_IRQ_DMA1S7,
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.shift = DMA_INT_STREAM7_SHIFT,
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.base = STM32_DMA1_BASE + STM32_DMA_OFFSET(7),
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},
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#if STM32_NDMA > 1
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{
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.stream = 0,
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.irq = STM32_IRQ_DMA2S0,
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.shift = DMA_INT_STREAM0_SHIFT,
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.base = STM32_DMA2_BASE + STM32_DMA_OFFSET(0),
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},
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{
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.stream = 1,
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.irq = STM32_IRQ_DMA2S1,
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.shift = DMA_INT_STREAM1_SHIFT,
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.base = STM32_DMA2_BASE + STM32_DMA_OFFSET(1),
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},
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{
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.stream = 2,
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.irq = STM32_IRQ_DMA2S2,
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.shift = DMA_INT_STREAM2_SHIFT,
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.base = STM32_DMA2_BASE + STM32_DMA_OFFSET(2),
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},
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{
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.stream = 3,
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.irq = STM32_IRQ_DMA2S3,
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.shift = DMA_INT_STREAM3_SHIFT,
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.base = STM32_DMA2_BASE + STM32_DMA_OFFSET(3),
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},
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{
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.stream = 4,
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.irq = STM32_IRQ_DMA2S4,
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.base = STM32_DMA2_BASE + STM32_DMA_OFFSET(4),
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},
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{
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.stream = 5,
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.irq = STM32_IRQ_DMA2S5,
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.shift = DMA_INT_STREAM5_SHIFT,
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.base = STM32_DMA2_BASE + STM32_DMA_OFFSET(5),
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},
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{
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.stream = 6,
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.irq = STM32_IRQ_DMA2S6,
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.shift = DMA_INT_STREAM6_SHIFT,
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.base = STM32_DMA2_BASE + STM32_DMA_OFFSET(6),
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},
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{
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.stream = 7,
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.irq = STM32_IRQ_DMA2S7,
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.shift = DMA_INT_STREAM7_SHIFT,
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.base = STM32_DMA2_BASE + STM32_DMA_OFFSET(7),
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},
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#endif
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};
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* DMA register access functions
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****************************************************************************/
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/* Get non-channel register from DMA1 or DMA2 */
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static inline uint32_t dmabase_getreg(struct stm32_dma_s *dmast, uint32_t offset)
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{
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return getreg32(DMA_BASE(dmast->base) + offset);
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}
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/* Write to non-channel register in DMA1 or DMA2 */
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static inline void dmabase_putreg(struct stm32_dma_s *dmast, uint32_t offset, uint32_t value)
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{
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putreg32(value, DMA_BASE(dmast->base) + offset);
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}
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/* Get channel register from DMA1 or DMA2 */
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static inline uint32_t dmast_getreg(struct stm32_dma_s *dmast, uint32_t offset)
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{
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return getreg32(dmast->base + offset);
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}
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/* Write to channel register in DMA1 or DMA2 */
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static inline void dmast_putreg(struct stm32_dma_s *dmast, uint32_t offset, uint32_t value)
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{
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putreg32(value, dmast->base + offset);
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}
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/************************************************************************************
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* Name: stm32_dmatake() and stm32_dmagive()
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*
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* Description:
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* Used to get exclusive access to a DMA channel.
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*
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************************************************************************************/
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static void stm32_dmatake(FAR struct stm32_dma_s *dmast)
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{
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/* Take the semaphore (perhaps waiting) */
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while (sem_wait(&dmast->sem) != 0)
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{
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/* The only case that an error should occur here is if the wait was awakened
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* by a signal.
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*/
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ASSERT(errno == EINTR);
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}
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}
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static inline void stm32_dmagive(FAR struct stm32_dma_s *dmast)
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{
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(void)sem_post(&dmast->sem);
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}
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/************************************************************************************
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* Name: stm32_dmastream
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*
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* Description:
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* Get the g_dma table entry associated with a DMA controller and a stream number
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*
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************************************************************************************/
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static inline FAR struct stm32_dma_s *stm32_dmastream(unsigned int stream,
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unsigned int controller)
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{
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int index;
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DEBUGASSERT(stream < DMA_NSTREAMS && controller < STM32_NDMA);
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/* Convert the controller + stream based on the fact that there are 8 streams
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* per controller.
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*/
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#if STM32_NDMA > 1
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index = controller << 3 | stream;
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#else
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index = stream;
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#endif
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/* Then return the stream structure associated with the stream index */
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return &g_dma[index];
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}
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/************************************************************************************
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* Name: stm32_dmamap
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*
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* Description:
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* Get the g_dma table entry associated with a bit-encoded DMA selection
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*
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************************************************************************************/
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static inline FAR struct stm32_dma_s *stm32_dmamap(unsigned long dmamap)
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{
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/* Extract the DMA controller number from the bit encoded value */
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unsigned int controller = STM32_DMA_CONTROLLER(dmamap);
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/* Extact the stream number from the bit encoded value */
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unsigned int stream = STM32_DMA_STREAM(dmamap);
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/* Return the table entry associated with the controller + stream */
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return stm32_dmastream(stream, controller);
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}
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/************************************************************************************
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* Name: stm32_dmastreamdisable
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*
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* Description:
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* Disable the DMA stream
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*
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************************************************************************************/
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static void stm32_dmastreamdisable(struct stm32_dma_s *dmast)
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{
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uint32_t regoffset;
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uint32_t regval;
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/* Disable all interrupts at the DMA controller */
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regval = dmast_getreg(dmast, STM32_DMA_SCR_OFFSET);
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regval &= ~DMA_SCR_ALLINTS;
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/* Disable the DMA stream */
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regval &= ~DMA_SCR_EN;
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dmast_putreg(dmast, STM32_DMA_SCR_OFFSET, regval);
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/* Clear pending stream interrupts by setting bits in the upper or lower IFCR
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* register
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*/
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if (dmast->stream < 4)
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{
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regoffset = STM32_DMA_LIFCR_OFFSET;
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}
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else
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{
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regoffset = STM32_DMA_HIFCR_OFFSET;
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}
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dmabase_putreg(dmast, regoffset, (DMA_STREAM_MASK << dmast->shift));
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}
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/************************************************************************************
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* Name: stm32_dmainterrupt
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*
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* Description:
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* DMA interrupt handler
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*
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************************************************************************************/
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static int stm32_dmainterrupt(int irq, void *context)
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{
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struct stm32_dma_s *dmast;
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uint32_t status;
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uint32_t regoffset = 0;
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unsigned int stream = 0;
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unsigned int controller = 0;
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/* Get the stream and the controller that generated the interrupt */
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if (irq >= STM32_IRQ_DMA1S0 && irq <= STM32_IRQ_DMA1S6)
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{
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stream = irq - STM32_IRQ_DMA1S0;
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controller = DMA1;
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}
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else if (irq == STM32_IRQ_DMA1S7)
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{
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stream = 7;
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controller = DMA1;
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}
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else
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#if STM32_NDMA > 1
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if (irq >= STM32_IRQ_DMA2S0 && irq <= STM32_IRQ_DMA2S4)
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{
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stream = irq - STM32_IRQ_DMA2S0;
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controller = DMA2;
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}
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else if (irq >= STM32_IRQ_DMA2S5 && irq <= STM32_IRQ_DMA2S7)
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{
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stream = irq - STM32_IRQ_DMA2S5 + 5;
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controller = DMA2;
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}
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else
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#endif
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{
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PANIC();
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}
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/* Get the stream structure from the stream and controller numbers */
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dmast = stm32_dmastream(stream, controller);
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/* Select the interrupt status register (either the LISR or HISR)
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* based on the stream number that caused the interrupt.
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*/
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if (stream < 4)
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{
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regoffset = STM32_DMA_LISR_OFFSET;
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}
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else
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{
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regoffset = STM32_DMA_HISR_OFFSET;
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}
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/* Get the interrupt status for this stream */
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status = (dmabase_getreg(dmast, regoffset) >> dmast->shift) & DMA_STREAM_MASK;
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/* Clear fetched stream interrupts by setting bits in the upper or lower IFCR
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* register
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*/
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if (stream < 4)
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{
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regoffset = STM32_DMA_LIFCR_OFFSET;
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}
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else
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{
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regoffset = STM32_DMA_HIFCR_OFFSET;
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}
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dmabase_putreg(dmast, regoffset, (status << dmast->shift));
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/* Invoke the callback */
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if (dmast->callback)
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{
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dmast->callback(dmast, status, dmast->arg);
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}
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return OK;
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: stm32_dmainitialize
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*
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* Description:
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* Initialize the DMA subsystem
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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void weak_function up_dmainitialize(void)
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{
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struct stm32_dma_s *dmast;
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int stream;
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/* Initialize each DMA stream */
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for (stream = 0; stream < DMA_NSTREAMS; stream++)
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{
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dmast = &g_dma[stream];
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sem_init(&dmast->sem, 0, 1);
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/* Attach DMA interrupt vectors */
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(void)irq_attach(dmast->irq, stm32_dmainterrupt);
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/* Disable the DMA stream */
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stm32_dmastreamdisable(dmast);
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/* Enable the IRQ at the NVIC (still disabled at the DMA controller) */
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up_enable_irq(dmast->irq);
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#ifdef CONFIG_ARCH_IRQPRIO
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/* Set the interrupt priority */
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up_prioritize_irq(dmast->irq, CONFIG_DMA_PRI);
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#endif
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}
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}
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|
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/****************************************************************************
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* Name: stm32_dmachannel
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*
|
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* Description:
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* Allocate a DMA channel. This function gives the caller mutually
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* exclusive access to the DMA channel specified by the 'dmamap' argument.
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* DMA channels are shared on the STM32: Devices sharing the same DMA
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* channel cannot do DMA concurrently! See the DMACHAN_* definitions in
|
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* stm32_dma.h.
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*
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* If the DMA channel is not available, then stm32_dmachannel() will wait
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* until the holder of the channel relinquishes the channel by calling
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* stm32_dmafree(). WARNING: If you have two devices sharing a DMA
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* channel and the code never releases the channel, the stm32_dmachannel
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* call for the other will hang forever in this function! Don't let your
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* design do that!
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*
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* Hmm.. I suppose this interface could be extended to make a non-blocking
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* version. Feel free to do that if that is what you need.
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*
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* Input parameter:
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* dmamap - Identifies the stream/channel resource. For the STM32 F4, this
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* is a bit-encoded value as provided by the DMAMAP_* definitions
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* in chip/stm32f40xxx_dma.h
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*
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* Returned Value:
|
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* Provided that 'dmamap' is valid, this function ALWAYS returns a non-NULL,
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* void* DMA channel handle. (If 'dmamap' is invalid, the function will
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* assert if debug is enabled or do something ignorant otherwise).
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*
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* Assumptions:
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* - The caller does not hold he DMA channel.
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* - The caller can wait for the DMA channel to be freed if it is no
|
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* available.
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*
|
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****************************************************************************/
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|
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DMA_HANDLE stm32_dmachannel(unsigned int dmamap)
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{
|
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FAR struct stm32_dma_s *dmast;
|
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|
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/* Get the stream index from the bit-encoded channel value */
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|
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dmast = stm32_dmamap(dmamap);
|
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DEBUGASSERT(dmast != NULL);
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|
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/* Get exclusive access to the DMA channel -- OR wait until the channel
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* is available if it is currently being used by another driver
|
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*/
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|
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stm32_dmatake(dmast);
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|
|
/* The caller now has exclusive use of the DMA channel. Assign the
|
|
* channel to the stream and return an opaque reference to the stream
|
|
* structure.
|
|
*/
|
|
|
|
dmast->channel = STM32_DMA_CHANNEL(dmamap);
|
|
return (DMA_HANDLE)dmast;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_dmafree
|
|
*
|
|
* Description:
|
|
* Release a DMA channel. If another thread is waiting for this DMA channel
|
|
* in a call to stm32_dmachannel, then this function will re-assign the
|
|
* DMA channel to that thread and wake it up. NOTE: The 'handle' used
|
|
* in this argument must NEVER be used again until stm32_dmachannel() is
|
|
* called again to re-gain access to the channel.
|
|
*
|
|
* Returned Value:
|
|
* None
|
|
*
|
|
* Assumptions:
|
|
* - The caller holds the DMA channel.
|
|
* - There is no DMA in progress
|
|
*
|
|
****************************************************************************/
|
|
|
|
void stm32_dmafree(DMA_HANDLE handle)
|
|
{
|
|
struct stm32_dma_s *dmast = (struct stm32_dma_s *)handle;
|
|
|
|
DEBUGASSERT(handle != NULL);
|
|
|
|
/* Release the channel */
|
|
|
|
stm32_dmagive(dmast);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_dmasetup
|
|
*
|
|
* Description:
|
|
* Configure DMA before using
|
|
*
|
|
****************************************************************************/
|
|
|
|
void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
|
|
size_t ntransfers, uint32_t scr)
|
|
{
|
|
struct stm32_dma_s *dmast = (struct stm32_dma_s *)handle;
|
|
uint32_t regoffset;
|
|
uint32_t regval;
|
|
|
|
dmadbg("paddr: %08x maddr: %08x ntransfers: %d scr: %08x\n",
|
|
paddr, maddr, ntransfers, scr);
|
|
|
|
#ifdef CONFIG_STM32_DMACAPABLE
|
|
DEBUGASSERT(stm32_dmacapable(maddr, ntransfers, scr));
|
|
#endif
|
|
|
|
/* "If the stream is enabled, disable it by resetting the EN bit in the
|
|
* DMA_SxCR register, then read this bit in order to confirm that there is no
|
|
* ongoing stream operation. Writing this bit to 0 is not immediately
|
|
* effective since it is actually written to 0 once all the current transfers
|
|
* have finished. When the EN bit is read as 0, this means that the stream is
|
|
* ready to be configured. It is therefore necessary to wait for the EN bit
|
|
* to be cleared before starting any stream configuration. ..."
|
|
*/
|
|
|
|
while ((dmast_getreg(dmast, STM32_DMA_SCR_OFFSET) & DMA_SCR_EN) != 0);
|
|
|
|
/* "... All the stream dedicated bits set in the status register (DMA_LISR
|
|
* and DMA_HISR) from the previous data block DMA transfer should be cleared
|
|
* before the stream can be re-enabled."
|
|
*
|
|
* Clear pending stream interrupts by setting bits in the upper or lower IFCR
|
|
* register
|
|
*/
|
|
|
|
if (dmast->stream < 4)
|
|
{
|
|
regoffset = STM32_DMA_LIFCR_OFFSET;
|
|
}
|
|
else
|
|
{
|
|
regoffset = STM32_DMA_HIFCR_OFFSET;
|
|
}
|
|
|
|
dmabase_putreg(dmast, regoffset, (DMA_STREAM_MASK << dmast->shift));
|
|
|
|
/* "Set the peripheral register address in the DMA_SPARx register. The data
|
|
* will be moved from/to this address to/from the memory after the
|
|
* peripheral event.
|
|
*/
|
|
|
|
dmast_putreg(dmast, STM32_DMA_SPAR_OFFSET, paddr);
|
|
|
|
/* "Set the memory address in the DMA_SM0ARx ... register. The data will be
|
|
* written to or read from this memory after the peripheral event."
|
|
*
|
|
* Note that in double-buffered mode it is explicitly assumed that the second
|
|
* buffer immediately follows the first.
|
|
*/
|
|
|
|
dmast_putreg(dmast, STM32_DMA_SM0AR_OFFSET, maddr);
|
|
if (scr & DMA_SCR_DBM)
|
|
{
|
|
dmast_putreg(dmast, STM32_DMA_SM1AR_OFFSET, maddr + ntransfers);
|
|
}
|
|
|
|
/* "Configure the total number of data items to be transferred in the
|
|
* DMA_SNDTRx register. After each peripheral event, this value will be
|
|
* decremented."
|
|
*
|
|
* "When the peripheral flow controller is used for a given stream, the value
|
|
* written into the DMA_SxNDTR has no effect on the DMA transfer. Actually,
|
|
* whatever the value written, it will be forced by hardware to 0xFFFF as soon
|
|
* as the stream is enabled..."
|
|
*/
|
|
|
|
dmast_putreg(dmast, STM32_DMA_SNDTR_OFFSET, ntransfers);
|
|
|
|
/* "Select the DMA channel (request) using CHSEL[2:0] in the DMA_SxCR register."
|
|
*
|
|
* "Configure the stream priority using the PL[1:0] bits in the DMA_SCRx"
|
|
* register."
|
|
*/
|
|
|
|
regval = dmast_getreg(dmast, STM32_DMA_SCR_OFFSET);
|
|
regval &= ~(DMA_SCR_PL_MASK | DMA_SCR_CHSEL_MASK);
|
|
regval |= scr & DMA_SCR_PL_MASK;
|
|
regval |= (uint32_t)dmast->channel << DMA_SCR_CHSEL_SHIFT;
|
|
dmast_putreg(dmast, STM32_DMA_SCR_OFFSET, regval);
|
|
|
|
/* "Configure the FIFO usage (enable or disable, threshold in transmission and
|
|
* reception)"
|
|
*
|
|
* "Caution is required when choosing the FIFO threshold (bits FTH[1:0] of the
|
|
* DMA_SxFCR register) and the size of the memory burst (MBURST[1:0] of the
|
|
* DMA_SxCR register): The content pointed by the FIFO threshold must exactly
|
|
* match to an integer number of memory burst transfers. If this is not in the
|
|
* case, a FIFO error (flag FEIFx of the DMA_HISR or DMA_LISR register) will be
|
|
* generated when the stream is enabled, then the stream will be automatically
|
|
* disabled."
|
|
*
|
|
* The FIFO is disabled in circular mode when transferring data from a
|
|
* peripheral to memory, as in this case it is usually desirable to know that
|
|
* every byte from the peripheral is transferred immediately to memory. It is
|
|
* not practical to flush the DMA FIFO, as this requires disabling the channel
|
|
* which triggers the transfer-complete interrupt.
|
|
*
|
|
* NOTE: The FEIFx error interrupt is not enabled because the FEIFx seems to
|
|
* be reported spuriously causing good transfers to be marked as failures.
|
|
*/
|
|
|
|
regval = dmast_getreg(dmast, STM32_DMA_SFCR_OFFSET);
|
|
regval &= ~(DMA_SFCR_FTH_MASK | DMA_SFCR_FS_MASK | DMA_SFCR_FEIE);
|
|
if (!((scr & (DMA_SCR_CIRC | DMA_SCR_DIR_MASK)) == (DMA_SCR_CIRC | DMA_SCR_DIR_P2M)))
|
|
{
|
|
regval |= (DMA_SFCR_FTH_FULL | DMA_SFCR_DMDIS);
|
|
}
|
|
dmast_putreg(dmast, STM32_DMA_SFCR_OFFSET, regval);
|
|
|
|
/* "Configure data transfer direction, circular mode, peripheral & memory
|
|
* incremented mode, peripheral & memory data size, and interrupt after
|
|
* half and/or full transfer in the DMA_CCRx register."
|
|
*
|
|
* Note: The CT bit is always reset.
|
|
*/
|
|
|
|
regval = dmast_getreg(dmast, STM32_DMA_SCR_OFFSET);
|
|
regval &= ~(DMA_SCR_PFCTRL | DMA_SCR_DIR_MASK | DMA_SCR_PINC | DMA_SCR_MINC |
|
|
DMA_SCR_PSIZE_MASK | DMA_SCR_MSIZE_MASK | DMA_SCR_PINCOS |
|
|
DMA_SCR_CIRC | DMA_SCR_DBM | DMA_SCR_CT |
|
|
DMA_SCR_PBURST_MASK | DMA_SCR_MBURST_MASK);
|
|
scr &= (DMA_SCR_PFCTRL | DMA_SCR_DIR_MASK | DMA_SCR_PINC | DMA_SCR_MINC |
|
|
DMA_SCR_PSIZE_MASK | DMA_SCR_MSIZE_MASK | DMA_SCR_PINCOS |
|
|
DMA_SCR_DBM | DMA_SCR_CIRC |
|
|
DMA_SCR_PBURST_MASK | DMA_SCR_MBURST_MASK);
|
|
regval |= scr;
|
|
dmast_putreg(dmast, STM32_DMA_SCR_OFFSET, regval);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_dmastart
|
|
*
|
|
* Description:
|
|
* Start the DMA transfer
|
|
*
|
|
* Assumptions:
|
|
* - DMA handle allocated by stm32_dmachannel()
|
|
* - No DMA in progress
|
|
*
|
|
****************************************************************************/
|
|
|
|
void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool half)
|
|
{
|
|
struct stm32_dma_s *dmast = (struct stm32_dma_s *)handle;
|
|
uint32_t scr;
|
|
|
|
DEBUGASSERT(handle != NULL);
|
|
|
|
/* Save the callback info. This will be invoked whent the DMA commpletes */
|
|
|
|
dmast->callback = callback;
|
|
dmast->arg = arg;
|
|
|
|
/* Activate the stream by setting the ENABLE bit in the DMA_SCRx register.
|
|
* As soon as the stream is enabled, it can serve any DMA request from the
|
|
* peripheral connected on the stream.
|
|
*/
|
|
|
|
scr = dmast_getreg(dmast, STM32_DMA_SCR_OFFSET);
|
|
scr |= DMA_SCR_EN;
|
|
|
|
/* In normal mode, interrupt at either half or full completion. In circular
|
|
* and double-buffered modes, always interrupt on buffer wrap, and optionally
|
|
* interrupt at the halfway point.
|
|
*/
|
|
|
|
if ((scr & (DMA_SCR_DBM | DMA_SCR_CIRC)) == 0)
|
|
{
|
|
/* Once half of the bytes are transferred, the half-transfer flag (HTIF) is
|
|
* set and an interrupt is generated if the Half-Transfer Interrupt Enable
|
|
* bit (HTIE) is set. At the end of the transfer, the Transfer Complete Flag
|
|
* (TCIF) is set and an interrupt is generated if the Transfer Complete
|
|
* Interrupt Enable bit (TCIE) is set.
|
|
*/
|
|
|
|
scr |= (half ? (DMA_SCR_HTIE | DMA_SCR_TEIE) : (DMA_SCR_TCIE | DMA_SCR_TEIE));
|
|
}
|
|
else
|
|
{
|
|
/* In non-stop modes, when the transfer completes it immediately resets
|
|
* and starts again. The transfer-complete interrupt is thus always
|
|
* enabled, and the half-complete interrupt can be used in circular
|
|
* mode to determine when the buffer is half-full, or in double-buffered
|
|
* mode to determine when one of the two buffers is full.
|
|
*/
|
|
|
|
scr |= (half ? DMA_SCR_HTIE : 0) | DMA_SCR_TCIE | DMA_SCR_TEIE;
|
|
}
|
|
|
|
dmast_putreg(dmast, STM32_DMA_SCR_OFFSET, scr);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_dmastop
|
|
*
|
|
* Description:
|
|
* Cancel the DMA. After stm32_dmastop() is called, the DMA channel is
|
|
* reset and stm32_dmasetup() must be called before stm32_dmastart() can be
|
|
* called again
|
|
*
|
|
* Assumptions:
|
|
* - DMA handle allocated by stm32_dmachannel()
|
|
*
|
|
****************************************************************************/
|
|
|
|
void stm32_dmastop(DMA_HANDLE handle)
|
|
{
|
|
struct stm32_dma_s *dmast = (struct stm32_dma_s *)handle;
|
|
stm32_dmastreamdisable(dmast);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_dmaresidual
|
|
*
|
|
* Description:
|
|
* Read the DMA bytes-remaining register.
|
|
*
|
|
* Assumptions:
|
|
* - DMA handle allocated by stm32_dmachannel()
|
|
*
|
|
****************************************************************************/
|
|
|
|
size_t stm32_dmaresidual(DMA_HANDLE handle)
|
|
{
|
|
struct stm32_dma_s *dmast = (struct stm32_dma_s *)handle;
|
|
uint32_t residual;
|
|
|
|
/* Fetch the count of bytes remaining to be transferred.
|
|
*
|
|
* If the FIFO is enabled, this count may be inaccurate. ST don't
|
|
* appear to document whether this counts the peripheral or the memory
|
|
* side of the channel, and they don't make the memory pointer
|
|
* available either.
|
|
*
|
|
* For reception in circular mode the FIFO is disabled in order that
|
|
* this value can be useful.
|
|
*/
|
|
|
|
residual = dmast_getreg(dmast, STM32_DMA_SNDTR_OFFSET);
|
|
|
|
return (size_t)residual;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_dmacapable
|
|
*
|
|
* Description:
|
|
* Check if the DMA controller can transfer data to/from given memory
|
|
* address. This depends on the internal connections in the ARM bus matrix
|
|
* of the processor. Note that this only applies to memory addresses, it
|
|
* will return false for any peripheral address.
|
|
*
|
|
* Returned value:
|
|
* True, if transfer is possible.
|
|
*
|
|
****************************************************************************/
|
|
|
|
#ifdef CONFIG_STM32_DMACAPABLE
|
|
bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr)
|
|
{
|
|
uint32_t transfer_size, burst_length;
|
|
uint32_t mend;
|
|
|
|
dmavdbg("stm32_dmacapable: 0x%08x/%u 0x%08x\n", maddr, count, ccr);
|
|
|
|
/* Verify that the address conforms to the memory transfer size.
|
|
* Transfers to/from memory performed by the DMA controller are
|
|
* required to be aligned to their size.
|
|
*
|
|
* See ST RM0090 rev4, section 9.3.11
|
|
*
|
|
* Compute mend inline to avoid a possible non-constant integer
|
|
* multiply.
|
|
*/
|
|
|
|
switch (ccr & DMA_SCR_MSIZE_MASK)
|
|
{
|
|
case DMA_SCR_MSIZE_8BITS:
|
|
transfer_size = 1;
|
|
mend = maddr + count - 1;
|
|
break;
|
|
|
|
case DMA_SCR_MSIZE_16BITS:
|
|
transfer_size = 2;
|
|
mend = maddr + (count << 1) - 1;
|
|
break;
|
|
|
|
case DMA_SCR_MSIZE_32BITS:
|
|
transfer_size = 4;
|
|
mend = maddr + (count << 2) - 1;
|
|
break;
|
|
|
|
default:
|
|
dmavdbg("stm32_dmacapable: bad transfer size in CCR\n");
|
|
return false;
|
|
}
|
|
|
|
if ((maddr & (transfer_size - 1)) != 0)
|
|
{
|
|
dmavdbg("stm32_dmacapable: transfer unaligned\n");
|
|
return false;
|
|
}
|
|
|
|
/* Verify that burst transfers do not cross a 1KiB boundary. */
|
|
|
|
if ((maddr / 1024) != (mend / 1024))
|
|
{
|
|
/* The transfer as a whole crosses a 1KiB boundary.
|
|
* Verify that no burst does by asserting that the address
|
|
* is aligned to the burst length.
|
|
*/
|
|
|
|
switch (ccr & DMA_SCR_MBURST_MASK)
|
|
{
|
|
case DMA_SCR_MBURST_SINGLE:
|
|
burst_length = transfer_size;
|
|
break;
|
|
|
|
case DMA_SCR_MBURST_INCR4:
|
|
burst_length = transfer_size << 2;
|
|
break;
|
|
|
|
case DMA_SCR_MBURST_INCR8:
|
|
burst_length = transfer_size << 3;
|
|
break;
|
|
|
|
case DMA_SCR_MBURST_INCR16:
|
|
burst_length = transfer_size << 4;
|
|
break;
|
|
|
|
default:
|
|
dmavdbg("stm32_dmacapable: bad burst size in CCR\n");
|
|
return false;
|
|
}
|
|
|
|
if ((maddr & (burst_length - 1)) != 0)
|
|
{
|
|
dmavdbg("stm32_dmacapable: burst crosses 1KiB\n");
|
|
return false;
|
|
}
|
|
}
|
|
|
|
/* Verify that the transfer is to a memory region that supports DMA. */
|
|
|
|
if ((maddr & STM32_REGION_MASK) != (mend & STM32_REGION_MASK))
|
|
{
|
|
dmavdbg("stm32_dmacapable: transfer crosses memory region\n");
|
|
return false;
|
|
}
|
|
|
|
switch (maddr & STM32_REGION_MASK)
|
|
{
|
|
case STM32_FSMC_BANK1:
|
|
case STM32_FSMC_BANK2:
|
|
case STM32_FSMC_BANK3:
|
|
case STM32_FSMC_BANK4:
|
|
case STM32_SRAM_BASE:
|
|
/* All RAM is supported */
|
|
|
|
break;
|
|
|
|
case STM32_CODE_BASE:
|
|
/* Everything except the CCM ram is supported */
|
|
|
|
if (maddr >= STM32_CCMRAM_BASE &&
|
|
(maddr - STM32_CCMRAM_BASE) < 65536)
|
|
{
|
|
dmavdbg("stm32_dmacapable: transfer targets CCMRAM\n");
|
|
return false;
|
|
}
|
|
break;
|
|
|
|
default:
|
|
/* Everything else is unsupported by DMA */
|
|
|
|
dmavdbg("stm32_dmacapable: transfer targets unknown/unsupported region\n");
|
|
return false;
|
|
}
|
|
|
|
dmavdbg("stm32_dmacapable: transfer OK\n");
|
|
return true;
|
|
}
|
|
#endif
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_dmasample
|
|
*
|
|
* Description:
|
|
* Sample DMA register contents
|
|
*
|
|
* Assumptions:
|
|
* - DMA handle allocated by stm32_dmachannel()
|
|
*
|
|
****************************************************************************/
|
|
|
|
#ifdef CONFIG_DEBUG_DMA
|
|
void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs)
|
|
{
|
|
struct stm32_dma_s *dmast = (struct stm32_dma_s *)handle;
|
|
irqstate_t flags;
|
|
|
|
flags = irqsave();
|
|
regs->lisr = dmabase_getreg(dmast, STM32_DMA_LISR_OFFSET);
|
|
regs->hisr = dmabase_getreg(dmast, STM32_DMA_HISR_OFFSET);
|
|
regs->scr = dmast_getreg(dmast, STM32_DMA_SCR_OFFSET);
|
|
regs->sndtr = dmast_getreg(dmast, STM32_DMA_SNDTR_OFFSET);
|
|
regs->spar = dmast_getreg(dmast, STM32_DMA_SPAR_OFFSET);
|
|
regs->sm0ar = dmast_getreg(dmast, STM32_DMA_SM0AR_OFFSET);
|
|
regs->sm1ar = dmast_getreg(dmast, STM32_DMA_SM1AR_OFFSET);
|
|
regs->sfcr = dmast_getreg(dmast, STM32_DMA_SFCR_OFFSET);
|
|
irqrestore(flags);
|
|
}
|
|
#endif
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_dmadump
|
|
*
|
|
* Description:
|
|
* Dump previously sampled DMA register contents
|
|
*
|
|
* Assumptions:
|
|
* - DMA handle allocated by stm32_dmachannel()
|
|
*
|
|
****************************************************************************/
|
|
|
|
#ifdef CONFIG_DEBUG_DMA
|
|
void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs,
|
|
const char *msg)
|
|
{
|
|
struct stm32_dma_s *dmast = (struct stm32_dma_s *)handle;
|
|
uint32_t dmabase = DMA_BASE(dmast->base);
|
|
|
|
dmadbg("DMA Registers: %s\n", msg);
|
|
dmadbg(" LISR[%08x]: %08x\n", dmabase + STM32_DMA_LISR_OFFSET, regs->lisr);
|
|
dmadbg(" HISR[%08x]: %08x\n", dmabase + STM32_DMA_HISR_OFFSET, regs->hisr);
|
|
dmadbg(" SCR[%08x]: %08x\n", dmast->base + STM32_DMA_SCR_OFFSET, regs->scr);
|
|
dmadbg(" SNDTR[%08x]: %08x\n", dmast->base + STM32_DMA_SNDTR_OFFSET, regs->sndtr);
|
|
dmadbg(" SPAR[%08x]: %08x\n", dmast->base + STM32_DMA_SPAR_OFFSET, regs->spar);
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dmadbg(" SM0AR[%08x]: %08x\n", dmast->base + STM32_DMA_SM0AR_OFFSET, regs->sm0ar);
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dmadbg(" SM1AR[%08x]: %08x\n", dmast->base + STM32_DMA_SM1AR_OFFSET, regs->sm1ar);
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dmadbg(" SFCR[%08x]: %08x\n", dmast->base + STM32_DMA_SFCR_OFFSET, regs->sfcr);
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}
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#endif
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#endif /* CONFIG_STM32_STM32F40XX */
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