2019-08-19 17:16:08 +02:00
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/****************************************************************************
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* boards/arm/stm32/olimex-stm32-p107/include/board.h
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2012-08-10 19:07:02 +02:00
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*
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2021-03-19 12:39:00 +01:00
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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2012-08-10 19:07:02 +02:00
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*
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2021-03-19 12:39:00 +01:00
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* http://www.apache.org/licenses/LICENSE-2.0
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2012-08-10 19:07:02 +02:00
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*
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2021-03-19 12:39:00 +01:00
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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2012-08-10 19:07:02 +02:00
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*
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2019-08-19 17:16:08 +02:00
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****************************************************************************/
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2012-08-10 19:07:02 +02:00
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2019-08-19 17:16:08 +02:00
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#ifndef __BOARDS_ARM_STM32_OLIMEX_STM32_P107_INCLUDE_BOARD_H
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2020-01-31 19:07:39 +01:00
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#define __BOARDS_ARM_STM32_OLIMEX_STM32_P107_INCLUDE_BOARD_H
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2012-09-25 21:17:52 +02:00
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2019-08-19 17:16:08 +02:00
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/****************************************************************************
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2012-08-10 19:07:02 +02:00
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* Included Files
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2019-08-19 17:16:08 +02:00
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****************************************************************************/
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2012-08-10 19:07:02 +02:00
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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#endif
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#include "stm32_rcc.h"
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#include "stm32_sdio.h"
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2013-02-09 16:03:49 +01:00
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#include "stm32.h"
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2012-08-10 19:07:02 +02:00
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2019-08-19 17:16:08 +02:00
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/****************************************************************************
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2012-08-10 19:07:02 +02:00
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* Pre-processor Definitions
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2019-08-19 17:16:08 +02:00
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****************************************************************************/
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2012-08-10 19:07:02 +02:00
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2021-03-19 12:39:00 +01:00
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/* Clocking *****************************************************************/
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2012-08-10 19:07:02 +02:00
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2012-10-04 17:07:06 +02:00
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/* HSI - 8 MHz RC factory-trimmed
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* LSI - 40 KHz RC (30-60KHz, uncalibrated)
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* HSE - On-board crystal frequency is 25MHz
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* LSE - 32.768 kHz
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*/
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2012-08-10 19:07:02 +02:00
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#define STM32_BOARD_XTAL 25000000ul
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2012-10-04 17:07:06 +02:00
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#define STM32_HSI_FREQUENCY 8000000ul
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#define STM32_LSI_FREQUENCY 40000
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#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
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#define STM32_LSE_FREQUENCY 32768
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2019-09-11 16:56:56 +02:00
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/* PLL output is 72MHz */
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2012-09-22 17:12:50 +02:00
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#define STM32_PLL_PREDIV2 RCC_CFGR2_PREDIV2d5 /* 25MHz / 5 => 5MHz */
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#define STM32_PLL_PLL2MUL RCC_CFGR2_PLL2MULx8 /* 5MHz * 8 => 40MHz */
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#define STM32_PLL_PREDIV1 RCC_CFGR2_PREDIV1d5 /* 40MHz / 5 => 8MHz */
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#define STM32_PLL_PLLMUL RCC_CFGR_PLLMUL_CLKx9 /* 8MHz * 9 => 72Mhz */
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#define STM32_PLL_FREQUENCY (72000000)
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2012-09-22 17:12:50 +02:00
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/* SYCLLK and HCLK are the PLL frequency */
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#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY
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#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY
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#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
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/* APB2 clock (PCLK2) is HCLK (72MHz) */
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#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK
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#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY
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#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) /* Timers 2-7, 12-14 */
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/* APB2 timers 1 and 8 will receive PCLK2. */
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#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY)
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/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */
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#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2
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#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2)
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2016-06-09 16:29:55 +02:00
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/* APB1 timers 2-7 will be twice PCLK1 */
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2012-08-10 19:07:02 +02:00
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#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY)
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2016-06-09 16:29:55 +02:00
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#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY)
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2012-08-10 19:07:02 +02:00
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2021-03-19 12:39:00 +01:00
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/* MCO output driven by PLL3. From above, we already have PLL3 input
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* frequency as:
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2012-09-22 21:19:56 +02:00
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*
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2014-04-14 00:22:22 +02:00
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* STM32_PLL_PREDIV2 = 5, 25MHz / 5 => 5MHz
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2012-09-22 21:19:56 +02:00
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*/
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2014-04-14 00:22:22 +02:00
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2012-09-22 17:12:50 +02:00
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#if defined(CONFIG_STM32_MII_MCO) || defined(CONFIG_STM32_RMII_MCO)
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2012-09-22 21:19:56 +02:00
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# define BOARD_CFGR_MCO_SOURCE RCC_CFGR_PLL3CLK /* Source: PLL3 */
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# define STM32_PLL_PLL3MUL RCC_CFGR2_PLL3MULx10 /* MCO 5MHz * 10 = 50MHz */
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2012-09-22 17:12:50 +02:00
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#endif
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2019-08-19 17:16:08 +02:00
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#endif /* __BOARDS_ARM_STM32_OLIMEX_STM32_P107_INCLUDE_BOARD_H */
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