2015-10-03 01:42:29 +02:00
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/****************************************************************************
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2020-03-07 12:36:39 +01:00
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* arch/arm/src/sama5/sam_lowputc.c
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2013-07-23 03:16:37 +02:00
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*
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2020-03-07 12:36:39 +01:00
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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2013-07-23 03:16:37 +02:00
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*
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2020-03-07 12:36:39 +01:00
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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2013-07-23 03:16:37 +02:00
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*
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2020-03-07 12:36:39 +01:00
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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2013-07-23 03:16:37 +02:00
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*
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2015-10-03 01:42:29 +02:00
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****************************************************************************/
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2013-07-23 03:16:37 +02:00
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2015-10-03 01:42:29 +02:00
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/****************************************************************************
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2013-07-23 03:16:37 +02:00
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* Included Files
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2015-10-03 01:42:29 +02:00
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****************************************************************************/
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2013-07-23 03:16:37 +02:00
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#include <nuttx/config.h>
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#include <stdint.h>
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2016-02-14 02:11:09 +01:00
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#include <nuttx/irq.h>
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2013-07-23 03:16:37 +02:00
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2020-05-01 03:20:29 +02:00
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#include "arm_internal.h"
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#include "arm_arch.h"
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2013-07-23 03:16:37 +02:00
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2013-08-06 18:20:17 +02:00
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#include "sam_pio.h"
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2013-07-23 03:16:37 +02:00
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#include "sam_periphclks.h"
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2015-09-11 20:00:30 +02:00
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#include "sam_config.h"
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2014-04-01 19:24:15 +02:00
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#include "sam_dbgu.h"
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2013-07-23 03:16:37 +02:00
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#include "sam_lowputc.h"
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2019-05-25 15:59:12 +02:00
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#include "hardware/sam_uart.h"
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#include "hardware/sam_flexcom.h"
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#include "hardware/sam_dbgu.h"
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#include "hardware/sam_pinmap.h"
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2013-07-23 03:16:37 +02:00
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2015-09-12 02:42:49 +02:00
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#include <arch/board/board.h>
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2015-10-03 01:42:29 +02:00
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/****************************************************************************
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2015-04-08 16:04:12 +02:00
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* Pre-processor Definitions
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2015-10-03 01:42:29 +02:00
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****************************************************************************/
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2013-07-23 03:16:37 +02:00
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2014-06-20 19:40:36 +02:00
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/* The UART/USART modules are driven by the peripheral clock (MCK or MCK2). */
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2013-07-23 03:16:37 +02:00
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2015-09-11 22:30:19 +02:00
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#ifdef SAMA5_HAVE_FLEXCOM_CONSOLE
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2015-09-12 02:42:49 +02:00
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# define SAM_USART_CLOCK BOARD_FLEXCOM_FREQUENCY /* Frequency of the FLEXCOM clock */
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# define SAM_MR_USCLKS FLEXUS_MR_USCLKS_MCK /* Source = Main clock */
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2015-09-11 22:30:19 +02:00
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#else
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2015-09-12 02:42:49 +02:00
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# define SAM_USART_CLOCK BOARD_USART_FREQUENCY /* Frequency of the USART clock */
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# define SAM_MR_USCLKS UART_MR_USCLKS_MCK /* Source = Main clock */
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2015-09-11 22:30:19 +02:00
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#endif
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2013-07-23 03:16:37 +02:00
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/* Select USART parameters for the selected console */
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2014-04-01 19:24:15 +02:00
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#if defined(CONFIG_SAMA5_DBGU_CONSOLE)
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# define SAM_CONSOLE_VBASE SAM_DBGU_VBASE
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# define SAM_CONSOLE_BITS 8
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# define SAM_CONSOLE_2STOP 0
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2015-09-08 21:26:51 +02:00
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# ifdef CONFIG_SAMA5_DBGU_NOCONFIG
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# undef SUPPRESS_CONSOLE_CONFIG
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# define SUPPRESS_CONSOLE_CONFIG 1
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# define SAM_CONSOLE_BAUD 115200
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# define SAM_CONSOLE_PARITY 0
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# else
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# define SAM_CONSOLE_BAUD CONFIG_SAMA5_DBGU_BAUD
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# define SAM_CONSOLE_PARITY CONFIG_SAMA5_DBGU_PARITY
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# endif
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2014-04-01 19:24:15 +02:00
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#elif defined(CONFIG_UART0_SERIAL_CONSOLE)
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2013-07-23 04:59:47 +02:00
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# define SAM_CONSOLE_VBASE SAM_UART0_VBASE
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2013-07-23 03:16:37 +02:00
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# define SAM_CONSOLE_BAUD CONFIG_UART0_BAUD
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# define SAM_CONSOLE_BITS CONFIG_UART0_BITS
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# define SAM_CONSOLE_PARITY CONFIG_UART0_PARITY
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# define SAM_CONSOLE_2STOP CONFIG_UART0_2STOP
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#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
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2013-07-23 04:59:47 +02:00
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# define SAM_CONSOLE_VBASE SAM_UART1_VBASE
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2013-07-23 03:16:37 +02:00
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# define SAM_CONSOLE_BAUD CONFIG_UART1_BAUD
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# define SAM_CONSOLE_BITS CONFIG_UART1_BITS
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# define SAM_CONSOLE_PARITY CONFIG_UART1_PARITY
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# define SAM_CONSOLE_2STOP CONFIG_UART1_2STOP
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2015-09-09 20:11:45 +02:00
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#elif defined(CONFIG_UART2_SERIAL_CONSOLE)
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# define SAM_CONSOLE_VBASE SAM_UART2_VBASE
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# define SAM_CONSOLE_BAUD CONFIG_UART2_BAUD
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# define SAM_CONSOLE_BITS CONFIG_UART2_BITS
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# define SAM_CONSOLE_PARITY CONFIG_UART2_PARITY
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# define SAM_CONSOLE_2STOP CONFIG_UART2_2STOP
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#elif defined(CONFIG_UART3_SERIAL_CONSOLE)
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# define SAM_CONSOLE_VBASE SAM_UART3_VBASE
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# define SAM_CONSOLE_BAUD CONFIG_UART3_BAUD
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# define SAM_CONSOLE_BITS CONFIG_UART3_BITS
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# define SAM_CONSOLE_PARITY CONFIG_UART3_PARITY
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# define SAM_CONSOLE_2STOP CONFIG_UART3_2STOP
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#elif defined(CONFIG_UART4_SERIAL_CONSOLE)
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# define SAM_CONSOLE_VBASE SAM_UART4_VBASE
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# define SAM_CONSOLE_BAUD CONFIG_UART4_BAUD
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# define SAM_CONSOLE_BITS CONFIG_UART4_BITS
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# define SAM_CONSOLE_PARITY CONFIG_UART4_PARITY
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# define SAM_CONSOLE_2STOP CONFIG_UART4_2STOP
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2013-07-23 03:16:37 +02:00
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#elif defined(CONFIG_USART0_SERIAL_CONSOLE)
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2015-09-11 22:30:19 +02:00
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# ifdef CONFIG_SAMA5_FLEXCOM0_USART
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2015-09-12 02:42:49 +02:00
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# define SAM_CONSOLE_VBASE SAM_FLEXCOM0_VBASE
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2015-09-11 22:30:19 +02:00
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# else
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2015-09-12 02:42:49 +02:00
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# define SAM_CONSOLE_VBASE SAM_USART0_VBASE
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2015-09-11 22:30:19 +02:00
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# endif
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2013-07-23 03:16:37 +02:00
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# define SAM_CONSOLE_BAUD CONFIG_USART0_BAUD
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# define SAM_CONSOLE_BITS CONFIG_USART0_BITS
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# define SAM_CONSOLE_PARITY CONFIG_USART0_PARITY
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# define SAM_CONSOLE_2STOP CONFIG_USART0_2STOP
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#elif defined(CONFIG_USART1_SERIAL_CONSOLE)
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2015-09-11 22:30:19 +02:00
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# ifdef CONFIG_SAMA5_FLEXCOM1_USART
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2015-09-12 02:42:49 +02:00
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# define SAM_CONSOLE_VBASE SAM_FLEXCOM1_VBASE
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2015-09-11 22:30:19 +02:00
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# else
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2015-09-12 02:42:49 +02:00
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# define SAM_CONSOLE_VBASE SAM_USART1_VBASE
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2015-09-11 22:30:19 +02:00
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# endif
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2013-07-23 03:16:37 +02:00
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# define SAM_CONSOLE_BAUD CONFIG_USART1_BAUD
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# define SAM_CONSOLE_BITS CONFIG_USART1_BITS
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# define SAM_CONSOLE_PARITY CONFIG_USART1_PARITY
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# define SAM_CONSOLE_2STOP CONFIG_USART1_2STOP
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#elif defined(CONFIG_USART2_SERIAL_CONSOLE)
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2015-09-11 22:30:19 +02:00
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# ifdef CONFIG_SAMA5_FLEXCOM2_USART
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2015-09-12 02:42:49 +02:00
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# define SAM_CONSOLE_VBASE SAM_FLEXCOM2_VBASE
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2015-09-11 22:30:19 +02:00
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# else
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2015-09-12 02:42:49 +02:00
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# define SAM_CONSOLE_VBASE SAM_USART2_VBASE
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2015-09-11 22:30:19 +02:00
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# endif
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2013-07-23 03:16:37 +02:00
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# define SAM_CONSOLE_BAUD CONFIG_USART2_BAUD
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# define SAM_CONSOLE_BITS CONFIG_USART2_BITS
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# define SAM_CONSOLE_PARITY CONFIG_USART2_PARITY
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# define SAM_CONSOLE_2STOP CONFIG_USART2_2STOP
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#elif defined(CONFIG_USART3_SERIAL_CONSOLE)
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2015-09-11 22:30:19 +02:00
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# ifdef CONFIG_SAMA5_FLEXCOM3_USART
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2015-09-12 02:42:49 +02:00
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# define SAM_CONSOLE_VBASE SAM_FLEXCOM3_VBASE
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2015-09-11 22:30:19 +02:00
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# else
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2015-09-12 02:42:49 +02:00
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# define SAM_CONSOLE_VBASE SAM_USART3_VBASE
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2015-09-11 22:30:19 +02:00
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# endif
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2013-07-23 03:16:37 +02:00
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# define SAM_CONSOLE_BAUD CONFIG_USART3_BAUD
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# define SAM_CONSOLE_BITS CONFIG_USART3_BITS
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# define SAM_CONSOLE_PARITY CONFIG_USART3_PARITY
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# define SAM_CONSOLE_2STOP CONFIG_USART3_2STOP
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2015-09-11 20:00:30 +02:00
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#elif defined(CONFIG_USART4_SERIAL_CONSOLE)
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2015-09-11 22:30:19 +02:00
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# ifdef CONFIG_SAMA5_FLEXCOM4_USART
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2015-09-12 02:42:49 +02:00
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# define SAM_CONSOLE_VBASE SAM_FLEXCOM4_VBASE
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2015-09-11 22:30:19 +02:00
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# else
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2015-09-12 02:42:49 +02:00
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# define SAM_CONSOLE_VBASE SAM_USART4_VBASE
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2015-09-11 22:30:19 +02:00
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# endif
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2015-09-11 20:00:30 +02:00
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# define SAM_CONSOLE_BAUD CONFIG_USART4_BAUD
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# define SAM_CONSOLE_BITS CONFIG_USART4_BITS
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# define SAM_CONSOLE_PARITY CONFIG_USART4_PARITY
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# define SAM_CONSOLE_2STOP CONFIG_USART4_2STOP
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2013-07-23 03:16:37 +02:00
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#else
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# error "No CONFIG_U[S]ARTn_SERIAL_CONSOLE Setting"
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#endif
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/* Select the settings for the mode register */
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2015-09-11 22:30:19 +02:00
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#if defined(SAMA5_HAVE_UART_CONSOLE)
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2015-09-11 01:15:52 +02:00
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# if SAM_CONSOLE_BITS == 8 && SAM_CONSOLE_PARITY == 0
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# elif SAM_CONSOLE_BITS == 7 && SAM_CONSOLE_PARITY != 0
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# else
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# error "Unsupported combination of bits and parity in UART console"
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# endif
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# if SAM_CONSOLE_2STOP != 0
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# error "Unsupported number of stop bits and parity for UART console"
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# endif
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#endif
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2013-07-23 03:16:37 +02:00
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#if SAM_CONSOLE_BITS == 5
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# define MR_CHRL_VALUE UART_MR_CHRL_5BITS /* 5 bits */
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#elif SAM_CONSOLE_BITS == 6
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2015-09-11 01:15:52 +02:00
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# define MR_CHRL_VALUE UART_MR_CHRL_6BITS /* 6 bits */
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2013-07-23 03:16:37 +02:00
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#elif SAM_CONSOLE_BITS == 7
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# define MR_CHRL_VALUE UART_MR_CHRL_7BITS /* 7 bits */
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#elif SAM_CONSOLE_BITS == 8
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# define MR_CHRL_VALUE UART_MR_CHRL_8BITS /* 8 bits */
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#elif SAM_CONSOLE_BITS == 9 && !defined(CONFIG_UART0_SERIAL_CONSOLE) && \
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!defined(CONFIG_UART1_SERIAL_CONSOLE)
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# define MR_CHRL_VALUE UART_MR_MODE9
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#else
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2013-07-27 19:28:31 +02:00
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# error "Invalid number of bits"
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2013-07-23 03:16:37 +02:00
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#endif
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#if SAM_CONSOLE_PARITY == 1
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# define MR_PAR_VALUE UART_MR_PAR_ODD
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#elif SAM_CONSOLE_PARITY == 2
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# define MR_PAR_VALUE UART_MR_PAR_EVEN
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#else
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# define MR_PAR_VALUE UART_MR_PAR_NONE
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#endif
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#if SAM_CONSOLE_2STOP != 0
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# define MR_NBSTOP_VALUE UART_MR_NBSTOP_2
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#else
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# define MR_NBSTOP_VALUE UART_MR_NBSTOP_1
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#endif
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2015-09-11 01:15:52 +02:00
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#if defined(ATSAMA5D2)
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# define MR_VALUE (MR_PAR_VALUE | UART_MR_PERIPHCLK | \
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UART_MR_CHMODE_NORMAL)
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#elif defined(ATSAMA5D3) ||defined(ATSAMA5D4)
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# define MR_VALUE (UART_MR_MODE_NORMAL | SAM_MR_USCLKS | \
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MR_CHRL_VALUE | MR_PAR_VALUE | MR_NBSTOP_VALUE | \
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UART_MR_CHMODE_NORMAL)
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#endif
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2013-07-23 03:16:37 +02:00
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2015-10-03 01:42:29 +02:00
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/****************************************************************************
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2013-07-23 03:16:37 +02:00
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* Public Functions
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2015-10-03 01:42:29 +02:00
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****************************************************************************/
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2013-07-23 03:16:37 +02:00
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2015-10-03 01:42:29 +02:00
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/****************************************************************************
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2020-05-01 16:50:23 +02:00
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* Name: arm_lowputc
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2013-07-23 03:16:37 +02:00
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*
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* Description:
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* Output one byte on the serial console
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*
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2015-10-03 01:42:29 +02:00
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****************************************************************************/
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2013-07-23 03:16:37 +02:00
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2020-05-01 16:50:23 +02:00
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void arm_lowputc(char ch)
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2013-07-23 03:16:37 +02:00
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{
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2015-09-11 22:30:19 +02:00
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#if defined(SAMA5_HAVE_UART_CONSOLE) || defined(SAMA5_HAVE_USART_CONSOLE)
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2014-03-25 21:34:07 +01:00
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irqstate_t flags;
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2013-07-23 03:16:37 +02:00
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2015-10-07 19:39:06 +02:00
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for (; ; )
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2014-03-25 21:34:07 +01:00
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{
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/* Wait for the transmitter to be available */
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2013-07-23 03:16:37 +02:00
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2014-03-25 23:11:33 +01:00
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while ((getreg32(SAM_CONSOLE_VBASE + SAM_UART_SR_OFFSET) &
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2014-03-25 21:34:07 +01:00
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UART_INT_TXEMPTY) == 0);
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2013-07-23 03:16:37 +02:00
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2014-03-25 21:34:07 +01:00
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/* Disable interrupts so that the test and the transmission are
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* atomic.
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*/
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|
2016-02-14 02:11:09 +01:00
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flags = enter_critical_section();
|
2014-03-25 21:34:07 +01:00
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if ((getreg32(SAM_CONSOLE_VBASE + SAM_UART_SR_OFFSET) &
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UART_INT_TXEMPTY) != 0)
|
|
|
|
{
|
|
|
|
/* Send the character */
|
|
|
|
|
|
|
|
putreg32((uint32_t)ch, SAM_CONSOLE_VBASE + SAM_UART_THR_OFFSET);
|
2016-02-14 02:11:09 +01:00
|
|
|
leave_critical_section(flags);
|
2014-03-25 21:34:07 +01:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2016-02-14 02:11:09 +01:00
|
|
|
leave_critical_section(flags);
|
2014-04-01 19:24:15 +02:00
|
|
|
}
|
2015-09-11 22:30:19 +02:00
|
|
|
|
|
|
|
#elif defined(SAMA5_HAVE_FLEXCOM_CONSOLE)
|
|
|
|
irqstate_t flags;
|
|
|
|
|
2015-10-07 19:39:06 +02:00
|
|
|
for (; ; )
|
2015-09-11 22:30:19 +02:00
|
|
|
{
|
|
|
|
/* Wait for the transmitter to be available */
|
|
|
|
|
|
|
|
while ((getreg32(SAM_CONSOLE_VBASE + SAM_FLEXUS_CSR_OFFSET) &
|
|
|
|
FLEXUS_INT_TXEMPTY) == 0);
|
|
|
|
|
|
|
|
/* Disable interrupts so that the test and the transmission are
|
|
|
|
* atomic.
|
|
|
|
*/
|
|
|
|
|
2016-02-14 02:11:09 +01:00
|
|
|
flags = enter_critical_section();
|
2015-09-11 22:30:19 +02:00
|
|
|
if ((getreg32(SAM_CONSOLE_VBASE + SAM_FLEXUS_CSR_OFFSET) &
|
|
|
|
FLEXUS_INT_TXEMPTY) != 0)
|
|
|
|
{
|
|
|
|
/* Send the character */
|
|
|
|
|
|
|
|
putreg32((uint32_t)ch, SAM_CONSOLE_VBASE + SAM_FLEXUS_THR_OFFSET);
|
2016-02-14 02:11:09 +01:00
|
|
|
leave_critical_section(flags);
|
2015-09-11 22:30:19 +02:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2016-02-14 02:11:09 +01:00
|
|
|
leave_critical_section(flags);
|
2015-09-11 22:30:19 +02:00
|
|
|
}
|
|
|
|
|
2014-04-01 19:24:15 +02:00
|
|
|
#elif defined(CONFIG_SAMA5_DBGU_CONSOLE)
|
|
|
|
irqstate_t flags;
|
|
|
|
|
2015-10-07 19:39:06 +02:00
|
|
|
for (; ; )
|
2014-04-01 19:24:15 +02:00
|
|
|
{
|
|
|
|
/* Wait for the transmitter to be available */
|
|
|
|
|
|
|
|
while ((getreg32(SAM_DBGU_SR) & DBGU_INT_TXEMPTY) == 0);
|
|
|
|
|
|
|
|
/* Disable interrupts so that the test and the transmission are
|
|
|
|
* atomic.
|
|
|
|
*/
|
|
|
|
|
2016-02-14 02:11:09 +01:00
|
|
|
flags = enter_critical_section();
|
2014-04-01 19:24:15 +02:00
|
|
|
if ((getreg32(SAM_DBGU_SR) & DBGU_INT_TXEMPTY) != 0)
|
|
|
|
{
|
|
|
|
/* Send the character */
|
|
|
|
|
|
|
|
putreg32((uint32_t)ch, SAM_DBGU_THR);
|
2016-02-14 02:11:09 +01:00
|
|
|
leave_critical_section(flags);
|
2014-04-01 19:24:15 +02:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2016-02-14 02:11:09 +01:00
|
|
|
leave_critical_section(flags);
|
2014-03-25 21:34:07 +01:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: up_putc
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Provide priority, low-level access to support OS debug writes
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
int up_putc(int ch)
|
|
|
|
{
|
2015-09-11 22:30:19 +02:00
|
|
|
#if defined(SAMA5_HAVE_UART_CONSOLE) || defined(SAMA5_HAVE_USART_CONSOLE) || \
|
|
|
|
defined(SAMA5_HAVE_FLEXCOM_CONSOLE) || defined(CONFIG_SAMA5_DBGU_CONSOLE)
|
2014-03-25 21:34:07 +01:00
|
|
|
/* Check for LF */
|
|
|
|
|
|
|
|
if (ch == '\n')
|
|
|
|
{
|
|
|
|
/* Add CR */
|
|
|
|
|
2020-05-01 16:50:23 +02:00
|
|
|
arm_lowputc('\r');
|
2014-03-25 21:34:07 +01:00
|
|
|
}
|
|
|
|
|
2020-05-01 16:50:23 +02:00
|
|
|
arm_lowputc(ch);
|
2015-09-11 20:00:30 +02:00
|
|
|
#endif
|
2014-03-25 21:34:07 +01:00
|
|
|
return ch;
|
2013-07-23 03:16:37 +02:00
|
|
|
}
|
|
|
|
|
2015-10-03 01:42:29 +02:00
|
|
|
/****************************************************************************
|
2013-07-23 03:16:37 +02:00
|
|
|
* Name: sam_lowsetup
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* This performs basic initialization of the USART used for the serial
|
2019-08-04 22:50:28 +02:00
|
|
|
* console. Its purpose is to get the console output available as soon
|
2013-07-23 03:16:37 +02:00
|
|
|
* as possible.
|
|
|
|
*
|
2015-10-03 01:42:29 +02:00
|
|
|
****************************************************************************/
|
2013-07-23 03:16:37 +02:00
|
|
|
|
|
|
|
void sam_lowsetup(void)
|
|
|
|
{
|
2015-09-11 20:00:30 +02:00
|
|
|
/* Enable clocking for all selected UART/USARTs (USARTs may not
|
|
|
|
* necessarily be configured as UARTs).
|
|
|
|
*/
|
2013-07-23 03:16:37 +02:00
|
|
|
|
|
|
|
#ifdef CONFIG_SAMA5_UART0
|
|
|
|
sam_uart0_enableclk();
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_SAMA5_UART1
|
|
|
|
sam_uart1_enableclk();
|
|
|
|
#endif
|
2015-09-09 20:11:45 +02:00
|
|
|
#ifdef CONFIG_SAMA5_UART2
|
|
|
|
sam_uart2_enableclk();
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_SAMA5_UART3
|
|
|
|
sam_uart3_enableclk();
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_SAMA5_UART4
|
|
|
|
sam_uart4_enableclk();
|
|
|
|
#endif
|
2016-05-25 19:21:48 +02:00
|
|
|
#ifdef CONFIG_USART0_SERIALDRIVER
|
2013-07-23 03:16:37 +02:00
|
|
|
sam_usart0_enableclk();
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_SAMA5_USART1
|
|
|
|
sam_usart1_enableclk();
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_SAMA5_USART2
|
|
|
|
sam_usart2_enableclk();
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_SAMA5_USART3
|
|
|
|
sam_usart3_enableclk();
|
|
|
|
#endif
|
2015-09-11 22:54:30 +02:00
|
|
|
#ifdef CONFIG_SAMA5_FLEXCOM0
|
|
|
|
sam_flexcom0_enableclk();
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_SAMA5_FLEXCOM1
|
|
|
|
sam_flexcom1_enableclk();
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_SAMA5_FLEXCOM2
|
|
|
|
sam_flexcom2_enableclk();
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_SAMA5_FLEXCOM3
|
|
|
|
sam_flexcom3_enableclk();
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_SAMA5_FLEXCOM4
|
|
|
|
sam_flexcom4_enableclk();
|
|
|
|
#endif
|
2013-07-23 03:16:37 +02:00
|
|
|
|
2015-09-11 20:00:30 +02:00
|
|
|
/* Configure UART pins for all selected UART/USARTs. USARTs pins are
|
|
|
|
* only configured if the USART is also configured as as a UART.
|
|
|
|
*/
|
2013-07-23 03:16:37 +02:00
|
|
|
|
|
|
|
#ifdef CONFIG_SAMA5_UART0
|
2020-01-02 17:49:34 +01:00
|
|
|
sam_configpio(PIO_UART0_RXD);
|
|
|
|
sam_configpio(PIO_UART0_TXD);
|
2013-07-23 03:16:37 +02:00
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef CONFIG_SAMA5_UART1
|
2020-01-02 17:49:34 +01:00
|
|
|
sam_configpio(PIO_UART1_RXD);
|
|
|
|
sam_configpio(PIO_UART1_TXD);
|
2013-07-23 03:16:37 +02:00
|
|
|
#endif
|
|
|
|
|
2015-09-09 20:11:45 +02:00
|
|
|
#ifdef CONFIG_SAMA5_UART2
|
2020-01-02 17:49:34 +01:00
|
|
|
sam_configpio(PIO_UART2_RXD);
|
|
|
|
sam_configpio(PIO_UART2_TXD);
|
2015-09-09 20:11:45 +02:00
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef CONFIG_SAMA5_UART3
|
2020-01-02 17:49:34 +01:00
|
|
|
sam_configpio(PIO_UART3_RXD);
|
|
|
|
sam_configpio(PIO_UART3_TXD);
|
2015-09-09 20:11:45 +02:00
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef CONFIG_SAMA5_UART4
|
2020-01-02 17:49:34 +01:00
|
|
|
sam_configpio(PIO_UART4_RXD);
|
|
|
|
sam_configpio(PIO_UART4_TXD);
|
2015-09-09 20:11:45 +02:00
|
|
|
#endif
|
|
|
|
|
2016-05-25 19:21:48 +02:00
|
|
|
#if defined(CONFIG_USART0_SERIALDRIVER) && defined(CONFIG_SAMA5_USART0)
|
2020-01-02 17:49:34 +01:00
|
|
|
sam_configpio(PIO_USART0_RXD);
|
|
|
|
sam_configpio(PIO_USART0_TXD);
|
2013-07-23 03:16:37 +02:00
|
|
|
#ifdef CONFIG_USART0_OFLOWCONTROL
|
2020-01-02 17:49:34 +01:00
|
|
|
sam_configpio(PIO_USART0_CTS);
|
2013-07-23 03:16:37 +02:00
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_USART0_IFLOWCONTROL
|
2020-01-02 17:49:34 +01:00
|
|
|
sam_configpio(PIO_USART0_RTS);
|
2013-07-23 03:16:37 +02:00
|
|
|
#endif
|
|
|
|
#endif
|
|
|
|
|
2016-05-25 19:21:48 +02:00
|
|
|
#if defined(CONFIG_USART1_SERIALDRIVER) && defined(CONFIG_SAMA5_USART1)
|
2020-01-02 17:49:34 +01:00
|
|
|
sam_configpio(PIO_USART1_RXD);
|
|
|
|
sam_configpio(PIO_USART1_TXD);
|
2013-07-23 03:16:37 +02:00
|
|
|
#ifdef CONFIG_USART1_OFLOWCONTROL
|
2020-01-02 17:49:34 +01:00
|
|
|
sam_configpio(PIO_USART1_CTS);
|
2013-07-23 03:16:37 +02:00
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_USART1_IFLOWCONTROL
|
2020-01-02 17:49:34 +01:00
|
|
|
sam_configpio(PIO_USART1_RTS);
|
2013-07-23 03:16:37 +02:00
|
|
|
#endif
|
|
|
|
#endif
|
|
|
|
|
2016-05-25 19:21:48 +02:00
|
|
|
#if defined(CONFIG_USART2_SERIALDRIVER) && defined(CONFIG_SAMA5_USART2)
|
2020-01-02 17:49:34 +01:00
|
|
|
sam_configpio(PIO_USART2_RXD);
|
|
|
|
sam_configpio(PIO_USART2_TXD);
|
2013-07-23 03:16:37 +02:00
|
|
|
#ifdef CONFIG_USART2_OFLOWCONTROL
|
2020-01-02 17:49:34 +01:00
|
|
|
sam_configpio(PIO_USART2_CTS);
|
2013-07-23 03:16:37 +02:00
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_USART2_IFLOWCONTROL
|
2020-01-02 17:49:34 +01:00
|
|
|
sam_configpio(PIO_USART2_RTS);
|
2013-07-23 03:16:37 +02:00
|
|
|
#endif
|
|
|
|
#endif
|
|
|
|
|
2016-05-25 19:21:48 +02:00
|
|
|
#if defined(CONFIG_USART3_SERIALDRIVER) && defined(CONFIG_SAMA5_USART3)
|
2020-01-02 17:49:34 +01:00
|
|
|
sam_configpio(PIO_USART3_RXD);
|
|
|
|
sam_configpio(PIO_USART3_TXD);
|
2013-07-23 03:16:37 +02:00
|
|
|
#ifdef CONFIG_USART3_OFLOWCONTROL
|
2020-01-02 17:49:34 +01:00
|
|
|
sam_configpio(PIO_USART3_CTS);
|
2013-07-23 03:16:37 +02:00
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_USART3_IFLOWCONTROL
|
2020-01-02 17:49:34 +01:00
|
|
|
sam_configpio(PIO_USART3_RTS);
|
2013-07-23 03:16:37 +02:00
|
|
|
#endif
|
2015-09-11 20:00:30 +02:00
|
|
|
#endif
|
|
|
|
|
2016-05-25 19:21:48 +02:00
|
|
|
#if defined(CONFIG_USART4_SERIALDRIVER) && defined(CONFIG_SAMA5_USART4)
|
2020-01-02 17:49:34 +01:00
|
|
|
sam_configpio(PIO_USART4_RXD);
|
|
|
|
sam_configpio(PIO_USART4_TXD);
|
2015-09-11 20:00:30 +02:00
|
|
|
#ifdef CONFIG_USART4_OFLOWCONTROL
|
2020-01-02 17:49:34 +01:00
|
|
|
sam_configpio(PIO_USART4_CTS);
|
2015-09-11 20:00:30 +02:00
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_USART4_IFLOWCONTROL
|
2020-01-02 17:49:34 +01:00
|
|
|
sam_configpio(PIO_USART4_RTS);
|
2015-09-11 20:00:30 +02:00
|
|
|
#endif
|
2015-09-11 22:54:30 +02:00
|
|
|
#endif
|
|
|
|
|
|
|
|
/* For Flexcom USARTs:
|
|
|
|
*
|
|
|
|
* FLEXCOM_IO0 = TXD
|
|
|
|
* FLEXCOM_IO1 = RXD
|
|
|
|
* FLEXCOM_IO2 = SCK
|
|
|
|
* FLEXCOM_IO3 = CTS
|
|
|
|
* FLEXCOM_IO4 = RTS
|
|
|
|
*/
|
|
|
|
|
2016-05-25 19:21:48 +02:00
|
|
|
#if defined(CONFIG_USART0_SERIALDRIVER) && defined(CONFIG_SAMA5_FLEXCOM0_USART)
|
2020-01-02 17:49:34 +01:00
|
|
|
sam_configpio(PIO_FLEXCOM0_IO0);
|
|
|
|
sam_configpio(PIO_FLEXCOM0_IO1);
|
2015-09-11 22:54:30 +02:00
|
|
|
#ifdef CONFIG_USART0_OFLOWCONTROL
|
2020-01-02 17:49:34 +01:00
|
|
|
sam_configpio(PIO_FLEXCOM0_IO3);
|
2015-09-11 22:54:30 +02:00
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_USART0_IFLOWCONTROL
|
2020-01-02 17:49:34 +01:00
|
|
|
sam_configpio(PIO_FLEXCOM0_IO4);
|
2015-09-11 22:54:30 +02:00
|
|
|
#endif
|
|
|
|
#endif
|
|
|
|
|
2016-05-25 19:21:48 +02:00
|
|
|
#if defined(CONFIG_USART1_SERIALDRIVER) && defined(CONFIG_SAMA5_FLEXCOM1_USART)
|
2020-01-02 17:49:34 +01:00
|
|
|
sam_configpio(PIO_FLEXCOM1_IO0);
|
|
|
|
sam_configpio(PIO_FLEXCOM1_IO1);
|
2015-09-11 22:54:30 +02:00
|
|
|
#ifdef CONFIG_USART1_OFLOWCONTROL
|
2020-01-02 17:49:34 +01:00
|
|
|
sam_configpio(PIO_FLEXCOM1_IO3);
|
2015-09-11 22:54:30 +02:00
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_USART1_IFLOWCONTROL
|
2020-01-02 17:49:34 +01:00
|
|
|
sam_configpio(PIO_FLEXCOM1_IO4);
|
2015-09-11 22:54:30 +02:00
|
|
|
#endif
|
|
|
|
#endif
|
|
|
|
|
2016-05-25 19:21:48 +02:00
|
|
|
#if defined(CONFIG_USART2_SERIALDRIVER) && defined(CONFIG_SAMA5_FLEXCOM2_USART)
|
2020-01-02 17:49:34 +01:00
|
|
|
sam_configpio(PIO_FLEXCOM2_IO0);
|
|
|
|
sam_configpio(PIO_FLEXCOM2_IO1);
|
2015-09-11 22:54:30 +02:00
|
|
|
#ifdef CONFIG_USART2_OFLOWCONTROL
|
2020-01-02 17:49:34 +01:00
|
|
|
sam_configpio(PIO_FLEXCOM2_IO3);
|
2015-09-11 22:54:30 +02:00
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_USART2_IFLOWCONTROL
|
2020-01-02 17:49:34 +01:00
|
|
|
sam_configpio(PIO_FLEXCOM2_IO4);
|
2015-09-11 22:54:30 +02:00
|
|
|
#endif
|
|
|
|
#endif
|
|
|
|
|
2016-05-25 19:21:48 +02:00
|
|
|
#if defined(CONFIG_USART3_SERIALDRIVER) && defined(CONFIG_SAMA5_FLEXCOM3_USART)
|
2020-01-02 17:49:34 +01:00
|
|
|
sam_configpio(PIO_FLEXCOM3_IO0);
|
|
|
|
sam_configpio(PIO_FLEXCOM3_IO1);
|
2015-09-11 22:54:30 +02:00
|
|
|
#ifdef CONFIG_USART3_OFLOWCONTROL
|
2020-01-02 17:49:34 +01:00
|
|
|
sam_configpio(PIO_FLEXCOM3_IO3);
|
2015-09-11 22:54:30 +02:00
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_USART3_IFLOWCONTROL
|
2020-01-02 17:49:34 +01:00
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sam_configpio(PIO_FLEXCOM3_IO4);
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2015-09-11 22:54:30 +02:00
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#endif
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#endif
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2016-05-25 19:21:48 +02:00
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#if defined(CONFIG_USART4_SERIALDRIVER) && defined(CONFIG_SAMA5_FLEXCOM4_USART)
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2020-01-02 17:49:34 +01:00
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sam_configpio(PIO_FLEXCOM4_IO0);
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sam_configpio(PIO_FLEXCOM4_IO1);
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2015-09-11 22:54:30 +02:00
|
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|
#ifdef CONFIG_USART4_OFLOWCONTROL
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2020-01-02 17:49:34 +01:00
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sam_configpio(PIO_FLEXCOM4_IO3);
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2015-09-11 22:54:30 +02:00
|
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|
#endif
|
|
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|
#ifdef CONFIG_USART4_IFLOWCONTROL
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2020-01-02 17:49:34 +01:00
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sam_configpio(PIO_FLEXCOM4_IO4);
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2015-09-11 22:54:30 +02:00
|
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|
#endif
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2013-07-23 03:16:37 +02:00
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#endif
|
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|
|
|
|
/* Configure the console (only) */
|
2014-04-01 19:24:15 +02:00
|
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|
|
2015-09-11 22:30:19 +02:00
|
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|
#if (defined(SAMA5_HAVE_UART_CONSOLE) || defined(SAMA5_HAVE_USART_CONSOLE)) && \
|
|
|
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!defined(SUPPRESS_CONSOLE_CONFIG)
|
2013-07-23 03:16:37 +02:00
|
|
|
/* Reset and disable receiver and transmitter */
|
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|
|
|
|
|
|
putreg32((UART_CR_RSTRX | UART_CR_RSTTX | UART_CR_RXDIS | UART_CR_TXDIS),
|
2013-07-23 04:59:47 +02:00
|
|
|
SAM_CONSOLE_VBASE + SAM_UART_CR_OFFSET);
|
2013-07-23 03:16:37 +02:00
|
|
|
|
|
|
|
/* Disable all interrupts */
|
|
|
|
|
2013-07-23 04:59:47 +02:00
|
|
|
putreg32(0xffffffff, SAM_CONSOLE_VBASE + SAM_UART_IDR_OFFSET);
|
2013-07-23 03:16:37 +02:00
|
|
|
|
|
|
|
/* Set up the mode register */
|
|
|
|
|
2013-07-23 04:59:47 +02:00
|
|
|
putreg32(MR_VALUE, SAM_CONSOLE_VBASE + SAM_UART_MR_OFFSET);
|
2013-07-23 03:16:37 +02:00
|
|
|
|
|
|
|
/* Configure the console baud. NOTE: Oversampling by 8 is not supported.
|
|
|
|
* This may limit BAUD rates for lower USART clocks.
|
|
|
|
*/
|
|
|
|
|
|
|
|
putreg32(((SAM_USART_CLOCK + (SAM_CONSOLE_BAUD << 3)) / (SAM_CONSOLE_BAUD << 4)),
|
2013-07-23 04:59:47 +02:00
|
|
|
SAM_CONSOLE_VBASE + SAM_UART_BRGR_OFFSET);
|
2013-07-23 03:16:37 +02:00
|
|
|
|
|
|
|
/* Enable receiver & transmitter */
|
|
|
|
|
|
|
|
putreg32((UART_CR_RXEN | UART_CR_TXEN),
|
2013-07-23 04:59:47 +02:00
|
|
|
SAM_CONSOLE_VBASE + SAM_UART_CR_OFFSET);
|
2015-09-11 22:30:19 +02:00
|
|
|
|
|
|
|
#elif defined(SAMA5_HAVE_FLEXCOM_CONSOLE) && !defined(SUPPRESS_CONSOLE_CONFIG)
|
2015-09-12 02:42:49 +02:00
|
|
|
/* Select USART mode for the Flexcom */
|
|
|
|
|
|
|
|
putreg32(FLEX_MR_OPMODE_USART, SAM_CONSOLE_VBASE + SAM_FLEX_MR_OFFSET);
|
|
|
|
|
2015-09-11 22:30:19 +02:00
|
|
|
/* Reset and disable receiver and transmitter */
|
|
|
|
|
|
|
|
putreg32((FLEXUS_CR_RSTRX | FLEXUS_CR_RSTTX | FLEXUS_CR_RXDIS | FLEXUS_CR_TXDIS),
|
|
|
|
SAM_CONSOLE_VBASE + SAM_FLEXUS_CR_OFFSET);
|
|
|
|
|
|
|
|
/* Disable all interrupts */
|
|
|
|
|
|
|
|
putreg32(0xffffffff, SAM_CONSOLE_VBASE + SAM_FLEXUS_IDR_OFFSET);
|
|
|
|
|
|
|
|
/* Set up the mode register */
|
|
|
|
|
|
|
|
putreg32(MR_VALUE, SAM_CONSOLE_VBASE + SAM_FLEXUS_MR_OFFSET);
|
|
|
|
|
|
|
|
/* Configure the console baud. NOTE: Oversampling by 8 is not supported.
|
|
|
|
* This may limit BAUD rates for lower USART clocks.
|
|
|
|
*/
|
|
|
|
|
|
|
|
putreg32(((SAM_USART_CLOCK + (SAM_CONSOLE_BAUD << 3)) / (SAM_CONSOLE_BAUD << 4)),
|
|
|
|
SAM_CONSOLE_VBASE + SAM_FLEXUS_BRGR_OFFSET);
|
|
|
|
|
|
|
|
/* Enable receiver & transmitter */
|
|
|
|
|
|
|
|
putreg32((FLEXUS_CR_RXEN | FLEXUS_CR_TXEN),
|
|
|
|
SAM_CONSOLE_VBASE + SAM_FLEXUS_CR_OFFSET);
|
|
|
|
|
2013-07-23 03:16:37 +02:00
|
|
|
#endif
|
2014-04-01 19:24:15 +02:00
|
|
|
|
|
|
|
#ifdef CONFIG_SAMA5_DBGU
|
|
|
|
/* Initialize the DBGU (might be the serial console) */
|
|
|
|
|
|
|
|
sam_dbgu_initialize();
|
|
|
|
#endif
|
2013-07-23 03:16:37 +02:00
|
|
|
}
|