nuttx/arch/arm/src/stm32f0l0g0/stm32_rcc.h

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/************************************************************************************
* arch/arm/src/stm32f0l0g0/stm32_rcc.h
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*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.orgr>
* Alan Carvalho de Assis <acassis@gmail.com>
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*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_RCC_H
#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_RCC_H
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/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "arm_arch.h"
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#include "chip.h"
#include "hardware/stm32_rcc.h"
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Brings in initial WIP support for the STML0. This initial commit is in pretty bad shape and, hence it it marked EXPERIMENTAL." Squashed commit of the following: arch/arm/src/stm32f0l0: Various changes for a clean compilation. Still does not compile correctly due to missing FLASH latency definitions. arch/arm/src/stm32f0l0/hardware: Add framework for the STM32 L0. Currently set to same as the STM32F0. arch/arm/src/stm32f0l0/hardware: Very fragmentary FLASH header register definitions for the STM32 L0. arch/arm/src/stm32f0l0: Bring in DMA v1. Cannot possibly be functionaly yet due to the limited number for M0 interrupts. arch/arm/src/stm32f0l0: Add STM32 F0/L0 LSE and backup power domain controls. arch/arm/src/stm32f0l0/hardware/stm32l0_pwr.h: Add STM32L0 PWR header file. arch/arm/include/stm32f0l0/chip.h: Clean up WIP chip header file. arch/arm/include/stm32f0l0/chip.h: WIP. arm/src/stm32f0l0: Resolve some small differences between F0 and L0 GPIO pin options. arch/arm/src/stm32f0l0: Better integrate STM32L0 header files. nuttx/arch/arm/include/stm32f0l0: Add STM32L0 IRQ number definition file. arch/arm/src/stm32f0l0: Add STM32L0 RCC driver. arch/arm/src/stm32f0l0/hardware: Adds basic STM32L0 header files. arch/arm/src/stm32f0l0: Add STM32L0 chip selections. configs/: Hook new STM32L0 boards into the configuration system. configs: nucleo boards use as default ST LINK MCO as clock input from MCU and for this HSEBYP must be enabled configs: add basic support for nucleo-l073rz configs: add basic support for b-l072z-lrwan1
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/************************************************************************************
* Public Function Prototypes
Brings in initial WIP support for the STML0. This initial commit is in pretty bad shape and, hence it it marked EXPERIMENTAL." Squashed commit of the following: arch/arm/src/stm32f0l0: Various changes for a clean compilation. Still does not compile correctly due to missing FLASH latency definitions. arch/arm/src/stm32f0l0/hardware: Add framework for the STM32 L0. Currently set to same as the STM32F0. arch/arm/src/stm32f0l0/hardware: Very fragmentary FLASH header register definitions for the STM32 L0. arch/arm/src/stm32f0l0: Bring in DMA v1. Cannot possibly be functionaly yet due to the limited number for M0 interrupts. arch/arm/src/stm32f0l0: Add STM32 F0/L0 LSE and backup power domain controls. arch/arm/src/stm32f0l0/hardware/stm32l0_pwr.h: Add STM32L0 PWR header file. arch/arm/include/stm32f0l0/chip.h: Clean up WIP chip header file. arch/arm/include/stm32f0l0/chip.h: WIP. arm/src/stm32f0l0: Resolve some small differences between F0 and L0 GPIO pin options. arch/arm/src/stm32f0l0: Better integrate STM32L0 header files. nuttx/arch/arm/include/stm32f0l0: Add STM32L0 IRQ number definition file. arch/arm/src/stm32f0l0: Add STM32L0 RCC driver. arch/arm/src/stm32f0l0/hardware: Adds basic STM32L0 header files. arch/arm/src/stm32f0l0: Add STM32L0 chip selections. configs/: Hook new STM32L0 boards into the configuration system. configs: nucleo boards use as default ST LINK MCO as clock input from MCU and for this HSEBYP must be enabled configs: add basic support for nucleo-l073rz configs: add basic support for b-l072z-lrwan1
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************************************************************************************/
/************************************************************************************
* Name: stm32_clockconfig
*
* Description:
* Called to initialize the STM32F0XX. This does whatever setup is needed to put
* the MCU in a usable state. This includes the initialization of clocking using
* the settings in board.h.
*
************************************************************************************/
void stm32_clockconfig(void);
Brings in initial WIP support for the STML0. This initial commit is in pretty bad shape and, hence it it marked EXPERIMENTAL." Squashed commit of the following: arch/arm/src/stm32f0l0: Various changes for a clean compilation. Still does not compile correctly due to missing FLASH latency definitions. arch/arm/src/stm32f0l0/hardware: Add framework for the STM32 L0. Currently set to same as the STM32F0. arch/arm/src/stm32f0l0/hardware: Very fragmentary FLASH header register definitions for the STM32 L0. arch/arm/src/stm32f0l0: Bring in DMA v1. Cannot possibly be functionaly yet due to the limited number for M0 interrupts. arch/arm/src/stm32f0l0: Add STM32 F0/L0 LSE and backup power domain controls. arch/arm/src/stm32f0l0/hardware/stm32l0_pwr.h: Add STM32L0 PWR header file. arch/arm/include/stm32f0l0/chip.h: Clean up WIP chip header file. arch/arm/include/stm32f0l0/chip.h: WIP. arm/src/stm32f0l0: Resolve some small differences between F0 and L0 GPIO pin options. arch/arm/src/stm32f0l0: Better integrate STM32L0 header files. nuttx/arch/arm/include/stm32f0l0: Add STM32L0 IRQ number definition file. arch/arm/src/stm32f0l0: Add STM32L0 RCC driver. arch/arm/src/stm32f0l0/hardware: Adds basic STM32L0 header files. arch/arm/src/stm32f0l0: Add STM32L0 chip selections. configs/: Hook new STM32L0 boards into the configuration system. configs: nucleo boards use as default ST LINK MCO as clock input from MCU and for this HSEBYP must be enabled configs: add basic support for nucleo-l073rz configs: add basic support for b-l072z-lrwan1
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/************************************************************************************
* Name: stm32_rcc_enablelse
*
* Description:
* Enable the External Low-Speed (LSE) Oscillator.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
************************************************************************************/
void stm32_rcc_enablelse(void);
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_RCC_H */