2015-10-03 15:25:03 +02:00
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/****************************************************************************
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2012-09-13 20:32:24 +02:00
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* arch/arm/src/lpc17xx/lpc17_i2c.c
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*
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* Copyright (C) 2011 Li Zhuoyi. All rights reserved.
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* Author: Li Zhuoyi <lzyy.cn@gmail.com>
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* History: 0.1 2011-08-20 initial version
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2013-05-08 14:57:55 +02:00
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*
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2012-09-13 20:32:24 +02:00
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* Derived from arch/arm/src/lpc31xx/lpc31_i2c.c
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*
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* Author: David Hewson
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*
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2013-04-30 16:08:02 +02:00
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* Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved.
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2012-09-13 20:32:24 +02:00
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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2015-10-03 15:25:03 +02:00
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****************************************************************************/
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2012-09-13 20:32:24 +02:00
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2015-10-03 15:25:03 +02:00
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/****************************************************************************
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2012-09-13 20:32:24 +02:00
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* Included Files
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2015-10-03 15:25:03 +02:00
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****************************************************************************/
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2012-09-13 20:32:24 +02:00
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <stdlib.h>
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#include <string.h>
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#include <errno.h>
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#include <debug.h>
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#include <nuttx/arch.h>
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2014-08-21 19:16:55 +02:00
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#include <nuttx/wdog.h>
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2016-01-30 14:59:44 +01:00
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#include <nuttx/i2c/i2c_master.h>
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2012-09-13 20:32:24 +02:00
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#include <arch/irq.h>
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#include <arch/board/board.h>
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#include "up_arch.h"
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#include "up_internal.h"
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2013-01-18 20:16:44 +01:00
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#include "chip.h"
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#include "chip/lpc17_syscon.h"
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#include "lpc17_gpio.h"
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2012-09-13 20:32:24 +02:00
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#include "lpc17_i2c.h"
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#if defined(CONFIG_LPC17_I2C0) || defined(CONFIG_LPC17_I2C1) || defined(CONFIG_LPC17_I2C2)
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#ifndef GPIO_I2C1_SCL
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2015-09-05 17:07:37 +02:00
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# define GPIO_I2C1_SCL GPIO_I2C1_SCL_1
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# define GPIO_I2C1_SDA GPIO_I2C1_SDA_1
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2012-09-13 20:32:24 +02:00
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#endif
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2012-11-27 16:09:12 +01:00
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2012-09-13 20:32:24 +02:00
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#ifndef CONFIG_I2C0_FREQ
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2015-09-05 17:07:37 +02:00
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# define CONFIG_I2C0_FREQ 100000
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2012-09-13 20:32:24 +02:00
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#endif
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2012-11-27 16:09:12 +01:00
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2012-09-13 20:32:24 +02:00
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#ifndef CONFIG_I2C1_FREQ
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2015-09-05 17:07:37 +02:00
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# define CONFIG_I2C1_FREQ 100000
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2012-09-13 20:32:24 +02:00
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#endif
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2012-11-27 16:09:12 +01:00
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2012-09-13 20:32:24 +02:00
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#ifndef CONFIG_I2C2_FREQ
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2015-09-05 17:07:37 +02:00
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# define CONFIG_I2C2_FREQ 100000
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2012-09-13 20:32:24 +02:00
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#endif
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2015-10-03 15:25:03 +02:00
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/****************************************************************************
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2015-04-08 16:04:12 +02:00
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* Pre-processor Definitions
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2015-10-03 15:25:03 +02:00
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****************************************************************************/
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2012-09-13 20:32:24 +02:00
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2015-10-03 15:25:03 +02:00
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/****************************************************************************
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2012-09-13 20:32:24 +02:00
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* Pre-processor Definitions
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2015-10-03 15:25:03 +02:00
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****************************************************************************/
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2012-09-13 20:32:24 +02:00
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#define I2C_TIMEOUT ((20 * CLK_TCK) / 1000) /* 20 mS */
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2015-10-03 15:25:03 +02:00
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/****************************************************************************
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2012-09-13 20:32:24 +02:00
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* Private Data
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2015-10-03 15:25:03 +02:00
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****************************************************************************/
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2012-11-27 16:09:12 +01:00
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2012-09-13 20:32:24 +02:00
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struct lpc17_i2cdev_s
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{
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2016-01-30 15:35:46 +01:00
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struct i2c_master_s dev; /* Generic I2C device */
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2012-11-27 16:09:12 +01:00
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struct i2c_msg_s msg; /* a single message for legacy read/write */
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unsigned int base; /* Base address of registers */
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uint16_t irqid; /* IRQ for this device */
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sem_t mutex; /* Only one thread can access at a time */
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sem_t wait; /* Place to wait for state machine completion */
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volatile uint8_t state; /* State of state machine */
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WDOG_ID timeout; /* watchdog to timeout when bus hung */
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uint16_t wrcnt; /* number of bytes sent to tx fifo */
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uint16_t rdcnt; /* number of bytes read from rx fifo */
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2012-09-13 20:32:24 +02:00
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};
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static struct lpc17_i2cdev_s i2cdevices[3];
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2015-10-03 15:25:03 +02:00
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/****************************************************************************
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2012-09-13 20:32:24 +02:00
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* Private Functions
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2015-10-03 15:25:03 +02:00
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****************************************************************************/
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2012-11-27 16:09:12 +01:00
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static int i2c_start(struct lpc17_i2cdev_s *priv);
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static void i2c_stop(struct lpc17_i2cdev_s *priv);
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static int i2c_interrupt(int irq, FAR void *context);
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static void i2c_timeout(int argc, uint32_t arg, ...);
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2012-09-13 20:32:24 +02:00
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2015-10-03 15:25:03 +02:00
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/****************************************************************************
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2012-09-13 20:32:24 +02:00
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* I2C device operations
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2015-10-03 15:25:03 +02:00
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****************************************************************************/
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2012-09-13 20:32:24 +02:00
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2016-01-30 15:35:46 +01:00
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static uint32_t i2c_setfrequency(FAR struct i2c_master_s *dev, uint32_t frequency);
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static int i2c_setaddress(FAR struct i2c_master_s *dev, int addr, int nbits);
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static int i2c_write(FAR struct i2c_master_s *dev, const uint8_t *buffer, int buflen);
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static int i2c_read(FAR struct i2c_master_s *dev, uint8_t *buffer, int buflen);
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static int i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s *msgs, int count);
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2012-09-13 20:32:24 +02:00
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struct i2c_ops_s lpc17_i2c_ops =
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{
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2012-11-27 16:09:12 +01:00
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.setfrequency = i2c_setfrequency,
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.setaddress = i2c_setaddress,
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.write = i2c_write,
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.read = i2c_read,
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2012-09-13 20:32:24 +02:00
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#ifdef CONFIG_I2C_TRANSFER
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2012-11-27 16:09:12 +01:00
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.transfer = i2c_transfer
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2012-09-13 20:32:24 +02:00
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#endif
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};
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2015-10-03 15:25:03 +02:00
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/****************************************************************************
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2012-09-13 20:32:24 +02:00
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* Name: lpc17_i2c_setfrequency
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*
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* Description:
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* Set the frequence for the next transfer
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*
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2015-10-03 15:25:03 +02:00
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****************************************************************************/
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2012-09-13 20:32:24 +02:00
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2016-01-30 15:35:46 +01:00
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static uint32_t i2c_setfrequency(FAR struct i2c_master_s *dev, uint32_t frequency)
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2012-09-13 20:32:24 +02:00
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{
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2012-11-27 16:09:12 +01:00
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struct lpc17_i2cdev_s *priv = (struct lpc17_i2cdev_s *) dev;
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2012-09-13 20:32:24 +02:00
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2012-11-27 16:09:12 +01:00
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if (frequency > 100000)
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2012-09-13 20:32:24 +02:00
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{
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2012-11-27 16:09:12 +01:00
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/* asymetric per 400Khz I2C spec */
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putreg32(LPC17_CCLK / (83 + 47) * 47 / frequency, priv->base + LPC17_I2C_SCLH_OFFSET);
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putreg32(LPC17_CCLK / (83 + 47) * 83 / frequency, priv->base + LPC17_I2C_SCLL_OFFSET);
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2012-09-13 20:32:24 +02:00
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}
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2012-11-27 16:09:12 +01:00
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else
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2012-09-13 20:32:24 +02:00
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{
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2012-11-27 16:09:12 +01:00
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/* 50/50 mark space ratio */
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putreg32(LPC17_CCLK / 100 * 50 / frequency, priv->base + LPC17_I2C_SCLH_OFFSET);
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putreg32(LPC17_CCLK / 100 * 50 / frequency, priv->base + LPC17_I2C_SCLL_OFFSET);
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2012-09-13 20:32:24 +02:00
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}
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2012-11-27 16:09:12 +01:00
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/* FIXME: This function should return the actual selected frequency */
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return frequency;
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2012-09-13 20:32:24 +02:00
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}
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2015-10-03 15:25:03 +02:00
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/****************************************************************************
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2012-09-13 20:32:24 +02:00
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* Name: lpc17_i2c_setaddress
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*
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* Description:
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* Set the I2C slave address for a subsequent read/write
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*
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2015-10-03 15:25:03 +02:00
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****************************************************************************/
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2012-11-27 16:09:12 +01:00
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2016-01-30 15:35:46 +01:00
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static int i2c_setaddress(FAR struct i2c_master_s *dev, int addr, int nbits)
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2012-09-13 20:32:24 +02:00
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{
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2012-11-27 16:09:12 +01:00
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struct lpc17_i2cdev_s *priv = (struct lpc17_i2cdev_s *) dev;
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2012-09-13 20:32:24 +02:00
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2012-11-27 16:09:12 +01:00
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DEBUGASSERT(dev != NULL);
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2015-10-06 01:13:53 +02:00
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DEBUGASSERT(nbits == 7);
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2012-09-13 20:32:24 +02:00
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2013-05-08 14:57:55 +02:00
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priv->msg.addr = addr << 1;
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2012-11-27 16:09:12 +01:00
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priv->msg.flags = 0 ;
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2012-09-13 20:32:24 +02:00
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2012-11-27 16:09:12 +01:00
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return OK;
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2012-09-13 20:32:24 +02:00
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}
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2015-10-03 15:25:03 +02:00
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/****************************************************************************
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2012-09-13 20:32:24 +02:00
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* Name: lpc17_i2c_write
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*
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* Description:
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* Send a block of data on I2C using the previously selected I2C
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* frequency and slave address.
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*
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2015-10-03 15:25:03 +02:00
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****************************************************************************/
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2012-11-27 16:09:12 +01:00
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2016-01-30 15:35:46 +01:00
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static int i2c_write(FAR struct i2c_master_s *dev, const uint8_t *buffer, int buflen)
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2012-09-13 20:32:24 +02:00
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{
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2012-11-27 16:09:12 +01:00
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struct lpc17_i2cdev_s *priv = (struct lpc17_i2cdev_s *) dev;
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int ret;
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2012-09-13 20:32:24 +02:00
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2012-11-27 16:09:12 +01:00
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DEBUGASSERT(dev != NULL);
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2012-09-13 20:32:24 +02:00
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2013-05-08 14:57:55 +02:00
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priv->wrcnt = 0;
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priv->rdcnt = 0;
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priv->msg.addr &= ~0x01;
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2015-10-07 19:39:06 +02:00
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priv->msg.buffer = (uint8_t *)buffer;
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2012-11-27 16:09:12 +01:00
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priv->msg.length = buflen;
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2013-05-08 14:57:55 +02:00
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2012-11-27 16:09:12 +01:00
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ret = i2c_start(priv);
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2012-09-13 20:32:24 +02:00
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2012-11-27 16:09:12 +01:00
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return ret > 0 ? OK : -ETIMEDOUT;
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2012-09-13 20:32:24 +02:00
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}
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2015-10-03 15:25:03 +02:00
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/****************************************************************************
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2012-09-13 20:32:24 +02:00
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* Name: lpc17_i2c_read
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*
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* Description:
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* Receive a block of data on I2C using the previously selected I2C
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* frequency and slave address.
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*
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2015-10-03 15:25:03 +02:00
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****************************************************************************/
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2012-11-27 16:09:12 +01:00
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2016-01-30 15:35:46 +01:00
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static int i2c_read(FAR struct i2c_master_s *dev, uint8_t *buffer, int buflen)
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2012-09-13 20:32:24 +02:00
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{
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2012-11-27 16:09:12 +01:00
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struct lpc17_i2cdev_s *priv = (struct lpc17_i2cdev_s *) dev;
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int ret;
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2012-09-13 20:32:24 +02:00
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2012-11-27 16:09:12 +01:00
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DEBUGASSERT(dev != NULL);
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2012-09-13 20:32:24 +02:00
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2013-05-08 14:57:55 +02:00
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priv->wrcnt = 0;
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priv->rdcnt = 0;
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priv->msg.addr |= 0x01;
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2012-11-27 16:09:12 +01:00
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priv->msg.buffer = buffer;
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priv->msg.length = buflen;
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2012-09-13 20:32:24 +02:00
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2012-11-27 16:09:12 +01:00
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ret = i2c_start(priv);
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2012-09-13 20:32:24 +02:00
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2012-11-27 16:09:12 +01:00
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return ret > 0 ? OK : -ETIMEDOUT;
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2012-09-13 20:32:24 +02:00
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}
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|
2015-10-03 15:25:03 +02:00
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|
|
/****************************************************************************
|
2012-09-13 20:32:24 +02:00
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* Name: i2c_start
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*
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* Description:
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* Perform a I2C transfer start
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*
|
2015-10-03 15:25:03 +02:00
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****************************************************************************/
|
2012-11-27 16:09:12 +01:00
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static int i2c_start(struct lpc17_i2cdev_s *priv)
|
2012-09-13 20:32:24 +02:00
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{
|
2012-11-27 16:09:12 +01:00
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int ret = -1;
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sem_wait(&priv->mutex);
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|
2013-05-08 14:57:55 +02:00
|
|
|
putreg32(I2C_CONCLR_STAC | I2C_CONCLR_SIC, priv->base + LPC17_I2C_CONCLR_OFFSET);
|
|
|
|
putreg32(I2C_CONSET_STA, priv->base + LPC17_I2C_CONSET_OFFSET);
|
2012-11-27 16:09:12 +01:00
|
|
|
|
|
|
|
wd_start(priv->timeout, I2C_TIMEOUT, i2c_timeout, 1, (uint32_t)priv);
|
|
|
|
sem_wait(&priv->wait);
|
|
|
|
wd_cancel(priv->timeout);
|
|
|
|
sem_post(&priv->mutex);
|
|
|
|
|
|
|
|
if (priv-> state == 0x18 || priv->state == 0x28)
|
|
|
|
{
|
|
|
|
ret = priv->wrcnt;
|
|
|
|
}
|
|
|
|
else if (priv-> state == 0x50 || priv->state == 0x58)
|
|
|
|
{
|
|
|
|
ret = priv->rdcnt;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
2013-05-08 14:57:55 +02:00
|
|
|
}
|
2012-09-13 20:32:24 +02:00
|
|
|
|
2015-10-03 15:25:03 +02:00
|
|
|
/****************************************************************************
|
2012-09-13 20:32:24 +02:00
|
|
|
* Name: i2c_stop
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Perform a I2C transfer stop
|
|
|
|
*
|
2015-10-03 15:25:03 +02:00
|
|
|
****************************************************************************/
|
2012-11-27 16:09:12 +01:00
|
|
|
|
|
|
|
static void i2c_stop(struct lpc17_i2cdev_s *priv)
|
2012-09-13 20:32:24 +02:00
|
|
|
{
|
2012-11-27 16:09:12 +01:00
|
|
|
if (priv->state != 0x38)
|
|
|
|
{
|
2013-05-08 14:57:55 +02:00
|
|
|
putreg32(I2C_CONSET_STO | I2C_CONSET_AA, priv->base + LPC17_I2C_CONSET_OFFSET);
|
2012-11-27 16:09:12 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
sem_post(&priv->wait);
|
2012-09-13 20:32:24 +02:00
|
|
|
}
|
|
|
|
|
2015-10-03 15:25:03 +02:00
|
|
|
/****************************************************************************
|
2012-09-13 20:32:24 +02:00
|
|
|
* Name: i2c_timeout
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Watchdog timer for timeout of I2C operation
|
|
|
|
*
|
2015-10-03 15:25:03 +02:00
|
|
|
****************************************************************************/
|
2012-09-13 20:32:24 +02:00
|
|
|
|
2012-11-27 16:09:12 +01:00
|
|
|
static void i2c_timeout(int argc, uint32_t arg, ...)
|
2012-09-13 20:32:24 +02:00
|
|
|
{
|
2012-11-27 16:09:12 +01:00
|
|
|
struct lpc17_i2cdev_s *priv = (struct lpc17_i2cdev_s *) arg;
|
2012-09-13 20:32:24 +02:00
|
|
|
|
2012-11-27 16:09:12 +01:00
|
|
|
irqstate_t flags = irqsave();
|
|
|
|
priv->state = 0xff;
|
|
|
|
sem_post(&priv->wait);
|
|
|
|
irqrestore(flags);
|
2012-09-13 20:32:24 +02:00
|
|
|
}
|
|
|
|
|
2015-10-03 15:25:03 +02:00
|
|
|
/****************************************************************************
|
2012-09-13 20:32:24 +02:00
|
|
|
* Name: i2c_interrupt
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* The I2C Interrupt Handler
|
|
|
|
*
|
2015-10-03 15:25:03 +02:00
|
|
|
****************************************************************************/
|
2012-09-13 20:32:24 +02:00
|
|
|
|
2012-11-27 16:09:12 +01:00
|
|
|
static int i2c_interrupt(int irq, FAR void *context)
|
2012-09-13 20:32:24 +02:00
|
|
|
{
|
2012-11-27 16:09:12 +01:00
|
|
|
struct lpc17_i2cdev_s *priv;
|
|
|
|
uint32_t state;
|
|
|
|
|
2012-09-13 20:32:24 +02:00
|
|
|
#ifdef CONFIG_LPC17_I2C0
|
2012-11-27 16:09:12 +01:00
|
|
|
if (irq == LPC17_IRQ_I2C0)
|
2012-09-13 20:32:24 +02:00
|
|
|
{
|
2015-10-07 19:39:06 +02:00
|
|
|
priv = &i2cdevices[0];
|
2012-09-13 20:32:24 +02:00
|
|
|
}
|
2012-11-27 16:09:12 +01:00
|
|
|
else
|
2012-09-13 20:32:24 +02:00
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_LPC17_I2C1
|
2012-11-27 16:09:12 +01:00
|
|
|
if (irq == LPC17_IRQ_I2C1)
|
2012-09-13 20:32:24 +02:00
|
|
|
{
|
2015-10-07 19:39:06 +02:00
|
|
|
priv = &i2cdevices[1];
|
2012-09-13 20:32:24 +02:00
|
|
|
}
|
2012-11-27 16:09:12 +01:00
|
|
|
else
|
2012-09-13 20:32:24 +02:00
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_LPC17_I2C2
|
2012-11-27 16:09:12 +01:00
|
|
|
if (irq == LPC17_IRQ_I2C2)
|
2012-09-13 20:32:24 +02:00
|
|
|
{
|
2015-10-07 19:39:06 +02:00
|
|
|
priv = &i2cdevices[2];
|
2012-09-13 20:32:24 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
#endif
|
|
|
|
{
|
2013-04-25 23:19:59 +02:00
|
|
|
PANIC();
|
2012-09-13 20:32:24 +02:00
|
|
|
}
|
2012-11-27 16:09:12 +01:00
|
|
|
|
2015-10-07 19:39:06 +02:00
|
|
|
/* Reference UM10360 19.10.5 */
|
2012-11-27 16:09:12 +01:00
|
|
|
|
2013-05-08 14:57:55 +02:00
|
|
|
state = getreg32(priv->base + LPC17_I2C_STAT_OFFSET);
|
|
|
|
putreg32(I2C_CONCLR_SIC, priv->base + LPC17_I2C_CONCLR_OFFSET);
|
2012-11-27 16:09:12 +01:00
|
|
|
priv->state = state;
|
|
|
|
state &= 0xf8;
|
|
|
|
|
|
|
|
switch (state)
|
|
|
|
{
|
2015-10-06 01:13:53 +02:00
|
|
|
case 0x00: /* Bus Error */
|
2013-05-08 14:57:55 +02:00
|
|
|
case 0x20:
|
2012-11-27 16:09:12 +01:00
|
|
|
case 0x30:
|
|
|
|
case 0x38:
|
|
|
|
case 0x48:
|
|
|
|
i2c_stop(priv);
|
|
|
|
break;
|
|
|
|
|
2015-10-06 01:13:53 +02:00
|
|
|
case 0x08: /* START */
|
|
|
|
case 0x10: /* Repeat START */
|
2013-05-08 14:57:55 +02:00
|
|
|
putreg32(priv->msg.addr, priv->base + LPC17_I2C_DAT_OFFSET);
|
|
|
|
putreg32(I2C_CONCLR_STAC, priv->base + LPC17_I2C_CONCLR_OFFSET);
|
2012-11-27 16:09:12 +01:00
|
|
|
break;
|
|
|
|
|
|
|
|
case 0x18:
|
|
|
|
priv->wrcnt = 0;
|
2013-05-08 14:57:55 +02:00
|
|
|
putreg32(priv->msg.buffer[0], priv->base + LPC17_I2C_DAT_OFFSET);
|
|
|
|
break;
|
2012-11-27 16:09:12 +01:00
|
|
|
|
|
|
|
case 0x28:
|
|
|
|
priv->wrcnt++;
|
2015-10-07 19:39:06 +02:00
|
|
|
if (priv->wrcnt < priv->msg.length)
|
2012-11-27 16:09:12 +01:00
|
|
|
{
|
2013-05-08 14:57:55 +02:00
|
|
|
putreg32(priv->msg.buffer[priv->wrcnt], priv->base + LPC17_I2C_DAT_OFFSET);
|
2012-11-27 16:09:12 +01:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
i2c_stop(priv);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 0x40:
|
2013-05-08 14:57:55 +02:00
|
|
|
priv->rdcnt = 0;
|
|
|
|
putreg32(I2C_CONSET_AA, priv->base + LPC17_I2C_CONSET_OFFSET);
|
2012-11-27 16:09:12 +01:00
|
|
|
break;
|
|
|
|
|
|
|
|
case 0x50:
|
|
|
|
if (priv->rdcnt < priv->msg.length)
|
|
|
|
{
|
2013-05-08 14:57:55 +02:00
|
|
|
priv->msg.buffer[priv->rdcnt] = getreg32(priv->base + LPC17_I2C_BUFR_OFFSET);
|
|
|
|
priv->rdcnt++;
|
2012-11-27 16:09:12 +01:00
|
|
|
}
|
|
|
|
|
2013-05-08 14:57:55 +02:00
|
|
|
if (priv->rdcnt >= priv->msg.length)
|
2012-11-27 16:09:12 +01:00
|
|
|
{
|
2013-05-08 14:57:55 +02:00
|
|
|
putreg32(I2C_CONCLR_AAC | I2C_CONCLR_SIC, priv->base + LPC17_I2C_CONCLR_OFFSET);
|
2012-11-27 16:09:12 +01:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 0x58:
|
|
|
|
i2c_stop(priv);
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
i2c_stop(priv);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return OK;
|
2012-09-13 20:32:24 +02:00
|
|
|
}
|
|
|
|
|
2015-10-03 15:25:03 +02:00
|
|
|
/****************************************************************************
|
2012-09-13 20:32:24 +02:00
|
|
|
* Public Functions
|
2015-10-03 15:25:03 +02:00
|
|
|
****************************************************************************/
|
2012-09-13 20:32:24 +02:00
|
|
|
|
2015-10-03 15:25:03 +02:00
|
|
|
/****************************************************************************
|
2012-09-13 20:32:24 +02:00
|
|
|
* Name: up_i2cinitialize
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Initialise an I2C device
|
|
|
|
*
|
2015-10-03 15:25:03 +02:00
|
|
|
****************************************************************************/
|
2012-09-13 20:32:24 +02:00
|
|
|
|
2016-01-30 15:35:46 +01:00
|
|
|
struct i2c_master_s *up_i2cinitialize(int port)
|
2012-09-13 20:32:24 +02:00
|
|
|
{
|
2012-11-27 16:09:12 +01:00
|
|
|
struct lpc17_i2cdev_s *priv;
|
|
|
|
irqstate_t flags;
|
|
|
|
uint32_t regval;
|
2012-09-13 20:32:24 +02:00
|
|
|
|
2012-11-27 16:09:12 +01:00
|
|
|
if (port > 2)
|
2012-09-13 20:32:24 +02:00
|
|
|
{
|
2012-11-27 16:09:12 +01:00
|
|
|
dbg("lpc I2C Only support 0,1,2\n");
|
|
|
|
return NULL;
|
2012-09-13 20:32:24 +02:00
|
|
|
}
|
|
|
|
|
2012-11-27 16:09:12 +01:00
|
|
|
flags = irqsave();
|
2012-09-13 20:32:24 +02:00
|
|
|
|
2015-10-07 19:39:06 +02:00
|
|
|
priv = &i2cdevices[port];
|
2012-09-13 20:32:24 +02:00
|
|
|
#ifdef CONFIG_LPC17_I2C0
|
2012-11-27 16:09:12 +01:00
|
|
|
if (port == 0)
|
2012-09-13 20:32:24 +02:00
|
|
|
{
|
2015-10-07 19:39:06 +02:00
|
|
|
priv = (FAR struct lpc17_i2cdev_s *)&i2cdevices[0];
|
2012-11-27 16:09:12 +01:00
|
|
|
priv->base = LPC17_I2C0_BASE;
|
|
|
|
priv->irqid = LPC17_IRQ_I2C0;
|
|
|
|
|
|
|
|
regval = getreg32(LPC17_SYSCON_PCONP);
|
|
|
|
regval |= SYSCON_PCONP_PCI2C0;
|
|
|
|
putreg32(regval, LPC17_SYSCON_PCONP);
|
|
|
|
|
|
|
|
regval = getreg32(LPC17_SYSCON_PCLKSEL0);
|
|
|
|
regval &= ~SYSCON_PCLKSEL0_I2C0_MASK;
|
|
|
|
regval |= (SYSCON_PCLKSEL_CCLK << SYSCON_PCLKSEL0_I2C0_SHIFT);
|
|
|
|
putreg32(regval, LPC17_SYSCON_PCLKSEL0);
|
2013-05-08 14:57:55 +02:00
|
|
|
|
2012-11-27 16:09:12 +01:00
|
|
|
lpc17_configgpio(GPIO_I2C0_SCL);
|
|
|
|
lpc17_configgpio(GPIO_I2C0_SDA);
|
2013-05-08 14:57:55 +02:00
|
|
|
|
2012-11-27 16:09:12 +01:00
|
|
|
putreg32(LPC17_CCLK/CONFIG_I2C0_FREQ/2, priv->base + LPC17_I2C_SCLH_OFFSET);
|
|
|
|
putreg32(LPC17_CCLK/CONFIG_I2C0_FREQ/2, priv->base + LPC17_I2C_SCLL_OFFSET);
|
2012-09-13 20:32:24 +02:00
|
|
|
}
|
2012-11-27 16:09:12 +01:00
|
|
|
else
|
2012-09-13 20:32:24 +02:00
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_LPC17_I2C1
|
2012-11-27 16:09:12 +01:00
|
|
|
if (port == 1)
|
2012-09-13 20:32:24 +02:00
|
|
|
{
|
2015-10-07 19:39:06 +02:00
|
|
|
priv = (FAR struct lpc17_i2cdev_s *)&i2cdevices[1];
|
2012-11-27 16:09:12 +01:00
|
|
|
priv->base = LPC17_I2C1_BASE;
|
|
|
|
priv->irqid = LPC17_IRQ_I2C1;
|
2012-09-13 20:32:24 +02:00
|
|
|
|
2012-11-27 16:09:12 +01:00
|
|
|
regval = getreg32(LPC17_SYSCON_PCONP);
|
|
|
|
regval |= SYSCON_PCONP_PCI2C1;
|
|
|
|
putreg32(regval, LPC17_SYSCON_PCONP);
|
2012-09-13 20:32:24 +02:00
|
|
|
|
2012-11-27 16:09:12 +01:00
|
|
|
regval = getreg32(LPC17_SYSCON_PCLKSEL1);
|
|
|
|
regval &= ~SYSCON_PCLKSEL1_I2C1_MASK;
|
|
|
|
regval |= (SYSCON_PCLKSEL_CCLK << SYSCON_PCLKSEL1_I2C1_SHIFT);
|
|
|
|
putreg32(regval, LPC17_SYSCON_PCLKSEL1);
|
2012-09-13 20:32:24 +02:00
|
|
|
|
2012-11-27 16:09:12 +01:00
|
|
|
lpc17_configgpio(GPIO_I2C1_SCL);
|
|
|
|
lpc17_configgpio(GPIO_I2C1_SDA);
|
2012-09-13 20:32:24 +02:00
|
|
|
|
2012-11-27 16:09:12 +01:00
|
|
|
putreg32(LPC17_CCLK/CONFIG_I2C1_FREQ/2, priv->base + LPC17_I2C_SCLH_OFFSET);
|
|
|
|
putreg32(LPC17_CCLK/CONFIG_I2C1_FREQ/2, priv->base + LPC17_I2C_SCLL_OFFSET);
|
2012-09-13 20:32:24 +02:00
|
|
|
}
|
2012-11-27 16:09:12 +01:00
|
|
|
else
|
2012-09-13 20:32:24 +02:00
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_LPC17_I2C2
|
2012-11-27 16:09:12 +01:00
|
|
|
if (port == 2)
|
2012-09-13 20:32:24 +02:00
|
|
|
{
|
2015-10-07 19:39:06 +02:00
|
|
|
priv = (FAR struct lpc17_i2cdev_s *)&i2cdevices[2];
|
2012-11-27 16:09:12 +01:00
|
|
|
priv->base = LPC17_I2C2_BASE;
|
|
|
|
priv->irqid = LPC17_IRQ_I2C2;
|
|
|
|
|
|
|
|
regval = getreg32(LPC17_SYSCON_PCONP);
|
|
|
|
regval |= SYSCON_PCONP_PCI2C2;
|
|
|
|
putreg32(regval, LPC17_SYSCON_PCONP);
|
|
|
|
|
|
|
|
regval = getreg32(LPC17_SYSCON_PCLKSEL1);
|
|
|
|
regval &= ~SYSCON_PCLKSEL1_I2C2_MASK;
|
|
|
|
regval |= (SYSCON_PCLKSEL_CCLK << SYSCON_PCLKSEL1_I2C2_SHIFT);
|
|
|
|
putreg32(regval, LPC17_SYSCON_PCLKSEL1);
|
2013-05-08 14:57:55 +02:00
|
|
|
|
2012-11-27 16:09:12 +01:00
|
|
|
lpc17_configgpio(GPIO_I2C2_SCL);
|
|
|
|
lpc17_configgpio(GPIO_I2C2_SDA);
|
2013-05-08 14:57:55 +02:00
|
|
|
|
2012-11-27 16:09:12 +01:00
|
|
|
putreg32(LPC17_CCLK/CONFIG_I2C2_FREQ/2, priv->base + LPC17_I2C_SCLH_OFFSET);
|
|
|
|
putreg32(LPC17_CCLK/CONFIG_I2C2_FREQ/2, priv->base + LPC17_I2C_SCLL_OFFSET);
|
2012-09-13 20:32:24 +02:00
|
|
|
}
|
2012-11-27 16:09:12 +01:00
|
|
|
else
|
2012-09-13 20:32:24 +02:00
|
|
|
#endif
|
|
|
|
{
|
2013-04-30 16:08:02 +02:00
|
|
|
irqrestore(flags);
|
2012-11-27 16:09:12 +01:00
|
|
|
return NULL;
|
2012-09-13 20:32:24 +02:00
|
|
|
}
|
|
|
|
|
2013-05-08 14:57:55 +02:00
|
|
|
putreg32(I2C_CONSET_I2EN, priv->base + LPC17_I2C_CONSET_OFFSET);
|
2012-09-13 20:32:24 +02:00
|
|
|
|
2012-11-27 16:09:12 +01:00
|
|
|
sem_init(&priv->mutex, 0, 1);
|
|
|
|
sem_init(&priv->wait, 0, 0);
|
2012-09-13 20:32:24 +02:00
|
|
|
|
2012-11-27 16:09:12 +01:00
|
|
|
/* Allocate a watchdog timer */
|
2012-09-13 20:32:24 +02:00
|
|
|
|
2012-11-27 16:09:12 +01:00
|
|
|
priv->timeout = wd_create();
|
|
|
|
DEBUGASSERT(priv->timeout != 0);
|
2012-09-13 20:32:24 +02:00
|
|
|
|
2012-11-27 16:09:12 +01:00
|
|
|
/* Attach Interrupt Handler */
|
2012-09-13 20:32:24 +02:00
|
|
|
|
2012-11-27 16:09:12 +01:00
|
|
|
irq_attach(priv->irqid, i2c_interrupt);
|
2012-09-13 20:32:24 +02:00
|
|
|
|
2012-11-27 16:09:12 +01:00
|
|
|
/* Enable Interrupt Handler */
|
|
|
|
|
|
|
|
up_enable_irq(priv->irqid);
|
|
|
|
|
|
|
|
/* Install our operations */
|
|
|
|
|
|
|
|
priv->dev.ops = &lpc17_i2c_ops;
|
2013-04-30 16:08:02 +02:00
|
|
|
|
|
|
|
irqrestore(flags);
|
2012-11-27 16:09:12 +01:00
|
|
|
return &priv->dev;
|
2012-09-13 20:32:24 +02:00
|
|
|
}
|
|
|
|
|
2015-10-03 15:25:03 +02:00
|
|
|
/****************************************************************************
|
2012-09-13 20:32:24 +02:00
|
|
|
* Name: up_i2cuninitalize
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Uninitialise an I2C device
|
|
|
|
*
|
2015-10-03 15:25:03 +02:00
|
|
|
****************************************************************************/
|
2012-09-13 20:32:24 +02:00
|
|
|
|
2016-01-30 15:35:46 +01:00
|
|
|
int up_i2cuninitialize(FAR struct i2c_master_s * dev)
|
2012-09-13 20:32:24 +02:00
|
|
|
{
|
2012-11-27 16:09:12 +01:00
|
|
|
struct lpc17_i2cdev_s *priv = (struct lpc17_i2cdev_s *) dev;
|
2013-05-08 14:57:55 +02:00
|
|
|
|
2012-11-27 16:09:12 +01:00
|
|
|
/* Disable I2C */
|
|
|
|
|
2013-05-08 14:57:55 +02:00
|
|
|
putreg32(I2C_CONCLRT_I2ENC, priv->base + LPC17_I2C_CONCLR_OFFSET);
|
2012-11-27 16:09:12 +01:00
|
|
|
|
|
|
|
/* Reset data structures */
|
|
|
|
|
|
|
|
sem_destroy(&priv->mutex);
|
|
|
|
sem_destroy(&priv->wait);
|
|
|
|
|
|
|
|
/* Free the watchdog timer */
|
|
|
|
|
|
|
|
wd_delete(priv->timeout);
|
|
|
|
priv->timeout = NULL;
|
|
|
|
|
|
|
|
/* Disable interrupts */
|
|
|
|
|
|
|
|
up_disable_irq(priv->irqid);
|
|
|
|
|
|
|
|
/* Detach Interrupt Handler */
|
|
|
|
|
|
|
|
irq_detach(priv->irqid);
|
|
|
|
return OK;
|
2012-09-13 20:32:24 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
#endif
|