2017-03-12 16:48:09 +01:00
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/****************************************************************************
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2021-03-08 22:39:04 +01:00
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* drivers/wireless/ieee80211/bcm43xxx/bcmf_sdio.c
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2017-03-12 16:48:09 +01:00
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*
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2021-05-27 11:12:43 +02:00
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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2017-03-12 16:48:09 +01:00
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*
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2021-05-27 11:12:43 +02:00
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* http://www.apache.org/licenses/LICENSE-2.0
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2017-03-12 16:48:09 +01:00
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*
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2021-05-27 11:12:43 +02:00
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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2017-03-12 16:48:09 +01:00
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/compiler.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <string.h>
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2022-06-18 19:02:21 +02:00
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#include <stdio.h>
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2017-03-12 16:48:09 +01:00
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#include <debug.h>
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#include <errno.h>
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2017-04-30 20:29:48 +02:00
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#include <assert.h>
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2017-03-12 16:48:09 +01:00
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#include <nuttx/kmalloc.h>
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#include <nuttx/arch.h>
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2017-04-13 20:31:39 +02:00
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#include <nuttx/kthread.h>
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2017-04-28 19:28:29 +02:00
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#include <nuttx/wdog.h>
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2022-01-04 09:28:19 +01:00
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#include <nuttx/sdio.h>
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2022-06-16 14:16:32 +02:00
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#include <nuttx/signal.h>
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2017-03-12 16:48:09 +01:00
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#include <nuttx/wireless/ieee80211/bcmf_sdio.h>
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#include <nuttx/wireless/ieee80211/bcmf_board.h>
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2017-03-26 17:42:53 +02:00
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#include "bcmf_sdio.h"
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#include "bcmf_core.h"
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2017-04-13 20:31:39 +02:00
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#include "bcmf_sdpcm.h"
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2017-04-30 20:29:48 +02:00
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#include "bcmf_utils.h"
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2017-03-20 22:40:25 +01:00
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2017-04-23 22:17:43 +02:00
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#include "bcmf_sdio_core.h"
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#include "bcmf_sdio_regs.h"
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2017-03-12 16:48:09 +01:00
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#define BCMF_DEVICE_RESET_DELAY_MS 10
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#define BCMF_DEVICE_START_DELAY_MS 10
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2017-03-14 21:06:19 +01:00
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#define BCMF_CLOCK_SETUP_DELAY_MS 500
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2017-04-13 20:31:39 +02:00
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#define BCMF_THREAD_NAME "bcmf"
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#define BCMF_THREAD_STACK_SIZE 2048
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2022-06-23 06:54:30 +02:00
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#define BCMF_LOWPOWER_TIMEOUT_TICK SEC2TICK(2)
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2017-04-13 20:31:39 +02:00
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2019-12-05 18:49:12 +01:00
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/* Chip-common registers */
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2018-04-26 16:10:23 +02:00
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2022-09-06 08:18:45 +02:00
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#define CHIPCOMMON_GPIO_CONTROL ((uint32_t)(0x18000000 + 0x6c))
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#define CHIPCOMMON_SR_CONTROL0 ((uint32_t)(0x18000000 + 0x504))
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#define CHIPCOMMON_SR_CONTROL1 ((uint32_t)(0x18000000 + 0x508))
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2018-04-26 16:10:23 +02:00
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2017-03-12 16:48:09 +01:00
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/****************************************************************************
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2019-12-05 18:49:12 +01:00
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* Public Data
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2017-03-12 16:48:09 +01:00
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****************************************************************************/
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2019-12-05 18:49:12 +01:00
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/* Supported chip configurations */
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2022-06-14 08:36:58 +02:00
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#ifdef CONFIG_IEEE80211_BROADCOM_BCM4301X
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2022-08-14 21:04:18 +02:00
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extern const struct bcmf_chip_data bcmf_4301x_config_data;
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2022-06-13 11:01:49 +02:00
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#endif
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2019-12-05 18:49:12 +01:00
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#ifdef CONFIG_IEEE80211_BROADCOM_BCM43362
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2022-08-14 21:04:18 +02:00
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extern const struct bcmf_chip_data bcmf_43362_config_data;
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2019-12-05 18:49:12 +01:00
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#endif
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#ifdef CONFIG_IEEE80211_BROADCOM_BCM43438
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2022-08-14 21:04:18 +02:00
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extern const struct bcmf_chip_data bcmf_43438_config_data;
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2019-12-05 18:49:12 +01:00
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#endif
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2021-12-29 15:02:46 +01:00
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#ifdef CONFIG_IEEE80211_BROADCOM_BCM43455
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2022-08-14 21:04:18 +02:00
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extern const struct bcmf_chip_data bcmf_43455_config_data;
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2021-12-29 15:02:46 +01:00
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#endif
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2019-12-05 18:49:12 +01:00
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2017-03-12 16:48:09 +01:00
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/****************************************************************************
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* Private Function Prototypes
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****************************************************************************/
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2017-04-23 22:17:43 +02:00
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static int bcmf_probe(FAR struct bcmf_sdio_dev_s *sbus);
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static int bcmf_hwinitialize(FAR struct bcmf_sdio_dev_s *sbus);
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static void bcmf_hwuninitialize(FAR struct bcmf_sdio_dev_s *sbus);
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static int bcmf_chipinitialize(FAR struct bcmf_sdio_dev_s *sbus);
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2017-03-20 22:40:25 +01:00
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2018-04-26 16:10:23 +02:00
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static int bcmf_oob_irq(FAR void *arg);
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2017-03-12 16:48:09 +01:00
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2020-05-17 16:47:40 +02:00
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static int bcmf_sdio_bus_sleep(FAR struct bcmf_sdio_dev_s *sbus,
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bool sleep);
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2017-04-13 20:31:39 +02:00
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static int bcmf_sdio_thread(int argc, char **argv);
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static int bcmf_sdio_find_block_size(unsigned int size);
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2018-04-26 16:10:23 +02:00
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static int bcmf_sdio_sr_init(FAR struct bcmf_sdio_dev_s *sbus);
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static bool brcm_chip_sr_capable(FAR struct bcmf_sdio_dev_s *sbus);
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2017-03-12 16:48:09 +01:00
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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2018-04-26 16:10:23 +02:00
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int bcmf_oob_irq(FAR void *arg)
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2017-03-20 22:40:25 +01:00
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{
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2018-04-26 16:10:23 +02:00
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FAR struct bcmf_sdio_dev_s *sbus = (FAR struct bcmf_sdio_dev_s *)arg;
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2022-06-23 06:54:30 +02:00
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int semcount;
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2017-04-13 20:31:39 +02:00
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2017-04-23 22:17:43 +02:00
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if (sbus->ready)
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2017-04-13 20:31:39 +02:00
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{
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2018-04-26 16:10:23 +02:00
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/* Signal bmcf thread */
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2017-05-04 02:20:57 +02:00
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2017-04-23 22:17:43 +02:00
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sbus->irq_pending = true;
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2022-06-23 06:54:30 +02:00
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nxsem_get_value(&sbus->thread_signal, &semcount);
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if (semcount < 1)
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{
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nxsem_post(&sbus->thread_signal);
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}
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2017-04-13 20:31:39 +02:00
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}
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2018-04-26 16:10:23 +02:00
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2017-04-13 20:31:39 +02:00
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return OK;
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}
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2022-06-23 06:54:30 +02:00
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int bcmf_sdio_kso_enable(FAR struct bcmf_sdio_dev_s *sbus, bool enable)
|
2017-04-13 20:31:39 +02:00
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{
|
2022-06-23 06:54:30 +02:00
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uint8_t value;
|
2017-04-13 20:31:39 +02:00
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int loops;
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2022-06-23 06:54:30 +02:00
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int ret;
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if (!sbus->ready)
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{
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return -EPERM;
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}
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if (sbus->kso_enable == enable)
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{
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return OK;
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}
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if (enable)
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{
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loops = 200;
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while (--loops > 0)
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{
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ret = bcmf_write_reg(sbus, 1, SBSDIO_FUNC1_SLEEPCSR,
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SBSDIO_FUNC1_SLEEPCSR_KSO_MASK |
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SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK);
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if (ret != OK)
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{
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wlerr("HT Avail request failed %d\n", ret);
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return ret;
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}
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nxsig_usleep(100 * 1000);
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ret = bcmf_read_reg(sbus, 1, SBSDIO_FUNC1_SLEEPCSR, &value);
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if (ret != OK)
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{
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return ret;
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}
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if ((value & (SBSDIO_FUNC1_SLEEPCSR_KSO_MASK |
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SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK)) != 0)
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{
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break;
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}
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}
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if (loops <= 0)
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{
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|
return -ETIMEDOUT;
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|
}
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}
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else
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{
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ret = bcmf_write_reg(sbus, 1, SBSDIO_FUNC1_SLEEPCSR, 0);
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}
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if (ret == OK)
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|
{
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sbus->kso_enable = enable;
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}
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return ret;
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}
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|
int bcmf_sdio_bus_sleep(FAR struct bcmf_sdio_dev_s *sbus, bool sleep)
|
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|
|
{
|
2017-04-13 20:31:39 +02:00
|
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uint8_t value;
|
2022-06-23 06:54:30 +02:00
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int loops;
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int ret;
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if (!sbus->ready)
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{
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return -EPERM;
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|
}
|
2017-04-13 20:31:39 +02:00
|
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|
2017-04-23 22:17:43 +02:00
|
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if (sbus->sleeping == sleep)
|
2017-04-13 20:31:39 +02:00
|
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{
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return OK;
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}
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|
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if (sleep)
|
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{
|
2017-04-23 22:17:43 +02:00
|
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|
sbus->sleeping = true;
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return bcmf_write_reg(sbus, 1, SBSDIO_FUNC1_CHIPCLKCSR, 0);
|
2017-04-13 20:31:39 +02:00
|
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|
}
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else
|
|
|
|
{
|
2018-04-26 16:10:23 +02:00
|
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|
loops = 200;
|
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|
while (--loops > 0)
|
2017-04-13 20:31:39 +02:00
|
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{
|
2018-04-26 16:10:23 +02:00
|
|
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/* Request HT Avail */
|
2017-05-04 02:30:40 +02:00
|
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|
2018-04-26 16:10:23 +02:00
|
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ret = bcmf_write_reg(sbus, 1, SBSDIO_FUNC1_CHIPCLKCSR,
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SBSDIO_HT_AVAIL_REQ | SBSDIO_FORCE_HT);
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|
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if (ret != OK)
|
|
|
|
{
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|
|
|
wlerr("HT Avail request failed %d\n", ret);
|
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|
|
return ret;
|
|
|
|
}
|
2017-05-04 02:30:40 +02:00
|
|
|
|
2018-04-26 16:10:23 +02:00
|
|
|
/* Wait for High Throughput clock */
|
|
|
|
|
2022-06-16 14:16:32 +02:00
|
|
|
nxsig_usleep(100 * 1000);
|
2017-04-23 22:17:43 +02:00
|
|
|
ret = bcmf_read_reg(sbus, 1, SBSDIO_FUNC1_CHIPCLKCSR, &value);
|
2017-05-04 02:30:40 +02:00
|
|
|
|
2017-04-13 20:31:39 +02:00
|
|
|
if (ret != OK)
|
|
|
|
{
|
|
|
|
return ret;
|
|
|
|
}
|
2017-05-04 02:30:40 +02:00
|
|
|
|
2017-04-13 20:31:39 +02:00
|
|
|
if (value & SBSDIO_HT_AVAIL)
|
|
|
|
{
|
|
|
|
/* High Throughput clock is ready */
|
2018-04-26 16:10:23 +02:00
|
|
|
|
2017-04-13 20:31:39 +02:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2017-05-04 02:30:40 +02:00
|
|
|
|
2017-04-13 20:31:39 +02:00
|
|
|
if (loops <= 0)
|
|
|
|
{
|
2017-04-24 00:24:47 +02:00
|
|
|
wlerr("HT clock not ready\n");
|
2017-04-13 20:31:39 +02:00
|
|
|
return -ETIMEDOUT;
|
|
|
|
}
|
|
|
|
|
2017-04-23 22:17:43 +02:00
|
|
|
sbus->sleeping = false;
|
2017-04-13 20:31:39 +02:00
|
|
|
}
|
2017-05-04 02:30:40 +02:00
|
|
|
|
2017-03-26 17:42:53 +02:00
|
|
|
return OK;
|
2017-03-12 16:48:09 +01:00
|
|
|
}
|
|
|
|
|
2022-06-23 06:54:30 +02:00
|
|
|
int bcmf_sdio_bus_lowpower(FAR struct bcmf_sdio_dev_s *sbus, bool enable)
|
|
|
|
{
|
|
|
|
return sbus->support_sr ? bcmf_sdio_kso_enable(sbus, !enable) :
|
|
|
|
bcmf_sdio_bus_sleep(sbus, enable);
|
|
|
|
}
|
|
|
|
|
2017-03-12 16:48:09 +01:00
|
|
|
/****************************************************************************
|
|
|
|
* Name: bcmf_probe
|
|
|
|
****************************************************************************/
|
|
|
|
|
2017-04-23 22:17:43 +02:00
|
|
|
int bcmf_probe(FAR struct bcmf_sdio_dev_s *sbus)
|
2017-03-12 16:48:09 +01:00
|
|
|
{
|
|
|
|
int ret;
|
2021-10-19 01:44:25 +02:00
|
|
|
#ifdef CONFIG_IEEE80211_BROADCOM_SDIO_EHS_MODE
|
|
|
|
uint8_t value;
|
|
|
|
#endif
|
2017-03-12 16:48:09 +01:00
|
|
|
|
2017-03-14 21:06:19 +01:00
|
|
|
/* Probe sdio card compatible device */
|
2017-03-12 16:48:09 +01:00
|
|
|
|
2017-04-23 22:17:43 +02:00
|
|
|
ret = sdio_probe(sbus->sdio_dev);
|
2017-03-14 21:06:19 +01:00
|
|
|
if (ret != OK)
|
|
|
|
{
|
|
|
|
goto exit_error;
|
|
|
|
}
|
2017-03-12 16:48:09 +01:00
|
|
|
|
2017-03-14 21:06:19 +01:00
|
|
|
/* Set FN0 / FN1 / FN2 default block size */
|
|
|
|
|
2017-04-23 22:17:43 +02:00
|
|
|
ret = sdio_set_blocksize(sbus->sdio_dev, 0, 64);
|
2017-03-14 21:06:19 +01:00
|
|
|
if (ret != OK)
|
|
|
|
{
|
|
|
|
goto exit_error;
|
|
|
|
}
|
2017-03-12 16:48:09 +01:00
|
|
|
|
2017-04-23 22:17:43 +02:00
|
|
|
ret = sdio_set_blocksize(sbus->sdio_dev, 1, 64);
|
2017-03-14 21:06:19 +01:00
|
|
|
if (ret != OK)
|
|
|
|
{
|
|
|
|
goto exit_error;
|
|
|
|
}
|
2017-03-12 16:48:09 +01:00
|
|
|
|
2017-04-23 22:17:43 +02:00
|
|
|
ret = sdio_set_blocksize(sbus->sdio_dev, 2, 64);
|
2017-03-12 16:48:09 +01:00
|
|
|
if (ret != OK)
|
|
|
|
{
|
|
|
|
goto exit_error;
|
|
|
|
}
|
|
|
|
|
2017-03-14 21:06:19 +01:00
|
|
|
/* Enable device interrupts for FN0, FN1 and FN2 */
|
2017-03-12 16:48:09 +01:00
|
|
|
|
2017-04-23 22:17:43 +02:00
|
|
|
ret = bcmf_write_reg(sbus, 0, SDIO_CCCR_INTEN,
|
2017-03-20 22:40:25 +01:00
|
|
|
(1 << 0) | (1 << 1) | (1 << 2));
|
2017-03-14 21:06:19 +01:00
|
|
|
if (ret != OK)
|
2017-03-12 16:48:09 +01:00
|
|
|
{
|
|
|
|
goto exit_error;
|
|
|
|
}
|
|
|
|
|
2021-10-19 01:44:25 +02:00
|
|
|
#ifdef CONFIG_IEEE80211_BROADCOM_SDIO_EHS_MODE
|
|
|
|
/* Default device clock speed is up to 25 MHz.
|
2020-04-08 14:45:35 +02:00
|
|
|
* We could set EHS bit to operate at a clock rate up to 50 MHz.
|
2018-04-26 16:10:23 +02:00
|
|
|
*/
|
2017-03-14 21:06:19 +01:00
|
|
|
|
2021-10-19 01:44:25 +02:00
|
|
|
ret = bcmf_read_reg(sbus, 0, SDIO_CCCR_HIGHSPEED, &value);
|
2021-11-03 05:46:15 +01:00
|
|
|
if (ret != OK)
|
|
|
|
{
|
|
|
|
goto exit_error;
|
|
|
|
}
|
2021-10-19 01:44:25 +02:00
|
|
|
|
2021-11-03 05:46:15 +01:00
|
|
|
if (value & SDIO_CCCR_HIGHSPEED_SHS)
|
2021-10-19 01:44:25 +02:00
|
|
|
{
|
|
|
|
/* If the chip confirms its High-Speed capability,
|
|
|
|
* enable the High-Speed mode.
|
|
|
|
*/
|
|
|
|
|
|
|
|
ret = bcmf_write_reg(sbus, 0, SDIO_CCCR_HIGHSPEED,
|
|
|
|
SDIO_CCCR_HIGHSPEED_EHS);
|
2021-11-03 05:46:15 +01:00
|
|
|
if (ret != OK)
|
|
|
|
{
|
|
|
|
goto exit_error;
|
|
|
|
}
|
2021-10-19 01:44:25 +02:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2022-02-03 04:53:01 +01:00
|
|
|
wlwarn("High-Speed mode is not supported by the chip!\n");
|
2021-10-19 01:44:25 +02:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2017-04-23 22:17:43 +02:00
|
|
|
SDIO_CLOCK(sbus->sdio_dev, CLOCK_SD_TRANSFER_4BIT);
|
2022-06-16 14:16:32 +02:00
|
|
|
nxsig_usleep(BCMF_CLOCK_SETUP_DELAY_MS * 1000);
|
2017-03-14 21:06:19 +01:00
|
|
|
|
2017-03-26 17:42:53 +02:00
|
|
|
/* Enable bus FN1 */
|
2017-03-14 21:06:19 +01:00
|
|
|
|
2017-04-23 22:17:43 +02:00
|
|
|
ret = sdio_enable_function(sbus->sdio_dev, 1);
|
2017-03-26 17:42:53 +02:00
|
|
|
if (ret != OK)
|
2017-03-14 21:06:19 +01:00
|
|
|
{
|
2017-03-26 17:42:53 +02:00
|
|
|
goto exit_error;
|
2017-03-14 21:06:19 +01:00
|
|
|
}
|
|
|
|
|
2017-03-12 16:48:09 +01:00
|
|
|
return OK;
|
|
|
|
|
|
|
|
exit_error:
|
2017-04-24 00:24:47 +02:00
|
|
|
wlerr("ERROR: failed to probe device %d\n", sbus->minor);
|
2017-03-12 16:48:09 +01:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2017-03-14 21:06:19 +01:00
|
|
|
/****************************************************************************
|
|
|
|
* Name: bcmf_businitialize
|
|
|
|
****************************************************************************/
|
|
|
|
|
2017-04-23 22:17:43 +02:00
|
|
|
int bcmf_businitialize(FAR struct bcmf_sdio_dev_s *sbus)
|
2017-03-14 21:06:19 +01:00
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
int loops;
|
2017-03-26 17:42:53 +02:00
|
|
|
uint8_t value;
|
2017-03-14 21:06:19 +01:00
|
|
|
|
|
|
|
/* Send Active Low-Power clock request */
|
|
|
|
|
2017-04-23 22:17:43 +02:00
|
|
|
ret = bcmf_write_reg(sbus, 1, SBSDIO_FUNC1_CHIPCLKCSR,
|
2018-04-26 16:10:23 +02:00
|
|
|
SBSDIO_FORCE_HW_CLKREQ_OFF |
|
|
|
|
SBSDIO_ALP_AVAIL_REQ |
|
|
|
|
SBSDIO_FORCE_ALP);
|
2017-03-14 21:06:19 +01:00
|
|
|
|
|
|
|
if (ret != OK)
|
|
|
|
{
|
2017-03-20 22:40:25 +01:00
|
|
|
return ret;
|
2017-03-14 21:06:19 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
loops = 10;
|
|
|
|
while (--loops > 0)
|
|
|
|
{
|
2022-06-16 14:16:32 +02:00
|
|
|
nxsig_usleep(10 * 1000);
|
2017-04-23 22:17:43 +02:00
|
|
|
ret = bcmf_read_reg(sbus, 1, SBSDIO_FUNC1_CHIPCLKCSR, &value);
|
2017-03-14 21:06:19 +01:00
|
|
|
|
|
|
|
if (ret != OK)
|
|
|
|
{
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2017-03-20 22:40:25 +01:00
|
|
|
if (value & SBSDIO_ALP_AVAIL)
|
2017-03-14 21:06:19 +01:00
|
|
|
{
|
|
|
|
/* Active Low-Power clock is ready */
|
2018-04-26 16:10:23 +02:00
|
|
|
|
2017-03-14 21:06:19 +01:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (loops <= 0)
|
|
|
|
{
|
2017-04-24 00:24:47 +02:00
|
|
|
wlerr("failed to enable ALP\n");
|
2017-03-14 21:06:19 +01:00
|
|
|
return -ETIMEDOUT;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Clear Active Low-Power clock request */
|
|
|
|
|
2017-04-23 22:17:43 +02:00
|
|
|
ret = bcmf_write_reg(sbus, 1, SBSDIO_FUNC1_CHIPCLKCSR, 0);
|
2017-03-14 21:06:19 +01:00
|
|
|
if (ret != OK)
|
|
|
|
{
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Disable pull-ups on SDIO cmd, d0-2 lines */
|
|
|
|
|
2017-04-23 22:17:43 +02:00
|
|
|
ret = bcmf_write_reg(sbus, 1, SBSDIO_FUNC1_SDIOPULLUP, 0);
|
2017-03-14 21:06:19 +01:00
|
|
|
if (ret != OK)
|
|
|
|
{
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2017-03-20 22:40:25 +01:00
|
|
|
/* Do chip specific initialization */
|
2017-03-14 21:06:19 +01:00
|
|
|
|
2017-04-23 22:17:43 +02:00
|
|
|
ret = bcmf_chipinitialize(sbus);
|
2017-03-20 22:40:25 +01:00
|
|
|
if (ret != OK)
|
|
|
|
{
|
|
|
|
return ret;
|
|
|
|
}
|
2017-03-14 21:06:19 +01:00
|
|
|
|
2017-03-26 17:42:53 +02:00
|
|
|
/* Upload firmware */
|
|
|
|
|
2017-04-23 22:17:43 +02:00
|
|
|
ret = bcmf_core_upload_firmware(sbus);
|
2017-03-26 17:42:53 +02:00
|
|
|
if (ret != OK)
|
|
|
|
{
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Enable FN2 (frame transfers) */
|
2017-03-14 21:06:19 +01:00
|
|
|
|
2017-04-23 22:17:43 +02:00
|
|
|
ret = sdio_enable_function(sbus->sdio_dev, 2);
|
2017-03-26 17:42:53 +02:00
|
|
|
if (ret != OK)
|
|
|
|
{
|
|
|
|
return ret;
|
|
|
|
}
|
2017-03-14 21:06:19 +01:00
|
|
|
|
2017-04-13 20:31:39 +02:00
|
|
|
return OK;
|
|
|
|
}
|
|
|
|
|
2017-04-23 22:17:43 +02:00
|
|
|
int bcmf_bus_setup_interrupts(FAR struct bcmf_sdio_dev_s *sbus)
|
2017-04-13 20:31:39 +02:00
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
2017-03-26 17:42:53 +02:00
|
|
|
/* Configure gpio interrupt pin */
|
2017-03-20 22:40:25 +01:00
|
|
|
|
2017-05-04 02:20:57 +02:00
|
|
|
bcmf_board_setup_oob_irq(sbus->minor, bcmf_oob_irq, (void *)sbus);
|
2017-03-20 22:40:25 +01:00
|
|
|
|
2017-03-26 17:42:53 +02:00
|
|
|
/* Enable function 2 interrupt */
|
2017-03-20 22:40:25 +01:00
|
|
|
|
2017-04-23 22:17:43 +02:00
|
|
|
ret = sdio_enable_interrupt(sbus->sdio_dev, 0);
|
2017-03-26 17:42:53 +02:00
|
|
|
if (ret != OK)
|
|
|
|
{
|
|
|
|
return ret;
|
|
|
|
}
|
2018-04-26 16:10:23 +02:00
|
|
|
|
2017-04-23 22:17:43 +02:00
|
|
|
ret = sdio_enable_interrupt(sbus->sdio_dev, 2);
|
2017-03-26 17:42:53 +02:00
|
|
|
if (ret != OK)
|
|
|
|
{
|
|
|
|
return ret;
|
|
|
|
}
|
2017-03-20 22:40:25 +01:00
|
|
|
|
2018-04-26 16:10:23 +02:00
|
|
|
#ifndef CONFIG_BCMFMAC_NO_OOB
|
2017-03-26 17:42:53 +02:00
|
|
|
/* Redirect, configure and enable io for out-of-band interrupt signal */
|
2017-03-20 22:40:25 +01:00
|
|
|
|
2017-04-23 22:17:43 +02:00
|
|
|
ret = bcmf_write_reg(sbus, 0, SDIO_CCCR_BRCM_SEPINT,
|
2018-04-26 16:10:23 +02:00
|
|
|
SDIO_SEPINT_MASK | SDIO_SEPINT_OE |
|
|
|
|
SDIO_SEPINT_ACT_HI);
|
2017-03-26 17:42:53 +02:00
|
|
|
if (ret != OK)
|
|
|
|
{
|
|
|
|
return ret;
|
|
|
|
}
|
2018-04-26 16:10:23 +02:00
|
|
|
#endif
|
2017-03-26 17:42:53 +02:00
|
|
|
|
2017-04-13 20:31:39 +02:00
|
|
|
/* Wake up chip to be sure function 2 is running */
|
2017-03-26 17:42:53 +02:00
|
|
|
|
2017-04-23 22:17:43 +02:00
|
|
|
ret = bcmf_sdio_bus_sleep(sbus, false);
|
2017-04-13 20:31:39 +02:00
|
|
|
if (ret != OK)
|
2017-03-26 17:42:53 +02:00
|
|
|
{
|
2017-04-13 20:31:39 +02:00
|
|
|
return ret;
|
2017-03-26 17:42:53 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/* FN2 successfully enabled, set core and enable interrupts */
|
|
|
|
|
2017-04-23 22:17:43 +02:00
|
|
|
bcmf_write_sbregw(sbus,
|
|
|
|
CORE_BUS_REG(sbus->chip->core_base[SDIOD_CORE_ID],
|
2017-03-26 17:42:53 +02:00
|
|
|
hostintmask), I_HMB_SW_MASK);
|
|
|
|
|
2017-04-23 22:17:43 +02:00
|
|
|
bcmf_write_sbregb(sbus,
|
|
|
|
CORE_BUS_REG(sbus->chip->core_base[SDIOD_CORE_ID],
|
2017-03-26 17:42:53 +02:00
|
|
|
funcintmask), 2);
|
|
|
|
|
2018-04-26 16:10:23 +02:00
|
|
|
/* Lower F2 Watermark to avoid DMA Hang in F2 when SD Clock is stopped. */
|
2017-03-14 21:06:19 +01:00
|
|
|
|
2018-04-26 16:10:23 +02:00
|
|
|
bcmf_write_reg(sbus, 1, SBSDIO_WATERMARK, 8);
|
2017-03-14 21:06:19 +01:00
|
|
|
return OK;
|
|
|
|
}
|
|
|
|
|
2017-03-12 16:48:09 +01:00
|
|
|
/****************************************************************************
|
|
|
|
* Name: bcmf_hwinitialize
|
|
|
|
****************************************************************************/
|
|
|
|
|
2017-04-23 22:17:43 +02:00
|
|
|
int bcmf_hwinitialize(FAR struct bcmf_sdio_dev_s *sbus)
|
2017-03-12 16:48:09 +01:00
|
|
|
{
|
2022-06-18 22:43:36 +02:00
|
|
|
/* Power device */
|
|
|
|
|
|
|
|
bcmf_board_power(sbus->minor, true);
|
|
|
|
|
2017-03-12 16:48:09 +01:00
|
|
|
/* Attach and prepare SDIO interrupts */
|
|
|
|
|
2017-04-23 22:17:43 +02:00
|
|
|
SDIO_ATTACH(sbus->sdio_dev);
|
2017-03-12 16:48:09 +01:00
|
|
|
|
|
|
|
/* Set ID mode clocking (<400KHz) */
|
|
|
|
|
2017-04-23 22:17:43 +02:00
|
|
|
SDIO_CLOCK(sbus->sdio_dev, CLOCK_IDMODE);
|
2017-03-12 16:48:09 +01:00
|
|
|
|
2022-06-18 22:43:36 +02:00
|
|
|
/* Reset device */
|
2017-03-12 16:48:09 +01:00
|
|
|
|
2017-04-23 22:17:43 +02:00
|
|
|
bcmf_board_reset(sbus->minor, true);
|
2022-06-16 14:16:32 +02:00
|
|
|
nxsig_usleep(BCMF_DEVICE_RESET_DELAY_MS * 1000);
|
2017-04-23 22:17:43 +02:00
|
|
|
bcmf_board_reset(sbus->minor, false);
|
2017-03-12 16:48:09 +01:00
|
|
|
|
|
|
|
/* Wait for device to start */
|
|
|
|
|
2022-06-16 14:16:32 +02:00
|
|
|
nxsig_usleep(BCMF_DEVICE_START_DELAY_MS * 1000);
|
2017-03-12 16:48:09 +01:00
|
|
|
|
|
|
|
return OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: bcmf_hwuninitialize
|
|
|
|
****************************************************************************/
|
|
|
|
|
2017-04-23 22:17:43 +02:00
|
|
|
void bcmf_hwuninitialize(FAR struct bcmf_sdio_dev_s *sbus)
|
2017-03-12 16:48:09 +01:00
|
|
|
{
|
|
|
|
/* Shutdown device */
|
|
|
|
|
2017-04-23 22:17:43 +02:00
|
|
|
bcmf_board_power(sbus->minor, false);
|
|
|
|
bcmf_board_reset(sbus->minor, true);
|
2017-03-12 16:48:09 +01:00
|
|
|
}
|
|
|
|
|
2017-04-13 20:31:39 +02:00
|
|
|
int bcmf_sdio_find_block_size(unsigned int size)
|
|
|
|
{
|
|
|
|
int ret = 0;
|
|
|
|
int size_copy = size;
|
2018-04-26 16:10:23 +02:00
|
|
|
|
2017-05-04 02:20:57 +02:00
|
|
|
while (size_copy)
|
|
|
|
{
|
|
|
|
size_copy >>= 1;
|
|
|
|
ret++;
|
2019-10-29 23:56:24 +01:00
|
|
|
}
|
2017-04-13 20:31:39 +02:00
|
|
|
|
2019-10-29 23:56:24 +01:00
|
|
|
if (size & (size - 1))
|
2017-04-13 20:31:39 +02:00
|
|
|
{
|
2017-05-04 02:20:57 +02:00
|
|
|
return 1 << ret;
|
2017-04-13 20:31:39 +02:00
|
|
|
}
|
2017-05-04 02:20:57 +02:00
|
|
|
|
|
|
|
return 1 << (ret - 1);
|
2017-04-13 20:31:39 +02:00
|
|
|
}
|
|
|
|
|
2018-04-26 16:10:23 +02:00
|
|
|
/* Init save-restore if the firmware support it: */
|
|
|
|
|
|
|
|
static int bcmf_sdio_sr_init(FAR struct bcmf_sdio_dev_s *sbus)
|
|
|
|
{
|
|
|
|
uint8_t data;
|
|
|
|
|
|
|
|
if (brcm_chip_sr_capable(sbus))
|
|
|
|
{
|
|
|
|
/* Configure WakeupCtrl register to set HtAvail request bit in
|
|
|
|
* chipClockCSR register after the sdiod core is powered on.
|
|
|
|
*/
|
|
|
|
|
|
|
|
bcmf_read_reg(sbus, 1, SBSDIO_FUNC1_WAKEUPCTRL, &data);
|
|
|
|
data |= SBSDIO_FUNC1_WCTRL_HTWAIT_MASK;
|
|
|
|
bcmf_write_reg(sbus, 1, SBSDIO_FUNC1_WAKEUPCTRL, data);
|
|
|
|
|
|
|
|
/* Set brcmCardCapability to noCmdDecode mode.
|
|
|
|
* It makes sdiod_aos to wakeup host for any activity of cmd line,
|
|
|
|
* even though module won't decode cmd or respond
|
|
|
|
*/
|
|
|
|
|
2019-10-29 23:56:24 +01:00
|
|
|
bcmf_write_reg(sbus, 0, SDIO_CCCR_BRCM_CARDCAP,
|
|
|
|
SDIO_CCCR_BRCM_CARDCAP_CMD_NODEC);
|
|
|
|
bcmf_write_reg(sbus, 1, SBSDIO_FUNC1_CHIPCLKCSR,
|
|
|
|
SBSDIO_FORCE_HT);
|
2018-04-26 16:10:23 +02:00
|
|
|
|
|
|
|
/* Enable KeepSdioOn (KSO) bit for normal operation */
|
|
|
|
|
2022-06-23 06:54:30 +02:00
|
|
|
bcmf_sdio_kso_enable(sbus, true);
|
|
|
|
|
|
|
|
sbus->support_sr = true;
|
2018-04-26 16:10:23 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
return OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Check if the firmware supports save restore feature.
|
|
|
|
* TODO: Add more chip specific logic, and move it to a new bcmf_chip.c file.
|
|
|
|
*/
|
|
|
|
|
|
|
|
static bool brcm_chip_sr_capable(FAR struct bcmf_sdio_dev_s *sbus)
|
|
|
|
{
|
|
|
|
uint32_t srctrl = 0;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
/* Check if fw initialized sr engine */
|
|
|
|
|
|
|
|
ret = bcmf_read_sbregw(sbus, CHIPCOMMON_SR_CONTROL1, &srctrl);
|
|
|
|
if (ret != OK)
|
|
|
|
{
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
return (srctrl != 0);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2022-08-14 21:04:18 +02:00
|
|
|
/****************************************************************************
|
|
|
|
* Name: bcmf_bus_sdio_initialize
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
static int bcmf_bus_sdio_initialize(FAR struct bcmf_dev_s *priv,
|
|
|
|
int minor, FAR struct sdio_dev_s *dev)
|
|
|
|
{
|
|
|
|
FAR struct bcmf_sdio_dev_s *sbus;
|
|
|
|
FAR char *argv[2];
|
|
|
|
char arg1[32];
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
/* Allocate sdio bus structure */
|
|
|
|
|
|
|
|
sbus = (FAR struct bcmf_sdio_dev_s *)kmm_malloc(sizeof(*sbus));
|
|
|
|
if (!sbus)
|
|
|
|
{
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Initialize sdio bus device structure */
|
|
|
|
|
|
|
|
memset(sbus, 0, sizeof(*sbus));
|
|
|
|
sbus->sdio_dev = dev;
|
|
|
|
sbus->minor = minor;
|
|
|
|
sbus->ready = false;
|
|
|
|
sbus->sleeping = true;
|
|
|
|
|
|
|
|
sbus->bus.txframe = bcmf_sdpcm_queue_frame;
|
|
|
|
sbus->bus.rxframe = bcmf_sdpcm_get_rx_frame;
|
|
|
|
sbus->bus.allocate_frame = bcmf_sdpcm_alloc_frame;
|
|
|
|
sbus->bus.free_frame = bcmf_sdpcm_free_frame;
|
|
|
|
sbus->bus.stop = NULL; /* TODO */
|
|
|
|
|
|
|
|
/* Init transmit frames queue */
|
|
|
|
|
2022-09-06 08:18:45 +02:00
|
|
|
nxmutex_init(&sbus->queue_lock);
|
2022-08-14 21:04:18 +02:00
|
|
|
list_initialize(&sbus->tx_queue);
|
|
|
|
list_initialize(&sbus->rx_queue);
|
|
|
|
|
|
|
|
/* Setup free buffer list */
|
|
|
|
|
|
|
|
bcmf_initialize_interface_frames();
|
|
|
|
|
|
|
|
/* Init thread semaphore */
|
|
|
|
|
2022-09-06 08:18:45 +02:00
|
|
|
nxsem_init(&sbus->thread_signal, 0, 0);
|
2022-08-14 21:04:18 +02:00
|
|
|
|
|
|
|
/* Configure hardware */
|
|
|
|
|
|
|
|
bcmf_board_initialize(sbus->minor);
|
|
|
|
|
|
|
|
/* Register sdio bus */
|
|
|
|
|
|
|
|
priv->bus = &sbus->bus;
|
|
|
|
|
|
|
|
/* Spawn bcmf daemon thread */
|
|
|
|
|
|
|
|
snprintf(arg1, sizeof(arg1), "%p", priv);
|
|
|
|
argv[0] = arg1;
|
|
|
|
argv[1] = NULL;
|
|
|
|
ret = kthread_create(BCMF_THREAD_NAME,
|
|
|
|
CONFIG_IEEE80211_BROADCOM_SCHED_PRIORITY,
|
|
|
|
BCMF_THREAD_STACK_SIZE, bcmf_sdio_thread,
|
|
|
|
argv);
|
|
|
|
if (ret <= 0)
|
|
|
|
{
|
|
|
|
wlerr("Cannot spawn bcmf thread\n");
|
|
|
|
ret = -EBADE;
|
|
|
|
goto exit_free_bus;
|
|
|
|
}
|
|
|
|
|
|
|
|
sbus->thread_id = (pid_t)ret;
|
|
|
|
|
|
|
|
return OK;
|
|
|
|
|
|
|
|
exit_free_bus:
|
|
|
|
kmm_free(sbus);
|
|
|
|
priv->bus = NULL;
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2017-03-12 16:48:09 +01:00
|
|
|
/****************************************************************************
|
|
|
|
* Public Functions
|
|
|
|
****************************************************************************/
|
|
|
|
|
2022-08-14 21:04:18 +02:00
|
|
|
/****************************************************************************
|
|
|
|
* Name: bcmf_sdio_initialize
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Initialize the drive with a SDIO connection.
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
int bcmf_sdio_initialize(int minor, FAR struct sdio_dev_s *dev)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
FAR struct bcmf_dev_s *priv;
|
|
|
|
|
|
|
|
wlinfo("minor: %d\n", minor);
|
|
|
|
|
|
|
|
priv = bcmf_allocate_device();
|
|
|
|
if (!priv)
|
|
|
|
{
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Init sdio bus */
|
|
|
|
|
|
|
|
ret = bcmf_bus_sdio_initialize(priv, minor, dev);
|
|
|
|
if (ret != OK)
|
|
|
|
{
|
|
|
|
ret = -EIO;
|
|
|
|
goto exit_free_device;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Bus initialized, register network driver */
|
|
|
|
|
|
|
|
return bcmf_driver_initialize(priv);
|
|
|
|
|
|
|
|
exit_free_device:
|
|
|
|
bcmf_free_device(priv);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2017-03-26 17:42:53 +02:00
|
|
|
/****************************************************************************
|
|
|
|
* Name: bcmf_transfer_bytes
|
|
|
|
****************************************************************************/
|
|
|
|
|
2017-04-23 22:17:43 +02:00
|
|
|
int bcmf_transfer_bytes(FAR struct bcmf_sdio_dev_s *sbus, bool write,
|
2017-03-26 17:42:53 +02:00
|
|
|
uint8_t function, uint32_t address,
|
|
|
|
uint8_t *buf, unsigned int len)
|
|
|
|
{
|
2017-04-13 20:31:39 +02:00
|
|
|
unsigned int blocklen;
|
|
|
|
unsigned int nblocks;
|
|
|
|
|
2022-06-23 06:54:30 +02:00
|
|
|
if (!sbus->ready)
|
|
|
|
{
|
|
|
|
return -EPERM;
|
|
|
|
}
|
|
|
|
|
2017-03-26 17:42:53 +02:00
|
|
|
/* Use rw_io_direct method if len is 1 */
|
|
|
|
|
2017-04-13 20:31:39 +02:00
|
|
|
if (len == 0)
|
|
|
|
{
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2017-03-26 17:42:53 +02:00
|
|
|
if (len == 1)
|
|
|
|
{
|
|
|
|
if (write)
|
|
|
|
{
|
2017-04-23 22:17:43 +02:00
|
|
|
return sdio_io_rw_direct(sbus->sdio_dev, write,
|
2017-03-26 17:42:53 +02:00
|
|
|
function, address, *buf, NULL);
|
|
|
|
}
|
2018-04-26 16:10:23 +02:00
|
|
|
|
2017-04-23 22:17:43 +02:00
|
|
|
return sdio_io_rw_direct(sbus->sdio_dev, write,
|
2017-03-26 17:42:53 +02:00
|
|
|
function, address, 0, buf);
|
|
|
|
}
|
|
|
|
|
2019-10-29 23:56:24 +01:00
|
|
|
/* Find best block settings for transfer */
|
2017-03-26 17:42:53 +02:00
|
|
|
|
2019-10-29 23:56:24 +01:00
|
|
|
if (len >= 64)
|
|
|
|
{
|
|
|
|
/* Use block mode */
|
2017-04-13 20:31:39 +02:00
|
|
|
|
2019-10-29 23:56:24 +01:00
|
|
|
blocklen = 64;
|
|
|
|
nblocks = (len + 63) / 64;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* Use byte mode */
|
2017-04-13 20:31:39 +02:00
|
|
|
|
2019-10-29 23:56:24 +01:00
|
|
|
blocklen = bcmf_sdio_find_block_size(len);
|
|
|
|
nblocks = 0;
|
|
|
|
}
|
2017-04-13 20:31:39 +02:00
|
|
|
|
2020-05-17 16:47:40 +02:00
|
|
|
return sdio_io_rw_extended(sbus->sdio_dev, write, function, address, true,
|
|
|
|
buf, blocklen, nblocks);
|
2017-03-26 17:42:53 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: bcmf_read_reg
|
|
|
|
****************************************************************************/
|
|
|
|
|
2017-04-23 22:17:43 +02:00
|
|
|
int bcmf_read_reg(FAR struct bcmf_sdio_dev_s *sbus, uint8_t function,
|
2017-03-26 17:42:53 +02:00
|
|
|
uint32_t address, uint8_t *reg)
|
|
|
|
{
|
|
|
|
*reg = 0;
|
2017-04-23 22:17:43 +02:00
|
|
|
return bcmf_transfer_bytes(sbus, false, function, address, reg, 1);
|
2017-03-26 17:42:53 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: bcmf_write_reg
|
|
|
|
****************************************************************************/
|
|
|
|
|
2017-04-23 22:17:43 +02:00
|
|
|
int bcmf_write_reg(FAR struct bcmf_sdio_dev_s *sbus, uint8_t function,
|
2017-03-26 17:42:53 +02:00
|
|
|
uint32_t address, uint8_t reg)
|
|
|
|
{
|
2017-04-23 22:17:43 +02:00
|
|
|
return bcmf_transfer_bytes(sbus, true, function, address, ®, 1);
|
2017-03-26 17:42:53 +02:00
|
|
|
}
|
|
|
|
|
2022-06-18 22:43:36 +02:00
|
|
|
/****************************************************************************
|
|
|
|
* Name: bcmf_bus_sdio_active
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
int bcmf_bus_sdio_active(FAR struct bcmf_dev_s *priv, bool active)
|
|
|
|
{
|
|
|
|
FAR struct bcmf_sdio_dev_s *sbus = (FAR struct bcmf_sdio_dev_s *)priv->bus;
|
|
|
|
int ret = OK;
|
|
|
|
|
|
|
|
if (!active)
|
|
|
|
{
|
|
|
|
goto exit_uninit_hw;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Initialize device hardware */
|
|
|
|
|
|
|
|
ret = bcmf_hwinitialize(sbus);
|
|
|
|
if (ret != OK)
|
|
|
|
{
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2022-06-23 06:54:30 +02:00
|
|
|
sbus->ready = active;
|
|
|
|
|
2022-06-18 22:43:36 +02:00
|
|
|
/* Probe device */
|
|
|
|
|
|
|
|
ret = bcmf_probe(sbus);
|
|
|
|
if (ret != OK)
|
|
|
|
{
|
|
|
|
goto exit_uninit_hw;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Initialize device bus */
|
|
|
|
|
|
|
|
ret = bcmf_businitialize(sbus);
|
|
|
|
if (ret != OK)
|
|
|
|
{
|
|
|
|
goto exit_uninit_hw;
|
|
|
|
}
|
|
|
|
|
|
|
|
nxsig_usleep(100 * 1000);
|
|
|
|
|
|
|
|
ret = bcmf_bus_setup_interrupts(sbus);
|
|
|
|
if (ret != OK)
|
|
|
|
{
|
|
|
|
goto exit_uninit_hw;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = bcmf_sdio_sr_init(sbus);
|
|
|
|
if (ret == OK)
|
|
|
|
{
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
exit_uninit_hw:
|
|
|
|
sbus->ready = false;
|
|
|
|
bcmf_hwuninitialize(sbus);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2017-04-23 22:17:43 +02:00
|
|
|
int bcmf_chipinitialize(FAR struct bcmf_sdio_dev_s *sbus)
|
2017-03-20 22:40:25 +01:00
|
|
|
{
|
|
|
|
uint32_t value = 0;
|
2018-04-26 16:10:23 +02:00
|
|
|
int chipid;
|
|
|
|
int ret;
|
2017-03-20 22:40:25 +01:00
|
|
|
|
2017-04-23 22:17:43 +02:00
|
|
|
ret = bcmf_read_sbregw(sbus, SI_ENUM_BASE, &value);
|
2017-03-20 22:40:25 +01:00
|
|
|
if (ret != OK)
|
|
|
|
{
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2018-04-26 16:10:23 +02:00
|
|
|
chipid = value & 0xffff;
|
|
|
|
sbus->cur_chip_id = chipid;
|
|
|
|
|
2017-03-20 22:40:25 +01:00
|
|
|
switch (chipid)
|
|
|
|
{
|
2022-06-14 08:36:58 +02:00
|
|
|
#ifdef CONFIG_IEEE80211_BROADCOM_BCM4301X
|
|
|
|
case SDIO_DEVICE_ID_BROADCOM_43012:
|
2022-06-13 11:01:49 +02:00
|
|
|
case SDIO_DEVICE_ID_BROADCOM_43013:
|
2022-06-14 08:36:58 +02:00
|
|
|
wlinfo("bcm%d chip detected\n", chipid);
|
2022-08-14 21:04:18 +02:00
|
|
|
sbus->chip = (struct bcmf_chip_data *)&bcmf_4301x_config_data;
|
2022-06-13 11:01:49 +02:00
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
|
2017-04-23 22:17:43 +02:00
|
|
|
#ifdef CONFIG_IEEE80211_BROADCOM_BCM43362
|
2017-03-26 17:42:53 +02:00
|
|
|
case SDIO_DEVICE_ID_BROADCOM_43362:
|
2017-04-24 00:24:47 +02:00
|
|
|
wlinfo("bcm43362 chip detected\n");
|
2022-08-14 21:04:18 +02:00
|
|
|
sbus->chip = (struct bcmf_chip_data *)&bcmf_43362_config_data;
|
2017-03-20 22:40:25 +01:00
|
|
|
break;
|
2017-04-23 22:17:43 +02:00
|
|
|
#endif
|
2018-04-26 16:10:23 +02:00
|
|
|
|
|
|
|
#ifdef CONFIG_IEEE80211_BROADCOM_BCM43438
|
|
|
|
case SDIO_DEVICE_ID_BROADCOM_43430:
|
|
|
|
wlinfo("bcm43438 chip detected\n");
|
2022-08-14 21:04:18 +02:00
|
|
|
sbus->chip = (struct bcmf_chip_data *)&bcmf_43438_config_data;
|
2018-04-26 16:10:23 +02:00
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
|
2021-12-29 15:02:46 +01:00
|
|
|
#ifdef CONFIG_IEEE80211_BROADCOM_BCM43455
|
|
|
|
case SDIO_DEVICE_ID_BROADCOM_43455:
|
|
|
|
wlinfo("bcm43455 chip detected\n");
|
2022-08-14 21:04:18 +02:00
|
|
|
sbus->chip = (struct bcmf_chip_data *)&bcmf_43455_config_data;
|
2021-12-29 15:02:46 +01:00
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
|
2017-03-20 22:40:25 +01:00
|
|
|
default:
|
2017-04-24 00:24:47 +02:00
|
|
|
wlerr("chip 0x%x is not supported\n", chipid);
|
2017-03-20 22:40:25 +01:00
|
|
|
return -ENODEV;
|
2018-04-26 16:10:23 +02:00
|
|
|
}
|
|
|
|
|
2017-03-20 22:40:25 +01:00
|
|
|
return OK;
|
|
|
|
}
|
2017-04-13 20:31:39 +02:00
|
|
|
|
|
|
|
int bcmf_sdio_thread(int argc, char **argv)
|
|
|
|
{
|
2022-06-18 19:02:21 +02:00
|
|
|
FAR struct bcmf_dev_s *priv = (FAR struct bcmf_dev_s *)
|
|
|
|
((uintptr_t)strtoul(argv[1], NULL, 16));
|
2017-05-04 02:20:57 +02:00
|
|
|
FAR struct bcmf_sdio_dev_s *sbus = (FAR struct bcmf_sdio_dev_s *)priv->bus;
|
2022-06-23 06:54:30 +02:00
|
|
|
uint32_t timeout = BCMF_LOWPOWER_TIMEOUT_TICK;
|
2017-10-04 23:22:27 +02:00
|
|
|
int ret;
|
2017-05-04 02:30:40 +02:00
|
|
|
|
2018-04-26 16:10:23 +02:00
|
|
|
wlinfo(" Enter\n");
|
2017-04-13 20:31:39 +02:00
|
|
|
|
|
|
|
/* FIXME wait for the chip to be ready to receive commands */
|
|
|
|
|
2022-06-16 14:16:32 +02:00
|
|
|
nxsig_usleep(50 * 1000);
|
2017-05-04 02:30:40 +02:00
|
|
|
|
2022-06-18 22:43:36 +02:00
|
|
|
while (true)
|
2017-04-13 20:31:39 +02:00
|
|
|
{
|
2022-06-23 06:54:30 +02:00
|
|
|
/* Check if RX/TX frames are available */
|
2017-04-13 20:31:39 +02:00
|
|
|
|
2022-06-23 06:54:30 +02:00
|
|
|
if ((sbus->intstatus & I_HMB_FRAME_IND) == 0 &&
|
2022-07-02 06:39:48 +02:00
|
|
|
list_is_empty(&sbus->tx_queue) &&
|
2022-06-23 06:54:30 +02:00
|
|
|
!sbus->irq_pending)
|
2017-04-13 20:31:39 +02:00
|
|
|
{
|
2022-06-23 06:54:30 +02:00
|
|
|
/* Wait for event (device interrupt or user request) */
|
2017-04-13 20:31:39 +02:00
|
|
|
|
2022-06-23 06:54:30 +02:00
|
|
|
if (timeout == UINT_MAX)
|
|
|
|
{
|
|
|
|
ret = nxsem_wait_uninterruptible(&sbus->thread_signal);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
ret = nxsem_tickwait_uninterruptible(&sbus->thread_signal,
|
|
|
|
timeout);
|
|
|
|
}
|
2017-04-13 20:31:39 +02:00
|
|
|
|
2022-06-23 06:54:30 +02:00
|
|
|
if (ret == -ETIMEDOUT)
|
|
|
|
{
|
|
|
|
/* Turn off clock request. */
|
|
|
|
|
|
|
|
timeout = UINT_MAX;
|
2023-03-22 13:19:06 +01:00
|
|
|
#ifdef CONFIG_IEEE80211_BROADCOM_LOWPOWER
|
2022-06-23 06:54:30 +02:00
|
|
|
bcmf_sdio_bus_lowpower(sbus, true);
|
2023-03-22 13:19:06 +01:00
|
|
|
#endif
|
2022-06-23 06:54:30 +02:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
else if (ret < 0)
|
|
|
|
{
|
|
|
|
wlerr("Error while waiting for semaphore\n");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
timeout = BCMF_LOWPOWER_TIMEOUT_TICK;
|
2017-04-13 20:31:39 +02:00
|
|
|
|
|
|
|
/* Wake up device */
|
|
|
|
|
2022-06-23 06:54:30 +02:00
|
|
|
bcmf_sdio_bus_lowpower(sbus, false);
|
2017-04-13 20:31:39 +02:00
|
|
|
|
2017-04-23 22:17:43 +02:00
|
|
|
if (sbus->irq_pending)
|
2017-04-13 20:31:39 +02:00
|
|
|
{
|
|
|
|
/* Woken up by interrupt, read device status */
|
|
|
|
|
2017-04-23 22:17:43 +02:00
|
|
|
sbus->irq_pending = false;
|
2017-04-13 20:31:39 +02:00
|
|
|
|
2020-05-17 16:47:40 +02:00
|
|
|
bcmf_read_sbregw(
|
|
|
|
sbus,
|
|
|
|
CORE_BUS_REG(sbus->chip->core_base[SDIOD_CORE_ID], intstatus),
|
|
|
|
&sbus->intstatus);
|
2017-04-13 20:31:39 +02:00
|
|
|
|
|
|
|
/* Clear interrupts */
|
|
|
|
|
2020-05-17 16:47:40 +02:00
|
|
|
bcmf_write_sbregw(
|
|
|
|
sbus,
|
|
|
|
CORE_BUS_REG(sbus->chip->core_base[SDIOD_CORE_ID], intstatus),
|
|
|
|
sbus->intstatus);
|
2017-04-13 20:31:39 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/* On frame indication, read available frames */
|
|
|
|
|
2017-04-23 22:17:43 +02:00
|
|
|
if (sbus->intstatus & I_HMB_FRAME_IND)
|
2017-04-13 20:31:39 +02:00
|
|
|
{
|
|
|
|
do
|
|
|
|
{
|
|
|
|
ret = bcmf_sdpcm_readframe(priv);
|
2017-05-04 02:20:57 +02:00
|
|
|
}
|
|
|
|
while (ret == OK);
|
2017-05-04 02:30:40 +02:00
|
|
|
|
2017-04-13 20:31:39 +02:00
|
|
|
if (ret == -ENODATA)
|
|
|
|
{
|
|
|
|
/* All frames processed */
|
2017-04-16 13:13:11 +02:00
|
|
|
|
2017-04-23 22:17:43 +02:00
|
|
|
sbus->intstatus &= ~I_HMB_FRAME_IND;
|
2017-04-13 20:31:39 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-04-16 11:28:08 +02:00
|
|
|
/* Send all queued frames */
|
|
|
|
|
|
|
|
do
|
|
|
|
{
|
|
|
|
ret = bcmf_sdpcm_sendframe(priv);
|
2017-05-04 02:20:57 +02:00
|
|
|
}
|
|
|
|
while (ret == OK);
|
2017-04-13 20:31:39 +02:00
|
|
|
}
|
2017-04-23 22:17:43 +02:00
|
|
|
|
2017-04-24 00:24:47 +02:00
|
|
|
wlinfo("Exit\n");
|
2017-04-23 22:17:43 +02:00
|
|
|
return 0;
|
2017-04-30 20:29:48 +02:00
|
|
|
}
|