2022-01-07 18:44:06 +01:00
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/****************************************************************************
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* arch/xtensa/include/esp32s3/irq.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* This file should never be included directly but, rather, only indirectly
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* through nuttx/irq.h
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*/
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#ifndef __ARCH_XTENSA_INCLUDE_ESP32S3_IRQ_H
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#define __ARCH_XTENSA_INCLUDE_ESP32S3_IRQ_H
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2022-03-18 21:35:05 +01:00
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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2022-01-07 18:44:06 +01:00
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#define ESP32S3_INT_PRIO_DEF 1
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2023-09-13 14:10:06 +02:00
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/* CPU interrupt flags:
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* These flags can be used to specify which interrupt qualities the
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* code calling esp32s3_setup_irq needs.
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*/
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#define ESP32S3_CPUINT_FLAG_LEVEL (1 << 0) /* Level-triggered interrupt */
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#define ESP32S3_CPUINT_FLAG_EDGE (1 << 1) /* Edge-triggered interrupt */
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#define ESP32S3_CPUINT_FLAG_SHARED (1 << 2) /* Interrupt can be shared between ISRs */
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#define ESP32S3_CPUINT_FLAG_IRAM (1 << 3) /* ISR can be called if cache is disabled */
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2022-01-07 18:44:06 +01:00
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/* Interrupt Matrix
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*
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* The Interrupt Matrix embedded in the ESP32-S3 independently allocates
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* peripheral interrupt sources to the two CPUs’ peripheral interrupts, to
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* timely inform CPU0 or CPU1 to process the interrupts once the interrupt
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* signals are generated.
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* Peripheral interrupt sources must be routed to CPU0/CPU1 peripheral
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* interrupts via this interrupt matrix due to the following considerations:
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* - ESP32-S3 has 99 peripheral interrupt sources. To map them to 32 CPU0
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* interrupts or 32 CPU1 interrupts, this matrix is needed.
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* - Through this matrix, one peripheral interrupt source can be mapped to
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* multiple CPU0 interrupts or CPU1 interrupts according to application
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* requirements.
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*
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* Features:
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* - Accept 99 peripheral interrupt sources as input.
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* - Generate 26 peripheral interrupts to CPU0 and 26 peripheral interrupts
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* to CPU1 as output. Note that the remaining 6 CPU0 interrupts and 6 CPU1
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* interrupts are internal interrupts.
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* - Support disabling CPU non-maskable interrupt (NMI) sources.
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* - Support querying current interrupt status of peripheral interrupt
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* sources.
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*/
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#define ESP32S3_PERIPH_MAC 0
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#define ESP32S3_PERIPH_MAC_NMI 1
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#define ESP32S3_PERIPH_PWR 2
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#define ESP32S3_PERIPH_BB 3
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#define ESP32S3_PERIPH_BT_MAC 4
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#define ESP32S3_PERIPH_BT_BB 5
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#define ESP32S3_PERIPH_BT_BB_NMI 6
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#define ESP32S3_PERIPH_RWBT 7
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#define ESP32S3_PERIPH_RWBLE 8
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#define ESP32S3_PERIPH_RWBT_NMI 9
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/* RESERVED interrupts: 12, 13, 15, 18, 19 */
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#define ESP32S3_PERIPH_RWBLE_NMI 10
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#define ESP32S3_PERIPH_I2C_MST 11
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#define ESP32S3_PERIPH_UHCI0 14
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#define ESP32S3_PERIPH_GPIO_INT_CPU 16
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#define ESP32S3_PERIPH_GPIO_INT_CPU_NMI 17
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/* RESERVED interrupts: 23 */
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#define ESP32S3_PERIPH_SPI1 20
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#define ESP32S3_PERIPH_SPI2 21
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#define ESP32S3_PERIPH_SPI3 22
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#define ESP32S3_PERIPH_LCD_CAM 24
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#define ESP32S3_PERIPH_I2S0 25
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#define ESP32S3_PERIPH_I2S1 26
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#define ESP32S3_PERIPH_UART0 27
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#define ESP32S3_PERIPH_UART1 28
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#define ESP32S3_PERIPH_UART2 29
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/* RESERVED interrupts: 33, 34 */
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#define ESP32S3_PERIPH_SDIO_HOST 30
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#define ESP32S3_PERIPH_PWM0 31
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#define ESP32S3_PERIPH_PWM1 32
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#define ESP32S3_PERIPH_LEDC 35
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#define ESP32S3_PERIPH_EFUSE 36
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2023-08-29 12:43:30 +02:00
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#define ESP32S3_PERIPH_TWAI 37
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2022-01-07 18:44:06 +01:00
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#define ESP32S3_PERIPH_USB 38
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#define ESP32S3_PERIPH_RTC_CORE 39
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/* RESERVED interrupts: 44, 45, 46, 47, 48, 49 */
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#define ESP32S3_PERIPH_RMT 40
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#define ESP32S3_PERIPH_PCNT 41
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#define ESP32S3_PERIPH_I2C_EXT0 42
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#define ESP32S3_PERIPH_I2C_EXT1 43
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#define ESP32S3_PERIPH_TG_T0_LEVEL 50
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#define ESP32S3_PERIPH_TG_T1_LEVEL 51
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#define ESP32S3_PERIPH_TG_WDT_LEVEL 52
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#define ESP32S3_PERIPH_TG1_T0_LEVEL 53
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#define ESP32S3_PERIPH_TG1_T1_LEVEL 54
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#define ESP32S3_PERIPH_TG1_WDT_LEVEL 55
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#define ESP32S3_PERIPH_CACHE_IA 56
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#define ESP32S3_PERIPH_SYSTIMER_TARGET0 57
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#define ESP32S3_PERIPH_SYSTIMER_TARGET1 58
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#define ESP32S3_PERIPH_SYSTIMER_TARGET2 59
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#define ESP32S3_PERIPH_SPI_MEM_REJECT 60
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#define ESP32S3_PERIPH_DCACHE_PRELOAD 61
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#define ESP32S3_PERIPH_ICACHE_PRELOAD 62
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#define ESP32S3_PERIPH_DCACHE_SYNC 63
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#define ESP32S3_PERIPH_ICACHE_SYNC 64
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#define ESP32S3_PERIPH_APB_ADC 65
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#define ESP32S3_PERIPH_DMA_IN_CH0 66
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#define ESP32S3_PERIPH_DMA_IN_CH1 67
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#define ESP32S3_PERIPH_DMA_IN_CH2 68
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#define ESP32S3_PERIPH_DMA_IN_CH3 69
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#define ESP32S3_PERIPH_DMA_IN_CH4 70
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#define ESP32S3_PERIPH_DMA_OUT_CH0 71
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#define ESP32S3_PERIPH_DMA_OUT_CH1 72
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#define ESP32S3_PERIPH_DMA_OUT_CH2 73
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#define ESP32S3_PERIPH_DMA_OUT_CH3 74
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#define ESP32S3_PERIPH_DMA_OUT_CH4 75
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#define ESP32S3_PERIPH_RSA 76
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#define ESP32S3_PERIPH_AES 77
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#define ESP32S3_PERIPH_SHA 78
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#define ESP32S3_PERIPH_INT_FROM_CPU0 79
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#define ESP32S3_PERIPH_INT_FROM_CPU1 80
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#define ESP32S3_PERIPH_INT_FROM_CPU2 81
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#define ESP32S3_PERIPH_INT_FROM_CPU3 82
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#define ESP32S3_PERIPH_ASSIST_DEBUG 83
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#define ESP32S3_PERIPH_DMA_APB_PMS_MONITOR_VIOLATE 84
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#define ESP32S3_PERIPH_CORE_0_IRAM0_PMS_MONITOR_VIOLATE 85
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#define ESP32S3_PERIPH_CORE_0_DRAM0_PMS_MONITOR_VIOLATE 86
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#define ESP32S3_PERIPH_CORE_0_PIF_PMS_MONITOR_VIOLATE 87
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#define ESP32S3_PERIPH_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE 88
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#define ESP32S3_PERIPH_CORE_1_IRAM0_PMS_MONITOR_VIOLATE 89
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#define ESP32S3_PERIPH_CORE_1_DRAM0_PMS_MONITOR_VIOLATE 90
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#define ESP32S3_PERIPH_CORE_1_PIF_PMS_MONITOR_VIOLATE 91
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#define ESP32S3_PERIPH_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE 92
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#define ESP32S3_PERIPH_BACKUP_PMS_VIOLATE 93
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#define ESP32S3_PERIPH_CACHE_CORE0_ACS 94
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#define ESP32S3_PERIPH_CACHE_CORE1_ACS 95
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#define ESP32S3_PERIPH_USB_DEVICE 96
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#define ESP32S3_PERIPH_PERIPH_BACKUP 97
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#define ESP32S3_PERIPH_DMA_EXTMEM_REJECT 98
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/* Total number of peripherals */
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#define ESP32S3_NPERIPHERALS 99
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/* Exceptions
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*
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* IRAM Offset Description
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* 0x0000 Windows
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* 0x0180 Level 2 interrupt
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* 0x01c0 Level 3 interrupt
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* 0x0200 Level 4 interrupt
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* 0x0240 Level 5 interrupt
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* 0x0280 Debug exception
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* 0x02c0 NMI exception
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* 0x0300 Kernel exception
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* 0x0340 User exception
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* 0x03c0 Double exception
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*/
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/* IRQ numbers for internal interrupts that are dispatched like peripheral
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* interrupts.
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*/
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#define XTENSA_IRQ_TIMER0 0 /* INTERRUPT, bit 6 */
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#define XTENSA_IRQ_TIMER1 1 /* INTERRUPT, bit 15 */
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#define XTENSA_IRQ_TIMER2 2 /* INTERRUPT, bit 16 */
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#define XTENSA_IRQ_SYSCALL 3 /* User interrupt w/EXCCAUSE=syscall */
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#define XTENSA_IRQ_SWINT 4 /* Software interrupt */
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2022-02-18 07:18:42 +01:00
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#define XTENSA_NIRQ_INTERNAL 5 /* Number of dispatch internal interrupts */
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#define XTENSA_IRQ_FIRSTPERIPH 5 /* First peripheral IRQ number */
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/* IRQ numbers for peripheral interrupts coming through the Interrupt
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* Matrix.
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*/
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#define ESP32S3_IRQ2PERIPH(irq) ((irq) - XTENSA_IRQ_FIRSTPERIPH)
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#define ESP32S3_PERIPH2IRQ(id) ((id) + XTENSA_IRQ_FIRSTPERIPH)
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#define ESP32S3_IRQ_MAC (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_MAC)
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#define ESP32S3_IRQ_MAC_NMI (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_MAC_NMI)
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#define ESP32S3_IRQ_PWR (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_PWR)
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#define ESP32S3_IRQ_BB (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_BB)
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#define ESP32S3_IRQ_BT_MAC (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_BT_MAC)
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#define ESP32S3_IRQ_BT_BB (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_BT_BB)
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#define ESP32S3_IRQ_BT_BB_NMI (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_BT_BB_NMI)
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#define ESP32S3_IRQ_RWBT (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_RWBT)
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#define ESP32S3_IRQ_RWBLE (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_RWBLE)
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#define ESP32S3_IRQ_RWBT_NMI (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_RWBT_NMI)
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#define ESP32S3_IRQ_RWBLE_NMI (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_RWBLE_NMI)
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#define ESP32S3_IRQ_I2C_MST (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_I2C_MST)
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#define ESP32S3_IRQ_UHCI0 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_UHCI0)
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#define ESP32S3_IRQ_GPIO_INT_CPU (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_GPIO_INT_CPU)
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#define ESP32S3_IRQ_GPIO_INT_CPU_NMI (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_GPIO_INT_CPU_NMI)
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#define ESP32S3_IRQ_SPI1 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_SPI1)
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#define ESP32S3_IRQ_SPI2 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_SPI2)
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#define ESP32S3_IRQ_SPI3 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_SPI3)
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#define ESP32S3_IRQ_LCD_CAM (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_LCD_CAM)
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#define ESP32S3_IRQ_I2S0 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_I2S0)
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#define ESP32S3_IRQ_I2S1 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_I2S1)
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#define ESP32S3_IRQ_UART0 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_UART0)
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#define ESP32S3_IRQ_UART1 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_UART1)
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#define ESP32S3_IRQ_UART2 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_UART2)
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#define ESP32S3_IRQ_SDIO_HOST (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_SDIO_HOST)
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#define ESP32S3_IRQ_PWM0 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_PWM0)
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#define ESP32S3_IRQ_SREG0 ESP32S3_IRQ_MAC
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#define ESP32S3_NIRQS_SREG0 32
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#define ESP32S3_IRQ_PWM1 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_PWM1)
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#define ESP32S3_IRQ_LEDC (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_LEDC)
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#define ESP32S3_IRQ_EFUSE (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_EFUSE)
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2023-08-29 12:43:30 +02:00
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#define ESP32S3_IRQ_TWAI (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_TWAI)
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2022-01-07 18:44:06 +01:00
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#define ESP32S3_IRQ_USB (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_USB)
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#define ESP32S3_IRQ_RTC_CORE (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_RTC_CORE)
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#define ESP32S3_IRQ_RMT (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_RMT)
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#define ESP32S3_IRQ_PCNT (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_PCNT)
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#define ESP32S3_IRQ_I2C_EXT0 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_I2C_EXT0)
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#define ESP32S3_IRQ_I2C_EXT1 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_I2C_EXT1)
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#define ESP32S3_IRQ_TG_T0_LEVEL (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_TG_T0_LEVEL)
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#define ESP32S3_IRQ_TG_T1_LEVEL (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_TG_T1_LEVEL)
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#define ESP32S3_IRQ_TG_WDT_LEVEL (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_TG_WDT_LEVEL)
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#define ESP32S3_IRQ_TG1_T0_LEVEL (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_TG1_T0_LEVEL)
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#define ESP32S3_IRQ_TG1_T1_LEVEL (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_TG1_T1_LEVEL)
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#define ESP32S3_IRQ_TG1_WDT_LEVEL (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_TG1_WDT_LEVEL)
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#define ESP32S3_IRQ_CACHE_IA (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_CACHE_IA)
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#define ESP32S3_IRQ_SYSTIMER_TARGET0 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_SYSTIMER_TARGET0)
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#define ESP32S3_IRQ_SYSTIMER_TARGET1 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_SYSTIMER_TARGET1)
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#define ESP32S3_IRQ_SYSTIMER_TARGET2 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_SYSTIMER_TARGET2)
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#define ESP32S3_IRQ_SPI_MEM_REJECT (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_SPI_MEM_REJECT)
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#define ESP32S3_IRQ_DCACHE_PRELOAD (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_DCACHE_PRELOAD)
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#define ESP32S3_IRQ_ICACHE_PRELOAD (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_ICACHE_PRELOAD)
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#define ESP32S3_IRQ_DCACHE_SYNC (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_DCACHE_SYNC)
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#define ESP32S3_IRQ_SREG1 ESP32S3_IRQ_PWM1
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#define ESP32S3_NIRQS_SREG1 32
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#define ESP32S3_IRQ_ICACHE_SYNC (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_ICACHE_SYNC)
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#define ESP32S3_IRQ_APB_ADC (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_APB_ADC)
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#define ESP32S3_IRQ_DMA_IN_CH0 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_DMA_IN_CH0)
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#define ESP32S3_IRQ_DMA_IN_CH1 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_DMA_IN_CH1)
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#define ESP32S3_IRQ_DMA_IN_CH2 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_DMA_IN_CH2)
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#define ESP32S3_IRQ_DMA_IN_CH3 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_DMA_IN_CH3)
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#define ESP32S3_IRQ_DMA_IN_CH4 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_DMA_IN_CH4)
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#define ESP32S3_IRQ_DMA_OUT_CH0 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_DMA_OUT_CH0)
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#define ESP32S3_IRQ_DMA_OUT_CH1 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_DMA_OUT_CH1)
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#define ESP32S3_IRQ_DMA_OUT_CH2 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_DMA_OUT_CH2)
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#define ESP32S3_IRQ_DMA_OUT_CH3 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_DMA_OUT_CH3)
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#define ESP32S3_IRQ_DMA_OUT_CH4 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_DMA_OUT_CH4)
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#define ESP32S3_IRQ_RSA (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_RSA)
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#define ESP32S3_IRQ_AES (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_AES)
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#define ESP32S3_IRQ_SHA (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_SHA)
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#define ESP32S3_IRQ_INT_FROM_CPU0 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_INT_FROM_CPU0)
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#define ESP32S3_IRQ_INT_FROM_CPU1 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_INT_FROM_CPU1)
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#define ESP32S3_IRQ_INT_FROM_CPU2 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_INT_FROM_CPU2)
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#define ESP32S3_IRQ_INT_FROM_CPU3 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_INT_FROM_CPU3)
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#define ESP32S3_IRQ_ASSIST_DEBUG (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_ASSIST_DEBUG)
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#define ESP32S3_IRQ_DMA_APB_PMS_MONITOR_VIOLATE (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_DMA_APB_PMS_MONITOR_VIOLATE)
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#define ESP32S3_IRQ_CORE_0_IRAM0_PMS_MONITOR_VIOLATE (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_CORE_0_IRAM0_PMS_MONITOR_VIOLATE)
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#define ESP32S3_IRQ_CORE_0_DRAM0_PMS_MONITOR_VIOLATE (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_CORE_0_DRAM0_PMS_MONITOR_VIOLATE)
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#define ESP32S3_IRQ_CORE_0_PIF_PMS_MONITOR_VIOLATE (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_CORE_0_PIF_PMS_MONITOR_VIOLATE)
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#define ESP32S3_IRQ_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE)
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#define ESP32S3_IRQ_CORE_1_IRAM0_PMS_MONITOR_VIOLATE (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_CORE_1_IRAM0_PMS_MONITOR_VIOLATE)
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#define ESP32S3_IRQ_CORE_1_DRAM0_PMS_MONITOR_VIOLATE (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_CORE_1_DRAM0_PMS_MONITOR_VIOLATE)
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#define ESP32S3_IRQ_CORE_1_PIF_PMS_MONITOR_VIOLATE (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_CORE_1_PIF_PMS_MONITOR_VIOLATE)
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#define ESP32S3_IRQ_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE)
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#define ESP32S3_IRQ_BACKUP_PMS_VIOLATE (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_BACKUP_PMS_VIOLATE)
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#define ESP32S3_IRQ_CACHE_CORE0_ACS (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_CACHE_CORE0_ACS)
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#define ESP32S3_IRQ_CACHE_CORE1_ACS (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_CACHE_CORE1_ACS)
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#define ESP32S3_IRQ_SREG2 ESP32S3_IRQ_ICACHE_SYNC
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#define ESP32S3_NIRQS_SREG2 32
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#define ESP32S3_IRQ_USB_DEVICE (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_USB_DEVICE)
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2023-02-07 20:34:59 +01:00
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#define ESP32S3_IRQ_PERIPH_BACKUP (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_PERIPH_BACKUP)
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2022-01-07 18:44:06 +01:00
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#define ESP32S3_IRQ_DMA_EXTMEM_REJECT (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_DMA_EXTMEM_REJECT)
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#define ESP32S3_IRQ_SREG3 ESP32S3_IRQ_USB_DEVICE
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#define ESP32S3_NIRQS_SREG3 3
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#define ESP32S3_NIRQ_PERIPH ESP32S3_NPERIPHERALS
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2022-03-18 21:35:05 +01:00
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#ifdef CONFIG_ESP32S3_GPIO_IRQ
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/* Second level GPIO interrupts. GPIO interrupts are decoded and dispatched
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* as a second level of decoding: The first level dispatches to the GPIO
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* interrupt handler. The second to the decoded GPIO interrupt handler.
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2022-01-07 18:44:06 +01:00
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*/
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2022-03-18 21:35:05 +01:00
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# define ESP32S3_NIRQ_GPIO 49
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# define ESP32S3_FIRST_GPIOIRQ (XTENSA_NIRQ_INTERNAL + ESP32S3_NIRQ_PERIPH)
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# define ESP32S3_LAST_GPIOIRQ (ESP32S3_FIRST_GPIOIRQ + ESP32S3_NIRQ_GPIO - 1)
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# define ESP32S3_PIN2IRQ(p) ((p) + ESP32S3_FIRST_GPIOIRQ)
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# define ESP32S3_IRQ2PIN(i) ((i) - ESP32S3_FIRST_GPIOIRQ)
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2022-01-07 18:44:06 +01:00
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#else
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2022-03-18 21:35:05 +01:00
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# define ESP32S3_NIRQ_GPIO 0
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2022-01-07 18:44:06 +01:00
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#endif
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2023-02-07 20:34:59 +01:00
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#ifdef CONFIG_ESP32S3_RTCIO_IRQ
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/* Second level RTC interrupts. RTC interrupts are decoded and dispatched
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* as a second level of decoding: The first level dispatches to the RTC
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* interrupt handler. The second to the decoded RTC interrupt handler.
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* A third level might be required to be implemented on the driver (e.g.
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* Touch pads)
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*/
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# define ESP32S3_NIRQ_RTCIO_PERIPH 21
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# define ESP32S3_NIRQ_RTCIO_TOUCHPAD 15
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# define ESP32S3_NIRQ_RTCIO (ESP32S3_NIRQ_RTCIO_PERIPH+ESP32S3_NIRQ_RTCIO_TOUCHPAD)
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# define ESP32S3_FIRST_RTCIOIRQ_PERIPH (XTENSA_NIRQ_INTERNAL+ESP32S3_NIRQ_PERIPH+ESP32S3_NIRQ_GPIO)
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# define ESP32S3_LAST_RTCIOIRQ_PERIPH (ESP32S3_FIRST_RTCIOIRQ_PERIPH+ESP32S3_NIRQ_RTCIO_PERIPH-1)
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# define ESP32S3_IRQ_RTC_SLP_WAKEUP (ESP32S3_FIRST_RTCIOIRQ_PERIPH+0)
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# define ESP32S3_IRQ_RTC_SLP_REJECT (ESP32S3_FIRST_RTCIOIRQ_PERIPH+1)
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# define ESP32S3_IRQ_RTC_SDIO_IDLE (ESP32S3_FIRST_RTCIOIRQ_PERIPH+2)
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# define ESP32S3_IRQ_RTC_WDT (ESP32S3_FIRST_RTCIOIRQ_PERIPH+3)
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# define ESP32S3_IRQ_RTC_TOUCH_SCAN_DONE (ESP32S3_FIRST_RTCIOIRQ_PERIPH+4)
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# define ESP32S3_IRQ_RTC_ULP_CP (ESP32S3_FIRST_RTCIOIRQ_PERIPH+5)
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# define ESP32S3_IRQ_RTC_TOUCH_DONE (ESP32S3_FIRST_RTCIOIRQ_PERIPH+6)
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# define ESP32S3_IRQ_RTC_TOUCH_ACTIVE (ESP32S3_FIRST_RTCIOIRQ_PERIPH+7)
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# define ESP32S3_IRQ_RTC_TOUCH_INACTIVE (ESP32S3_FIRST_RTCIOIRQ_PERIPH+8)
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# define ESP32S3_IRQ_RTC_BROWN_OUT (ESP32S3_FIRST_RTCIOIRQ_PERIPH+9)
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# define ESP32S3_IRQ_RTC_MAIN_TIMER (ESP32S3_FIRST_RTCIOIRQ_PERIPH+10)
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# define ESP32S3_IRQ_RTC_SARADC1 (ESP32S3_FIRST_RTCIOIRQ_PERIPH+11)
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# define ESP32S3_IRQ_RTC_TSENS (ESP32S3_FIRST_RTCIOIRQ_PERIPH+12)
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# define ESP32S3_IRQ_RTC_COCPU (ESP32S3_FIRST_RTCIOIRQ_PERIPH+13)
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# define ESP32S3_IRQ_RTC_SARADC2 (ESP32S3_FIRST_RTCIOIRQ_PERIPH+14)
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# define ESP32S3_IRQ_RTC_SWD (ESP32S3_FIRST_RTCIOIRQ_PERIPH+15)
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# define ESP32S3_IRQ_RTC_XTAL32K_DEAD (ESP32S3_FIRST_RTCIOIRQ_PERIPH+16)
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# define ESP32S3_IRQ_RTC_COCPU_TRAP (ESP32S3_FIRST_RTCIOIRQ_PERIPH+17)
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# define ESP32S3_IRQ_RTC_TOUCH_TIMEOUT (ESP32S3_FIRST_RTCIOIRQ_PERIPH+18)
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# define ESP32S3_IRQ_RTC_GLITCH_DET (ESP32S3_FIRST_RTCIOIRQ_PERIPH+19)
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# define ESP32S3_IRQ_RTC_TOUCH_APPROACH_LOOP_DONE (ESP32S3_FIRST_RTCIOIRQ_PERIPH+20)
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# define ESP32S3_FIRST_RTCIOIRQ_TOUCHPAD (ESP32S3_LAST_RTCIOIRQ_PERIPH+1)
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# define ESP32S3_LAST_RTCIOIRQ_TOUCHPAD (ESP32S3_FIRST_RTCIOIRQ_TOUCHPAD+ESP32S3_NIRQ_RTCIO_TOUCHPAD-1)
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# define ESP32S3_TOUCHPAD2IRQ(t) ((t) + ESP32S3_FIRST_RTCIOIRQ_TOUCHPAD)
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# define ESP32S3_IRQ2TOUCHPAD(i) ((i) - ESP32S3_FIRST_RTCIOIRQ_TOUCHPAD)
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#else
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# define ESP32S3_NIRQ_RTCIO 0
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#endif
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|
2022-01-07 18:44:06 +01:00
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/* Total number of interrupts */
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2023-02-07 20:34:59 +01:00
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#define NR_IRQS (XTENSA_NIRQ_INTERNAL + ESP32S3_NIRQ_PERIPH + ESP32S3_NIRQ_GPIO + ESP32S3_NIRQ_RTCIO)
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2022-01-07 18:44:06 +01:00
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/* Xtensa CPU Interrupts.
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*
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* Each of the two CPUs (PRO and APP) have 32 interrupts each, of which
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* 26 can be mapped to peripheral interrupts:
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*
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* Level triggered peripherals (21 total):
|
2023-09-13 14:10:06 +02:00
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* 0-5, 8-10, 12-13, 17-18 - Priority 1
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* 19-21 - Priority 2
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* 22-23, 27 - Priority 3
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* 24-25, 28, 30 - Priority 4
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* 26, 31 - Priority 5
|
2022-01-07 18:44:06 +01:00
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* NMI (1 total):
|
2023-09-13 14:10:06 +02:00
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* 14 - NMI
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2022-01-07 18:44:06 +01:00
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*
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* CPU peripheral interrupts can be a assigned to a CPU interrupt using the
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* PRO_*_MAP_REG or APP_*_MAP_REG. There are a pair of these registers for
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* each peripheral source. Multiple peripheral interrupt sources can be
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* mapped to the same CPU interrupt.
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*
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* The remaining, six, internal CPU interrupts are:
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*
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* 6 Timer0 - Priority 1
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* 7 Software - Priority 1
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* 11 Profiling - Priority 3
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* 15 Timer1 - Priority 3
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* 16 Timer2 - Priority 5
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* 29 Software - Priority 3
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*
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* A peripheral interrupt can be disabled
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*/
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#define ESP32S3_CPUINT_LEVELPERIPH_0 0
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#define ESP32S3_CPUINT_LEVELPERIPH_1 1
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#define ESP32S3_CPUINT_LEVELPERIPH_2 2
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#define ESP32S3_CPUINT_LEVELPERIPH_3 3
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#define ESP32S3_CPUINT_LEVELPERIPH_4 4
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#define ESP32S3_CPUINT_LEVELPERIPH_5 5
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#define ESP32S3_CPUINT_LEVELPERIPH_6 8
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#define ESP32S3_CPUINT_LEVELPERIPH_7 9
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#define ESP32S3_CPUINT_LEVELPERIPH_8 12
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#define ESP32S3_CPUINT_LEVELPERIPH_9 13
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#define ESP32S3_CPUINT_LEVELPERIPH_10 17
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#define ESP32S3_CPUINT_LEVELPERIPH_11 18
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#define ESP32S3_CPUINT_LEVELPERIPH_12 19
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#define ESP32S3_CPUINT_LEVELPERIPH_13 20
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#define ESP32S3_CPUINT_LEVELPERIPH_14 21
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#define ESP32S3_CPUINT_LEVELPERIPH_15 23
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#define ESP32S3_CPUINT_LEVELPERIPH_16 24
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#define ESP32S3_CPUINT_LEVELPERIPH_17 25
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#define ESP32S3_CPUINT_LEVELPERIPH_18 26
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#define ESP32S3_CPUINT_LEVELPERIPH_19 27
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#define ESP32S3_CPUINT_LEVELPERIPH_20 31
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#define ESP32S3_CPUINT_NLEVELPERIPHS 21
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2023-08-01 20:02:52 +02:00
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#define ESP32S3_CPUINT_LEVELSET 0xdffe373f
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2022-01-07 18:44:06 +01:00
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2023-08-01 20:02:52 +02:00
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#define ESP32S3_CPUINT_NEDGEPERIPHS 0
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2022-01-07 18:44:06 +01:00
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#define ESP32S3_CPUINT_NNMIPERIPHS 1
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#define ESP32S3_CPUINT_NMISET 0x00004000
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#define ESP32S3_CPUINT_MAC 0
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2023-08-08 15:20:15 +02:00
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#define ESP32S3_CPUINT_PWR 0
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2023-06-09 17:59:55 +02:00
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#define ESP32S3_CPUINT_RWBLE 5
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2022-01-07 18:44:06 +01:00
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#define ESP32S3_CPUINT_TIMER0 6
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#define ESP32S3_CPUINT_SOFTWARE0 7
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2023-06-09 17:59:55 +02:00
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#define ESP32S3_CPUINT_BT_BB 8
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2022-01-07 18:44:06 +01:00
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#define ESP32S3_CPUINT_PROFILING 11
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#define ESP32S3_CPUINT_TIMER1 15
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#define ESP32S3_CPUINT_TIMER2 16
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#define ESP32S3_CPUINT_SOFTWARE1 29
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#define ESP32S3_CPUINT_NINTERNAL 6
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#define ESP32S3_NCPUINTS 32
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#define ESP32S3_CPUINT_MAX (ESP32S3_NCPUINTS - 1)
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#define ESP32S3_CPUINT_PERIPHSET 0xdffe773f
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#define ESP32S3_CPUINT_INTERNALSET 0x200188c0
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/* Priority 1: 0-10, 12-13, 17-18 (15)
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* Priority 2: 19-21 (3)
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* Priority 3: 11, 15, 22-23, 27, 29 (6)
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* Priority 4: 24-25, 28, 30 (4)
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* Priority 5: 16, 26, 31 (3)
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* Priority NMI: 14 (1)
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*/
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#define ESP32S3_INTPRI1_MASK 0x000637ff
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#define ESP32S3_INTPRI2_MASK 0x00380000
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#define ESP32S3_INTPRI3_MASK 0x28c08800
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#define ESP32S3_INTPRI4_MASK 0x53000000
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#define ESP32S3_INTPRI5_MASK 0x84010000
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#define ESP32S3_INTNMI_MASK 0x00004000
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/****************************************************************************
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* Public Types
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****************************************************************************/
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#ifndef __ASSEMBLY__
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/****************************************************************************
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* Inline functions
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_XTENSA_INCLUDE_ESP32S3_IRQ_H */
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