2021-03-08 16:19:29 +01:00
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/****************************************************************************
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* arch/risc-v/src/c906/c906_irq_dispatch.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <assert.h>
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#include <nuttx/irq.h>
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#include <nuttx/arch.h>
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#include <nuttx/board.h>
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#include <arch/board/board.h>
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#include "riscv_internal.h"
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#include "group/group.h"
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2022-03-25 13:18:36 +01:00
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#define RV_IRQ_MASK 59
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2021-03-08 16:19:29 +01:00
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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2022-01-13 10:42:43 +01:00
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* riscv_dispatch_irq
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2021-03-08 16:19:29 +01:00
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****************************************************************************/
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2022-03-25 13:18:36 +01:00
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void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs)
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2021-03-08 16:19:29 +01:00
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{
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2022-03-25 13:18:36 +01:00
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int irq = (vector >> RV_IRQ_MASK) | (vector & 0xf);
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uintptr_t *mepc = regs;
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2021-03-08 16:19:29 +01:00
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/* Check if fault happened */
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2022-01-20 15:37:52 +01:00
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if (vector < RISCV_IRQ_ECALLU)
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2021-03-08 16:19:29 +01:00
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{
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2022-03-25 13:18:36 +01:00
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riscv_fault(irq, regs);
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2021-03-08 16:19:29 +01:00
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}
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/* Firstly, check if the irq is machine external interrupt */
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2022-01-20 15:37:52 +01:00
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if (RISCV_IRQ_MEXT == irq)
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2021-03-08 16:19:29 +01:00
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{
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uint32_t val = getreg32(C906_PLIC_MCLAIM);
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/* Add the value to nuttx irq which is offset to the mext */
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irq = val + C906_IRQ_PERI_START;
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}
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/* NOTE: In case of ecall, we need to adjust mepc in the context */
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2022-01-20 15:37:52 +01:00
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if (RISCV_IRQ_ECALLM == irq || RISCV_IRQ_ECALLU == irq)
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2021-03-08 16:19:29 +01:00
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{
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*mepc += 4;
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}
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/* Acknowledge the interrupt */
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2021-03-13 17:13:21 +01:00
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riscv_ack_irq(irq);
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2021-03-08 16:19:29 +01:00
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#ifdef CONFIG_SUPPRESS_INTERRUPTS
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PANIC();
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#else
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/* Current regs non-zero indicates that we are processing an interrupt;
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* CURRENT_REGS is also used to manage interrupt level context switches.
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*
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* Nested interrupts are not supported
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*/
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ASSERT(CURRENT_REGS == NULL);
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CURRENT_REGS = regs;
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/* MEXT means no interrupt */
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2022-01-20 15:37:52 +01:00
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if (RISCV_IRQ_MEXT != irq)
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2021-03-08 16:19:29 +01:00
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{
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/* Deliver the IRQ */
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irq_dispatch(irq, regs);
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}
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if (C906_IRQ_PERI_START <= irq)
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{
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/* Then write PLIC_CLAIM to clear pending in PLIC */
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putreg32(irq - C906_IRQ_PERI_START, C906_PLIC_MCLAIM);
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}
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/* Check for a context switch. If a context switch occurred, then
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* CURRENT_REGS will have a different value than it did on entry. If an
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* interrupt level context switch has occurred, then restore the floating
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* point state and the establish the correct address environment before
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* returning from the interrupt.
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*/
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if (regs != CURRENT_REGS)
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{
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#ifdef CONFIG_ARCH_ADDRENV
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/* Make sure that the address environment for the previously
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* running task is closed down gracefully (data caches dump,
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* MMU flushed) and set up the address environment for the new
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* thread at the head of the ready-to-run list.
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*/
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group_addrenv(NULL);
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#endif
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}
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2022-03-25 07:46:19 +01:00
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#endif /* CONFIG_SUPPRESS_INTERRUPTS */
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2021-03-08 16:19:29 +01:00
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/* If a context switch occurred while processing the interrupt then
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* CURRENT_REGS may have change value. If we return any value different
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* from the input regs, then the lower level will know that a context
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* switch occurred during interrupt processing.
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*/
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2022-03-25 13:18:36 +01:00
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regs = (uintptr_t *)CURRENT_REGS;
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2021-03-08 16:19:29 +01:00
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CURRENT_REGS = NULL;
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return regs;
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}
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