2010-01-23 04:05:05 +01:00
|
|
|
/****************************************************************************
|
2013-06-02 21:57:22 +02:00
|
|
|
* arch/arm/src/sam34/sam_gpioirq.c
|
2010-01-23 04:05:05 +01:00
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|
*
|
2021-03-24 09:34:53 +01:00
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* Licensed to the Apache Software Foundation (ASF) under one or more
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|
* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
|
2010-01-23 04:05:05 +01:00
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*
|
2021-03-24 09:34:53 +01:00
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* http://www.apache.org/licenses/LICENSE-2.0
|
2010-01-23 04:05:05 +01:00
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*
|
2021-03-24 09:34:53 +01:00
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
|
2010-01-23 04:05:05 +01:00
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*
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****************************************************************************/
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/****************************************************************************
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|
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* Included Files
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|
****************************************************************************/
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|
#include <nuttx/config.h>
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#include <stdint.h>
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#include <assert.h>
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#include <errno.h>
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#include <debug.h>
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#include <nuttx/init.h>
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#include <nuttx/arch.h>
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#include <arch/irq.h>
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#include <arch/board/board.h>
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2020-05-01 03:20:29 +02:00
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#include "arm_arch.h"
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#include "arm_internal.h"
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2010-01-23 04:05:05 +01:00
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|
2013-06-02 21:04:40 +02:00
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#include "sam_gpio.h"
|
2013-06-13 01:32:00 +02:00
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|
#include "sam_periphclks.h"
|
2019-05-25 15:37:39 +02:00
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|
#include "hardware/sam_pmc.h"
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2010-01-23 04:05:05 +01:00
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2014-10-24 18:55:52 +02:00
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#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
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|
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defined(CONFIG_ARCH_CHIP_SAM3A)
|
2019-05-25 15:37:39 +02:00
|
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|
# include "hardware/sam3u_pio.h"
|
2014-10-24 18:55:52 +02:00
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|
#elif defined(CONFIG_ARCH_CHIP_SAM4E)
|
2019-05-25 15:37:39 +02:00
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# include "hardware/sam4e_pio.h"
|
2014-10-24 18:55:52 +02:00
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|
#elif defined(CONFIG_ARCH_CHIP_SAM4CM) || defined(CONFIG_ARCH_CHIP_SAM4S)
|
2019-05-25 15:37:39 +02:00
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|
# include "hardware/sam4s_pio.h"
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2014-10-24 18:55:52 +02:00
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#else
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# error Unrecognized SAM architecture
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#endif
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|
2014-03-23 22:51:08 +01:00
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#ifdef CONFIG_SAM34_GPIO_IRQ
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2010-01-23 04:05:05 +01:00
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/****************************************************************************
|
2015-04-08 16:04:12 +02:00
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* Pre-processor Definitions
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2010-01-23 04:05:05 +01:00
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****************************************************************************/
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
|
2013-06-02 21:04:40 +02:00
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* Name: sam_gpiobase
|
2010-01-23 04:05:05 +01:00
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*
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* Description:
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* Return the base address of the GPIO register set
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*
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|
****************************************************************************/
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|
2013-07-02 21:52:09 +02:00
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static inline uint32_t sam_gpiobase(gpio_pinset_t pinset)
|
2010-01-23 04:05:05 +01:00
|
|
|
{
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int port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
|
2013-06-02 18:33:57 +02:00
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|
return SAM_PION_BASE(port >> GPIO_PORT_SHIFT);
|
2010-01-23 04:05:05 +01:00
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|
}
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/****************************************************************************
|
2013-06-02 21:04:40 +02:00
|
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* Name: sam_gpiopin
|
2010-01-23 04:05:05 +01:00
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*
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|
* Description:
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* Returun the base address of the GPIO register set
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*
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|
****************************************************************************/
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|
2013-07-02 21:52:09 +02:00
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static inline int sam_gpiopin(gpio_pinset_t pinset)
|
2010-01-23 04:05:05 +01:00
|
|
|
{
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|
|
return 1 << ((pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT);
|
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|
|
}
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|
/****************************************************************************
|
2013-06-02 21:04:40 +02:00
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* Name: sam_irqbase
|
2010-01-23 04:05:05 +01:00
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*
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* Description:
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* Return gpio information associated with this IRQ
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*
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|
****************************************************************************/
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|
2013-06-02 21:04:40 +02:00
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static int sam_irqbase(int irq, uint32_t *base, int *pin)
|
2010-01-23 04:05:05 +01:00
|
|
|
{
|
2013-06-02 18:33:57 +02:00
|
|
|
if (irq >= SAM_IRQ_NIRQS)
|
2010-01-23 04:05:05 +01:00
|
|
|
{
|
2014-03-23 22:51:08 +01:00
|
|
|
#ifdef CONFIG_SAM34_GPIOA_IRQ
|
2013-06-02 18:33:57 +02:00
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if (irq <= SAM_IRQ_PA31)
|
2010-01-23 04:05:05 +01:00
|
|
|
{
|
2013-06-02 18:33:57 +02:00
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|
*base = SAM_PIOA_BASE;
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*pin = irq - SAM_IRQ_PA0;
|
2010-01-23 04:05:05 +01:00
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return OK;
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|
}
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|
#endif
|
2021-03-24 09:35:15 +01:00
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|
2014-03-23 22:51:08 +01:00
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|
#ifdef CONFIG_SAM34_GPIOB_IRQ
|
2013-06-02 18:33:57 +02:00
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|
if (irq <= SAM_IRQ_PB31)
|
2010-01-23 04:05:05 +01:00
|
|
|
{
|
2013-06-02 18:33:57 +02:00
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|
*base = SAM_PIOB_BASE;
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*pin = irq - SAM_IRQ_PB0;
|
2010-01-23 04:05:05 +01:00
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|
return OK;
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|
}
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|
#endif
|
2021-03-24 09:35:15 +01:00
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|
2014-03-23 22:51:08 +01:00
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|
#ifdef CONFIG_SAM34_GPIOC_IRQ
|
2013-06-02 18:33:57 +02:00
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if (irq <= SAM_IRQ_PC31)
|
2010-01-23 04:05:05 +01:00
|
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|
{
|
2013-06-02 18:33:57 +02:00
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|
*base = SAM_PIOC_BASE;
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|
*pin = irq - SAM_IRQ_PC0;
|
2010-01-23 04:05:05 +01:00
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|
return OK;
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|
}
|
2013-07-03 16:12:45 +02:00
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|
#endif
|
2021-03-24 09:35:15 +01:00
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|
2014-03-23 22:51:08 +01:00
|
|
|
#ifdef CONFIG_SAM34_GPIOD_IRQ
|
2013-07-03 16:12:45 +02:00
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|
if (irq <= SAM_IRQ_PD31)
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|
|
{
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|
*base = SAM_PIOD_BASE;
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*pin = irq - SAM_IRQ_PD0;
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|
return OK;
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}
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|
#endif
|
2021-03-24 09:35:15 +01:00
|
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|
2014-03-23 22:51:08 +01:00
|
|
|
#ifdef CONFIG_SAM34_GPIOE_IRQ
|
2013-07-03 16:12:45 +02:00
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if (irq <= SAM_IRQ_PE31)
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|
|
{
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|
*base = SAM_PIOE_BASE;
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|
*pin = irq - SAM_IRQ_PE0;
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|
return OK;
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|
}
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|
#endif
|
2021-03-24 09:35:15 +01:00
|
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|
2014-03-23 22:51:08 +01:00
|
|
|
#ifdef CONFIG_SAM34_GPIOF_IRQ
|
2013-07-03 16:12:45 +02:00
|
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|
if (irq <= SAM_IRQ_PF31)
|
|
|
|
{
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|
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|
*base = SAM_PIOF_BASE;
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|
|
*pin = irq - SAM_IRQ_PF0;
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|
return OK;
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|
|
|
}
|
2010-01-23 04:05:05 +01:00
|
|
|
#endif
|
|
|
|
}
|
2013-07-03 16:12:45 +02:00
|
|
|
|
2010-01-23 04:05:05 +01:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
2013-07-06 01:15:54 +02:00
|
|
|
* Name: sam_gpioa/b/cinterrupt
|
2010-01-23 04:05:05 +01:00
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Receive GPIOA/B/C interrupts
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2013-07-06 01:15:54 +02:00
|
|
|
static int sam_gpiointerrupt(uint32_t base, int irq0, void *context)
|
2010-01-23 04:05:05 +01:00
|
|
|
{
|
|
|
|
uint32_t pending;
|
|
|
|
uint32_t bit;
|
|
|
|
int irq;
|
|
|
|
|
2021-03-24 09:35:15 +01:00
|
|
|
pending = getreg32(base + SAM_PIO_ISR_OFFSET) &
|
|
|
|
getreg32(base + SAM_PIO_IMR_OFFSET);
|
2010-01-23 04:05:05 +01:00
|
|
|
for (bit = 1, irq = irq0; pending != 0; bit <<= 1, irq++)
|
|
|
|
{
|
|
|
|
if ((pending & bit) != 0)
|
|
|
|
{
|
|
|
|
/* Re-deliver the IRQ (recurses! We got here from irq_dispatch!) */
|
|
|
|
|
|
|
|
irq_dispatch(irq, context);
|
|
|
|
|
|
|
|
/* Remove this from the set of pending interrupts */
|
|
|
|
|
|
|
|
pending &= ~bit;
|
|
|
|
}
|
|
|
|
}
|
2021-03-24 09:35:15 +01:00
|
|
|
|
2010-01-23 04:05:05 +01:00
|
|
|
return OK;
|
|
|
|
}
|
|
|
|
|
2014-03-23 22:51:08 +01:00
|
|
|
#ifdef CONFIG_SAM34_GPIOA_IRQ
|
2017-02-27 13:27:56 +01:00
|
|
|
static int sam_gpioainterrupt(int irq, void *context, FAR void *arg)
|
2010-01-23 04:05:05 +01:00
|
|
|
{
|
2013-07-06 01:15:54 +02:00
|
|
|
return sam_gpiointerrupt(SAM_PIOA_BASE, SAM_IRQ_PA0, context);
|
2010-01-23 04:05:05 +01:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2014-03-23 22:51:08 +01:00
|
|
|
#ifdef CONFIG_SAM34_GPIOB_IRQ
|
2017-02-27 13:27:56 +01:00
|
|
|
static int sam_gpiobinterrupt(int irq, void *context, FAR void *arg)
|
2010-01-23 04:05:05 +01:00
|
|
|
{
|
2013-07-06 01:15:54 +02:00
|
|
|
return sam_gpiointerrupt(SAM_PIOB_BASE, SAM_IRQ_PB0, context);
|
2010-01-23 04:05:05 +01:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2014-03-23 22:51:08 +01:00
|
|
|
#ifdef CONFIG_SAM34_GPIOC_IRQ
|
2017-02-27 13:27:56 +01:00
|
|
|
static int sam_gpiocinterrupt(int irq, void *context, FAR void *arg)
|
2010-01-23 04:05:05 +01:00
|
|
|
{
|
2013-07-06 01:15:54 +02:00
|
|
|
return sam_gpiointerrupt(SAM_PIOC_BASE, SAM_IRQ_PC0, context);
|
2010-01-23 04:05:05 +01:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2014-03-23 22:51:08 +01:00
|
|
|
#ifdef CONFIG_SAM34_GPIOD_IRQ
|
2017-02-27 13:27:56 +01:00
|
|
|
static int sam_gpiodinterrupt(int irq, void *context, FAR void *arg)
|
2013-07-02 21:52:09 +02:00
|
|
|
{
|
2013-07-06 01:15:54 +02:00
|
|
|
return sam_gpiointerrupt(SAM_PIOD_BASE, SAM_IRQ_PD0, context);
|
2013-07-02 21:52:09 +02:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2014-03-23 22:51:08 +01:00
|
|
|
#ifdef CONFIG_SAM34_GPIOE_IRQ
|
2017-02-27 13:27:56 +01:00
|
|
|
static int sam_gpioeinterrupt(int irq, void *context, FAR void *arg)
|
2013-07-02 21:52:09 +02:00
|
|
|
{
|
2013-07-06 01:15:54 +02:00
|
|
|
return sam_gpiointerrupt(SAM_PIOE_BASE, SAM_IRQ_PE0, context);
|
2013-07-02 21:52:09 +02:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2014-03-23 22:51:08 +01:00
|
|
|
#ifdef CONFIG_SAM34_GPIOF_IRQ
|
2017-02-27 13:27:56 +01:00
|
|
|
static int sam_gpiofinterrupt(int irq, void *context, FAR void *arg)
|
2013-07-02 21:52:09 +02:00
|
|
|
{
|
2013-07-06 01:15:54 +02:00
|
|
|
return sam_gpiointerrupt(SAM_PIOF_BASE, SAM_IRQ_PF0, context);
|
2013-07-02 21:52:09 +02:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2010-01-23 04:05:05 +01:00
|
|
|
/****************************************************************************
|
|
|
|
* Public Functions
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
/****************************************************************************
|
2013-06-02 21:04:40 +02:00
|
|
|
* Name: sam_gpioirqinitialize
|
2010-01-23 04:05:05 +01:00
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Initialize logic to support a second level of interrupt decoding for
|
|
|
|
* GPIO pins.
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2013-06-02 21:04:40 +02:00
|
|
|
void sam_gpioirqinitialize(void)
|
2010-01-23 04:05:05 +01:00
|
|
|
{
|
|
|
|
/* Configure GPIOA interrupts */
|
|
|
|
|
2014-03-23 22:51:08 +01:00
|
|
|
#ifdef CONFIG_SAM34_GPIOA_IRQ
|
2010-01-23 04:05:05 +01:00
|
|
|
/* Enable GPIOA clocking */
|
|
|
|
|
2013-06-08 21:50:42 +02:00
|
|
|
sam_pioa_enableclk();
|
2010-01-23 04:05:05 +01:00
|
|
|
|
|
|
|
/* Clear and disable all GPIOA interrupts */
|
|
|
|
|
2020-01-02 17:49:34 +01:00
|
|
|
getreg32(SAM_PIOA_ISR);
|
2013-06-02 18:33:57 +02:00
|
|
|
putreg32(0xffffffff, SAM_PIOA_IDR);
|
2010-01-23 04:05:05 +01:00
|
|
|
|
|
|
|
/* Attach and enable the GPIOA IRQ */
|
|
|
|
|
2020-01-02 17:49:34 +01:00
|
|
|
irq_attach(SAM_IRQ_PIOA, sam_gpioainterrupt, NULL);
|
2013-06-02 18:33:57 +02:00
|
|
|
up_enable_irq(SAM_IRQ_PIOA);
|
2010-01-23 04:05:05 +01:00
|
|
|
#endif
|
|
|
|
|
|
|
|
/* Configure GPIOB interrupts */
|
|
|
|
|
2014-03-23 22:51:08 +01:00
|
|
|
#ifdef CONFIG_SAM34_GPIOB_IRQ
|
2010-01-23 04:05:05 +01:00
|
|
|
/* Enable GPIOB clocking */
|
|
|
|
|
2013-06-08 21:50:42 +02:00
|
|
|
sam_piob_enableclk();
|
2010-01-23 04:05:05 +01:00
|
|
|
|
|
|
|
/* Clear and disable all GPIOB interrupts */
|
|
|
|
|
2020-01-02 17:49:34 +01:00
|
|
|
getreg32(SAM_PIOB_ISR);
|
2013-06-02 18:33:57 +02:00
|
|
|
putreg32(0xffffffff, SAM_PIOB_IDR);
|
2010-01-23 04:05:05 +01:00
|
|
|
|
|
|
|
/* Attach and enable the GPIOB IRQ */
|
|
|
|
|
2020-01-02 17:49:34 +01:00
|
|
|
irq_attach(SAM_IRQ_PIOB, sam_gpiobinterrupt, NULL);
|
2013-06-02 18:33:57 +02:00
|
|
|
up_enable_irq(SAM_IRQ_PIOB);
|
2010-01-23 04:05:05 +01:00
|
|
|
#endif
|
|
|
|
|
|
|
|
/* Configure GPIOC interrupts */
|
|
|
|
|
2014-03-23 22:51:08 +01:00
|
|
|
#ifdef CONFIG_SAM34_GPIOC_IRQ
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2010-01-23 04:05:05 +01:00
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/* Enable GPIOC clocking */
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2013-06-08 21:50:42 +02:00
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sam_pioc_enableclk();
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2010-01-23 04:05:05 +01:00
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/* Clear and disable all GPIOC interrupts */
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2020-01-02 17:49:34 +01:00
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getreg32(SAM_PIOC_ISR);
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2013-06-02 18:33:57 +02:00
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putreg32(0xffffffff, SAM_PIOC_IDR);
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2010-01-23 04:05:05 +01:00
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/* Attach and enable the GPIOC IRQ */
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2020-01-02 17:49:34 +01:00
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irq_attach(SAM_IRQ_PIOC, sam_gpiocinterrupt, NULL);
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2013-06-02 18:33:57 +02:00
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up_enable_irq(SAM_IRQ_PIOC);
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2010-01-23 04:05:05 +01:00
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#endif
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2013-07-02 21:52:09 +02:00
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/* Configure GPIOD interrupts */
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2014-03-23 22:51:08 +01:00
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#ifdef CONFIG_SAM34_GPIOD_IRQ
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2013-07-02 21:52:09 +02:00
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/* Enable GPIOD clocking */
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sam_piod_enableclk();
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/* Clear and disable all GPIOD interrupts */
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2020-01-02 17:49:34 +01:00
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getreg32(SAM_PIOD_ISR);
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2013-07-02 21:52:09 +02:00
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putreg32(0xffffffff, SAM_PIOD_IDR);
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/* Attach and enable the GPIOC IRQ */
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2020-01-02 17:49:34 +01:00
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irq_attach(SAM_IRQ_PIOD, sam_gpiodinterrupt, NULL);
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2013-07-02 21:52:09 +02:00
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up_enable_irq(SAM_IRQ_PIOD);
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#endif
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/* Configure GPIOE interrupts */
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2014-03-23 22:51:08 +01:00
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#ifdef CONFIG_SAM34_GPIOE_IRQ
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2013-07-02 21:52:09 +02:00
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/* Enable GPIOE clocking */
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sam_pioe_enableclk();
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/* Clear and disable all GPIOE interrupts */
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2020-01-02 17:49:34 +01:00
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getreg32(SAM_PIOE_ISR);
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2013-07-02 21:52:09 +02:00
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putreg32(0xffffffff, SAM_PIOE_IDR);
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/* Attach and enable the GPIOE IRQ */
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2020-01-02 17:49:34 +01:00
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irq_attach(SAM_IRQ_PIOE, sam_gpioeinterrupt, NULL);
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2013-07-02 21:52:09 +02:00
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up_enable_irq(SAM_IRQ_PIOE);
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#endif
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/* Configure GPIOF interrupts */
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2014-03-23 22:51:08 +01:00
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#ifdef CONFIG_SAM34_GPIOF_IRQ
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2013-07-02 21:52:09 +02:00
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/* Enable GPIOF clocking */
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sam_piof_enableclk();
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/* Clear and disable all GPIOF interrupts */
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2020-01-02 17:49:34 +01:00
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getreg32(SAM_PIOF_ISR);
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2013-07-02 21:52:09 +02:00
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putreg32(0xffffffff, SAM_PIOF_IDR);
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/* Attach and enable the GPIOF IRQ */
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2020-01-02 17:49:34 +01:00
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irq_attach(SAM_IRQ_PIOF, sam_gpiofinterrupt, NULL);
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2013-07-02 21:52:09 +02:00
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up_enable_irq(SAM_IRQ_PIOF);
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#endif
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2010-01-23 04:05:05 +01:00
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}
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2021-03-24 09:35:15 +01:00
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/****************************************************************************
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2013-06-02 21:04:40 +02:00
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* Name: sam_gpioirq
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2010-01-23 04:05:05 +01:00
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*
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* Description:
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* Configure an interrupt for the specified GPIO pin.
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*
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2021-03-24 09:35:15 +01:00
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****************************************************************************/
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2010-01-23 04:05:05 +01:00
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2013-07-02 21:52:09 +02:00
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void sam_gpioirq(gpio_pinset_t pinset)
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2010-01-23 04:05:05 +01:00
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{
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2013-06-02 21:04:40 +02:00
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uint32_t base = sam_gpiobase(pinset);
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int pin = sam_gpiopin(pinset);
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2013-06-02 18:33:57 +02:00
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2015-10-06 01:13:53 +02:00
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/* Are any additional interrupt modes selected? */
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2010-01-23 04:05:05 +01:00
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2015-10-06 01:13:53 +02:00
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if ((pinset & _GIO_INT_AIM) != 0)
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{
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/* Yes.. Enable additional interrupt mode */
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2013-06-02 18:33:57 +02:00
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2015-10-06 01:13:53 +02:00
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putreg32(pin, base + SAM_PIO_AIMER_OFFSET);
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2010-01-23 04:05:05 +01:00
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2015-10-06 01:13:53 +02:00
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/* Level or edge detected interrupt? */
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2010-01-23 04:05:05 +01:00
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2015-10-06 01:13:53 +02:00
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if ((pinset & _GPIO_INT_LEVEL) != 0)
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{
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putreg32(pin, base + SAM_PIO_LSR_OFFSET); /* Level */
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}
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else
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{
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putreg32(pin, base + SAM_PIO_ESR_OFFSET); /* Edge */
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}
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2010-01-23 04:05:05 +01:00
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/* High level/rising edge or low level /falling edge? */
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2015-10-06 01:13:53 +02:00
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if ((pinset & _GPIO_INT_RH) != 0)
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{
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putreg32(pin, base + SAM_PIO_REHLSR_OFFSET); /* High level/Rising edge */
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}
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else
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{
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putreg32(pin, base + SAM_PIO_FELLSR_OFFSET); /* Low level/Falling edge */
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}
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}
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else
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{
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/* No.. Disable additional interrupt mode */
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putreg32(pin, base + SAM_PIO_AIMDR_OFFSET);
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}
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2010-01-23 04:05:05 +01:00
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}
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2021-03-24 09:35:15 +01:00
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/****************************************************************************
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2013-06-02 21:04:40 +02:00
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* Name: sam_gpioirqenable
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2010-01-23 04:05:05 +01:00
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*
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* Description:
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* Enable the interrupt for specified GPIO IRQ
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*
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2021-03-24 09:35:15 +01:00
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****************************************************************************/
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2010-01-23 04:05:05 +01:00
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2013-06-02 21:04:40 +02:00
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void sam_gpioirqenable(int irq)
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2010-01-23 04:05:05 +01:00
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{
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uint32_t base;
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int pin;
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2013-06-02 21:04:40 +02:00
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if (sam_irqbase(irq, &base, &pin) == OK)
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2010-01-23 04:05:05 +01:00
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{
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2015-10-07 19:39:06 +02:00
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/* Clear (all) pending interrupts and enable this pin interrupt */
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2010-01-23 04:05:05 +01:00
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2021-03-24 09:35:15 +01:00
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/* (void)getreg32(base + SAM_PIO_ISR_OFFSET); */
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2015-10-07 19:39:06 +02:00
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putreg32((1 << pin), base + SAM_PIO_IER_OFFSET);
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2010-01-23 04:05:05 +01:00
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}
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}
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2021-03-24 09:35:15 +01:00
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/****************************************************************************
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2013-06-02 21:04:40 +02:00
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* Name: sam_gpioirqdisable
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2010-01-23 04:05:05 +01:00
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*
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* Description:
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* Disable the interrupt for specified GPIO IRQ
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*
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2021-03-24 09:35:15 +01:00
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****************************************************************************/
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2010-01-23 04:05:05 +01:00
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2013-06-02 21:04:40 +02:00
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void sam_gpioirqdisable(int irq)
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2010-01-23 04:05:05 +01:00
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{
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uint32_t base;
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int pin;
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2013-06-02 21:04:40 +02:00
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if (sam_irqbase(irq, &base, &pin) == OK)
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2010-01-23 04:05:05 +01:00
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{
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2015-10-07 19:39:06 +02:00
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/* Disable this pin interrupt */
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2010-01-23 04:05:05 +01:00
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2015-10-07 19:39:06 +02:00
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putreg32((1 << pin), base + SAM_PIO_IDR_OFFSET);
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2010-01-23 04:05:05 +01:00
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}
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}
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2014-03-23 22:51:08 +01:00
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#endif /* CONFIG_SAM34_GPIO_IRQ */
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