2013-06-06 02:48:30 +02:00
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/****************************************************************************
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* arch/avr/src/sam34/sam4l_periphclks.c
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* This file is derived from nuttx/arch/avr/src/at32uc3/at32uc3_clkinit.c
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <arch/irq.h>
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#include <arch/board/board.h>
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#include "up_arch.h"
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#include "up_internal.h"
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#include "chip/sam4l_pm.h"
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#include "sam4l_periphclks.h"
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/****************************************************************************
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2013-06-07 22:59:33 +02:00
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* Pre-processor Definitions
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2013-06-06 02:48:30 +02:00
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****************************************************************************/
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2013-06-08 17:21:20 +02:00
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/* USBC source clock selection */
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#ifdef CONFIG_SAM34_USBC
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# if defined(BOARD_USBC_SRC_OSC0)
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# define SAM_USBC_GCLK_SOURCE SCIF_GCCTRL_OSCSEL_OSC0
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# elif defined(BOARD_USBC_SRC_PLL0)
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# define SAM_USBC_GCLK_SOURCE SCIF_GCCTRL_OSCSEL_PLL0
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# elif defined(BOARD_USBC_SRC_DFLL)
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# define SAM_USBC_GCLK_SOURCE SCIF_GCCTRL_OSCSEL_DFLL0
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# elif defined(BOARD_USBC_SRC_GCLKIN0)
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# define SAM_USBC_GCLK_SOURCE SCIF_GCCTRL_OSCSEL_GCLKIN0
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# else
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# error No USBC GCLK7 source clock defined
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# endif
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#endif
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2013-06-06 02:48:30 +02:00
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/****************************************************************************
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* Private Types
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****************************************************************************/
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/****************************************************************************
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* Private Function Prototypes
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****************************************************************************/
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/****************************************************************************
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* Global Variables
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****************************************************************************/
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/****************************************************************************
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* Private Variables
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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2013-06-07 22:59:33 +02:00
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/****************************************************************************
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* Name: sam_init_cpumask
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*
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* Description:
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* Called during boot to enable clocking on selected peripherals in the
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* CPU mask register.
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*
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****************************************************************************/
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static inline void sam_init_cpumask(void)
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{
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uint32_t mask = 0;
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/* OR in the user selected peripherals */
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2013-06-08 21:50:42 +02:00
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#ifdef CONFIG_SAM32_RESET_PERIPHCLKS
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2013-06-07 22:59:33 +02:00
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#ifdef CONFIG_SAM34_OCD
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mask |= PM_CPUMASK_OCD; /* On-Chip Debug */
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2013-06-08 21:50:42 +02:00
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#endif
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2013-06-07 22:59:33 +02:00
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#endif
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/* Save the new CPU mask */
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putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_CPUMASK_OFFSET),
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SAM_PM_UNLOCK);
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putreg32(mask, SAM_PM_CPUMASK);
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}
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/****************************************************************************
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* Name: sam_init_hsbmask
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*
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* Description:
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* Called during boot to enable clocking on selected peripherals in the
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* HSB mask register.
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*
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****************************************************************************/
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static inline void sam_init_hsbmask(void)
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{
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/* Select the non-optional peripherals */
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uint32_t mask = (PM_HSBMASK_FLASHCALW | PM_HSBMASK_APBB |
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2013-06-08 17:21:20 +02:00
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PM_HSBMASK_APBC | PM_HSBMASK_APBD);
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2013-06-07 22:59:33 +02:00
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/* OR in the user selected peripherals */
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2013-06-08 21:50:42 +02:00
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#ifdef CONFIG_SAM32_RESET_PERIPHCLKS
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2013-06-07 22:59:33 +02:00
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#ifdef CONFIG_SAM34_PDCA
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mask |= PM_HSBMASK_PDCA; /* PDCA */
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#endif
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#ifdef CONFIG_SAM34_HRAMC1
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mask |= PM_HSBMASK_HRAMC1; /* HRAMC1 (picoCache RAM) */
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#endif
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#ifdef CONFIG_SAM34_USBC
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mask |= PM_HSBMASK_USBC; /* USBC */
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#endif
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#ifdef CONFIG_SAM34_CRCCU
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mask |= PM_HSBMASK_CRCCU; /* CRCCU */
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#endif
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#ifdef CONFIG_SAM34_APBA
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mask |= PM_HSBMASK_APBA; /* APBA bridge */
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#endif
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#ifdef CONFIG_SAM34_AESA
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mask |= PM_HSBMASK_AESA; /* AESA */
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2013-06-08 21:50:42 +02:00
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#endif
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2013-06-07 22:59:33 +02:00
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#endif
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/* Save the new HSB mask */
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putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_HSBMASK_OFFSET),
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SAM_PM_UNLOCK);
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putreg32(mask, SAM_PM_HSBMASK);
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}
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/****************************************************************************
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* Name: sam_init_pbamask
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*
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* Description:
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* Called during boot to enable clocking on selected peripherals in the
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* PBA mask register.
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*
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****************************************************************************/
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static inline void sam_init_pbamask(void)
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{
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/* Select the non-optional peripherals */
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uint32_t mask = 0;
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uint32_t divmask = 0;
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/* OR in the user selected peripherals */
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2013-06-08 21:50:42 +02:00
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#ifdef CONFIG_SAM32_RESET_PERIPHCLKS
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2013-06-07 22:59:33 +02:00
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#ifdef CONFIG_SAM34_IISC
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mask |= PM_PBAMASK_IISC; /* IISC */
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#endif
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#ifdef CONFIG_SAM34_SPI
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mask |= PM_PBAMASK_SPI; /* SPI */
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#endif
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#ifdef CONFIG_SAM34_TC0
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mask |= PM_PBAMASK_TC0; /* TC0 */
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divmask |= PM_PBADIVMASK_TIMER_CLOCKS;
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#endif
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#ifdef CONFIG_SAM34_TC1
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mask |= PM_PBAMASK_TC1; /* TC1 */
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divmask |= PM_PBADIVMASK_TIMER_CLOCKS;
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#endif
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#ifdef CONFIG_SAM34_TWIM0
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mask |= PM_PBAMASK_TWIM0; /* TWIM0 */
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#endif
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#ifdef CONFIG_SAM34_TWIS0
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mask |= PM_PBAMASK_TWIS0; /* TWIS0 */
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#endif
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#ifdef CONFIG_SAM34_TWIM1
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mask |= PM_PBAMASK_TWIM1; /* TWIM1 */
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#endif
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#ifdef CONFIG_SAM34_TWIS1
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mask |= PM_PBAMASK_TWIS1; /* TWIS1 */
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#endif
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#ifdef CONFIG_SAM34_USART0
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mask |= PM_PBAMASK_USART0; /* USART0 */
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2013-06-08 17:21:20 +02:00
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divmask |= PM_PBADIVMASK_CLK_USART;
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2013-06-07 22:59:33 +02:00
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#endif
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#ifdef CONFIG_SAM34_USART1
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mask |= PM_PBAMASK_USART1; /* USART1 */
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2013-06-08 17:21:20 +02:00
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divmask |= PM_PBADIVMASK_CLK_USART;
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2013-06-07 22:59:33 +02:00
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#endif
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#ifdef CONFIG_SAM34_USART2
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mask |= PM_PBAMASK_USART2; /* USART2 */
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2013-06-08 17:21:20 +02:00
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divmask |= PM_PBADIVMASK_CLK_USART;
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2013-06-07 22:59:33 +02:00
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#endif
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#ifdef CONFIG_SAM34_USART3
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mask |= PM_PBAMASK_USART3; /* USART3 */
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2013-06-08 17:21:20 +02:00
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divmask |= PM_PBADIVMASK_CLK_USART;
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2013-06-07 22:59:33 +02:00
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#endif
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#ifdef CONFIG_SAM34_ADCIFE
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mask |= PM_PBAMASK_ADCIFE; /* ADCIFE */
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#endif
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#ifdef CONFIG_SAM34_DACC
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mask |= PM_PBAMASK_DACC; /* DACC */
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#endif
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#ifdef CONFIG_SAM34_ACIFC
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mask |= PM_PBAMASK_ACIFC; /* ACIFC */
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#endif
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#ifdef CONFIG_SAM34_GLOC
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mask |= PM_PBAMASK_GLOC; /* GLOC */
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#endif
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#ifdef CONFIG_SAM34_ABDACB
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mask |= PM_PBAMASK_ABDACB; /* ABDACB */
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#endif
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#ifdef CONFIG_SAM34_TRNG
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mask |= PM_PBAMASK_TRNG; /* TRNG */
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#endif
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#ifdef CONFIG_SAM34_PARC
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mask |= PM_PBAMASK_PARC; /* PARC */
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#endif
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#ifdef CONFIG_SAM34_CATB
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mask |= PM_PBAMASK_CATB; /* CATB */
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#endif
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#ifdef CONFIG_SAM34_TWIM2
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mask |= PM_PBAMASK_TWIM2; /* TWIM2 */
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#endif
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#ifdef CONFIG_SAM34_TWIM3
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mask |= PM_PBAMASK_TWIM3; /* TWIM3 */
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#endif
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#ifdef CONFIG_SAM34_LCDCA
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mask |= PM_PBAMASK_LCDCA; /* LCDCA*/
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2013-06-08 21:50:42 +02:00
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#endif
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2013-06-07 22:59:33 +02:00
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#endif
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/* Save the new PBA mask */
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putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBAMASK_OFFSET),
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SAM_PM_UNLOCK);
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putreg32(mask, SAM_PM_PBAMASK);
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/* Set the peripheral divider mask as necessary */
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putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBADIVMASK_OFFSET),
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SAM_PM_UNLOCK);
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putreg32(divmask, SAM_PM_PBADIVMASK);
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}
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/****************************************************************************
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* Name: sam_init_pbbmask
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*
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* Description:
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* Called during boot to enable clocking on selected peripherals in the
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* PBB mask register.
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*
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****************************************************************************/
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static inline void sam_init_pbbmask(void)
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{
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/* Select the non-optional peripherals */
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uint32_t mask = PM_PBBMASK_FLASHCALW;
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/* OR in the user selected peripherals */
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2013-06-08 21:50:42 +02:00
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#ifdef CONFIG_SAM32_RESET_PERIPHCLKS
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2013-06-07 22:59:33 +02:00
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#ifdef CONFIG_SAM34_HRAMC1
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mask |= PM_PBBMASK_HRAMC1; /* HRAMC1 */
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#endif
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#ifdef CONFIG_SAM34_HMATRIX
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mask |= PM_PBBMASK_HMATRIX; /* HMATRIX */
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#endif
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#ifdef CONFIG_SAM34_PDCA
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mask |= PM_PBBMASK_PDCA; /* PDCA */
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#endif
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#ifdef CONFIG_SAM34_CRCCU
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mask |= PM_PBBMASK_CRCCU; /* CRCCU */
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#endif
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#ifdef CONFIG_SAM34_USBC
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mask |= PM_PBBMASK_USBC; /* USBC */
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#endif
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#ifdef CONFIG_SAM34_PEVC
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mask |= PM_PBBMASK_PEVC; /* PEVC */
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2013-06-08 21:50:42 +02:00
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#endif
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2013-06-07 22:59:33 +02:00
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#endif
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/* Save the new PBB mask */
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putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBBMASK_OFFSET),
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SAM_PM_UNLOCK);
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putreg32(mask, SAM_PM_PBBMASK);
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}
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/****************************************************************************
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* Name: sam_init_pbcmask
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*
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* Description:
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* Called during boot to enable clocking on selected peripherals in the
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* PBC mask register.
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*
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****************************************************************************/
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static inline void sam_init_pbcmask(void)
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{
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/* Select the non-optional peripherals */
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uint32_t mask = (PM_PBCMASK_PM | PM_PBCMASK_SCIF | PM_PBCMASK_GPIO);
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/* OR in the user selected peripherals */
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2013-06-08 21:50:42 +02:00
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#ifdef CONFIG_SAM32_RESET_PERIPHCLKS
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2013-06-07 22:59:33 +02:00
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#ifdef CONFIG_SAM34_CHIPID
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mask |= PM_PBCMASK_CHIPID; /* CHIPID */
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#endif
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#ifdef CONFIG_SAM34_FREQM
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mask |= PM_PBCMASK_FREQM; /* FREQM */
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2013-06-08 21:50:42 +02:00
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#endif
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2013-06-07 22:59:33 +02:00
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#endif
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/* Save the new PBC mask */
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putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBCMASK_OFFSET),
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SAM_PM_UNLOCK);
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putreg32(mask, SAM_PM_PBCMASK);
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}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: sam_init_pbdmask
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Called during boot to enable clocking on selected peripherals in the
|
|
|
|
* PBD mask register.
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
static inline void sam_init_pbdmask(void)
|
|
|
|
{
|
|
|
|
/* Select the non-optional peripherals */
|
|
|
|
|
|
|
|
uint32_t mask = (PM_PBDMASK_BPM | PM_PBDMASK_BSCIF);
|
|
|
|
|
|
|
|
/* OR in the user selected peripherals */
|
|
|
|
|
2013-06-08 21:50:42 +02:00
|
|
|
#ifdef CONFIG_SAM32_RESET_PERIPHCLKS
|
2013-06-07 22:59:33 +02:00
|
|
|
#ifdef CONFIG_SAM34_AST
|
|
|
|
mask |= PM_PBDMASK_AST; /* AST */
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_SAM34_WDT
|
|
|
|
mask |= PM_PBDMASK_WDT; /* WDT */
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_SAM34_EIC
|
|
|
|
mask |= PM_PBDMASK_EIC; /* EIC */
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_SAM34_PICOUART
|
|
|
|
mask |= PM_PBDMASK_PICOUART; /* PICOUART */
|
2013-06-08 21:50:42 +02:00
|
|
|
#endif
|
2013-06-07 22:59:33 +02:00
|
|
|
#endif
|
|
|
|
|
|
|
|
/* Save the new PBD mask */
|
|
|
|
|
|
|
|
putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBDMASK_OFFSET),
|
|
|
|
SAM_PM_UNLOCK);
|
|
|
|
putreg32(mask, SAM_PM_PBDMASK);
|
|
|
|
}
|
|
|
|
|
2013-06-06 02:48:30 +02:00
|
|
|
/****************************************************************************
|
|
|
|
* Public Functions
|
|
|
|
****************************************************************************/
|
|
|
|
|
2013-06-07 22:59:33 +02:00
|
|
|
/****************************************************************************
|
|
|
|
* Name: sam_init_periphclks
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Called during boot to enable clocking on all selected peripherals.
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
void sam_init_periphclks(void)
|
|
|
|
{
|
|
|
|
sam_init_cpumask();
|
|
|
|
sam_init_hsbmask();
|
|
|
|
sam_init_pbamask();
|
|
|
|
sam_init_pbbmask();
|
|
|
|
sam_init_pbcmask();
|
|
|
|
sam_init_pbdmask();
|
|
|
|
}
|
|
|
|
|
2013-06-06 02:48:30 +02:00
|
|
|
/****************************************************************************
|
|
|
|
* Name: sam_modifyperipheral
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* This is a convenience function that is intended to be used to enable
|
|
|
|
* or disable peripheral module clocking.
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2013-06-07 22:59:33 +02:00
|
|
|
void sam_modifyperipheral(uintptr_t regaddr, uint32_t clrbits,
|
|
|
|
uint32_t setbits)
|
2013-06-06 02:48:30 +02:00
|
|
|
{
|
|
|
|
irqstate_t flags;
|
|
|
|
uint32_t regval;
|
|
|
|
|
|
|
|
/* Make sure that the following operations are atomic */
|
|
|
|
|
|
|
|
flags = irqsave();
|
|
|
|
|
|
|
|
/* Enable/disabling clocking */
|
|
|
|
|
|
|
|
regval = getreg32(regaddr);
|
|
|
|
regval &= ~clrbits;
|
|
|
|
regval |= setbits;
|
2013-06-07 22:59:33 +02:00
|
|
|
putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(regaddr - SAM_PM_BASE),
|
|
|
|
SAM_PM_UNLOCK);
|
2013-06-06 02:48:30 +02:00
|
|
|
putreg32(regval, regaddr);
|
|
|
|
|
|
|
|
irqrestore(flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: sam_pba_modifydivmask
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* This is a convenience function that is intended to be used to modify
|
|
|
|
* bits in the PBA divided clock (DIVMASK) register.
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
void sam_pba_modifydivmask(uint32_t clrbits, uint32_t setbits)
|
|
|
|
{
|
|
|
|
irqstate_t flags;
|
|
|
|
uint32_t regval;
|
|
|
|
|
|
|
|
/* Make sure that the following operations are atomic */
|
|
|
|
|
|
|
|
flags = irqsave();
|
|
|
|
|
|
|
|
/* Modify the PBA DIVMASK */
|
|
|
|
|
|
|
|
regval = getreg32(SAM_PM_PBADIVMASK);
|
|
|
|
regval &= ~clrbits;
|
|
|
|
regval |= setbits;
|
2013-06-07 22:59:33 +02:00
|
|
|
putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBADIVMASK_OFFSET),
|
|
|
|
SAM_PM_UNLOCK);
|
2013-06-06 02:48:30 +02:00
|
|
|
putreg32(regval, SAM_PM_PBADIVMASK);
|
|
|
|
|
|
|
|
irqrestore(flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: sam_pba_enableperipheral
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* This is a convenience function to enable a peripheral on the APBA
|
|
|
|
* bridge.
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
void sam_pba_enableperipheral(uint32_t bitset)
|
|
|
|
{
|
|
|
|
irqstate_t flags;
|
|
|
|
|
|
|
|
/* The following operations must be atomic */
|
|
|
|
|
|
|
|
flags = irqsave();
|
|
|
|
|
|
|
|
/* Enable the APBA bridge if necessary */
|
|
|
|
|
|
|
|
if (getreg32(SAM_PM_PBAMASK) == 0)
|
|
|
|
{
|
|
|
|
sam_hsb_enableperipheral(PM_HSBMASK_APBA);
|
|
|
|
}
|
|
|
|
|
|
|
|
irqrestore(flags);
|
|
|
|
|
|
|
|
/* Enable the module */
|
|
|
|
|
|
|
|
sam_enableperipheral(SAM_PM_PBAMASK, bitset);
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: sam_pba_disableperipheral
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* This is a convenience function to disable a peripheral on the APBA
|
|
|
|
* bridge.
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
void sam_pba_disableperipheral(uint32_t bitset)
|
|
|
|
{
|
|
|
|
irqstate_t flags;
|
|
|
|
|
|
|
|
/* Disable clocking to the module */
|
|
|
|
|
|
|
|
sam_disableperipheral(SAM_PM_PBAMASK, bitset);
|
|
|
|
|
|
|
|
/* Disable the APBA bridge if possible */
|
|
|
|
|
|
|
|
flags = irqsave();
|
|
|
|
|
|
|
|
if (getreg32(SAM_PM_PBAMASK) == 0)
|
|
|
|
{
|
|
|
|
sam_hsb_disableperipheral(PM_HSBMASK_APBA);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Disable PBA UART divided clock if none of the UARTS are in use */
|
|
|
|
|
|
|
|
if ((getreg32(SAM_PM_PBAMASK) & PM_PBAMASK_UARTS) == 0)
|
|
|
|
{
|
|
|
|
sam_pba_disabledivmask(PM_PBADIVMASK_CLK_USART);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Disable PBA TIMER divided clocks if none of the UARTS are in use */
|
|
|
|
|
|
|
|
if ((getreg32(SAM_PM_PBAMASK) & PM_PBAMASK_TIMERS) == 0)
|
|
|
|
{
|
|
|
|
sam_pba_disabledivmask(PM_PBADIVMASK_TIMER_CLOCKS);
|
|
|
|
}
|
|
|
|
|
|
|
|
irqrestore(flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: sam_pbb_enableperipheral
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* This is a convenience function to enable a peripheral on the APBB
|
|
|
|
* bridge.
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
void sam_pbb_enableperipheral(uint32_t bitset)
|
|
|
|
{
|
|
|
|
irqstate_t flags;
|
|
|
|
|
|
|
|
/* The following operations must be atomic */
|
|
|
|
|
|
|
|
flags = irqsave();
|
|
|
|
|
|
|
|
/* Enable the APBB bridge if necessary */
|
|
|
|
|
|
|
|
if (getreg32(SAM_PM_PBBMASK) == 0)
|
|
|
|
{
|
|
|
|
sam_hsb_enableperipheral(PM_HSBMASK_APBB);
|
|
|
|
}
|
|
|
|
|
|
|
|
irqrestore(flags);
|
|
|
|
|
|
|
|
/* Enable the module */
|
|
|
|
|
|
|
|
sam_enableperipheral(SAM_PM_PBBMASK, bitset);
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: sam_pbb_disableperipheral
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* This is a convenience function to disable a peripheral on the APBA
|
|
|
|
* bridge.
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
void sam_pbb_disableperipheral(uint32_t bitset)
|
|
|
|
{
|
|
|
|
irqstate_t flags;
|
|
|
|
|
|
|
|
/* Disable clocking to the peripheral module */
|
|
|
|
|
|
|
|
sam_disableperipheral(SAM_PM_PBBMASK, bitset);
|
|
|
|
|
|
|
|
/* Disable the APBB bridge if possible */
|
|
|
|
|
|
|
|
flags = irqsave();
|
|
|
|
|
|
|
|
if (getreg32(SAM_PM_PBBMASK) == 0)
|
|
|
|
{
|
|
|
|
sam_hsb_disableperipheral(PM_HSBMASK_APBB);
|
|
|
|
}
|
|
|
|
|
|
|
|
irqrestore(flags);
|
|
|
|
}
|
2013-06-08 17:21:20 +02:00
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: sam_usbc_enableclk
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Enable clocking for the USBC using settings from the board.h header files.
|
|
|
|
*
|
|
|
|
* "The USBC has two bus clocks connected: One High Speed Bus clock
|
|
|
|
* (CLK_USBC_AHB) and one Peripheral Bus clock (CLK_USBC_APB). These clocks
|
|
|
|
* are generated by the Power Manager. Both clocks are enabled at reset
|
|
|
|
* and can be disabled by the Power Manager. It is recommended to disable
|
|
|
|
* the USBC before disabling the clocks, to avoid freezing the USBC in
|
|
|
|
* an undefined state.
|
|
|
|
*
|
|
|
|
* "To follow the usb data rate at 12Mbit/s in full-speed mode, the
|
|
|
|
* CLK_USBC_AHB clock should be at minimum 12MHz.
|
|
|
|
*
|
|
|
|
* "The 48MHz USB clock is generated by a dedicated generic clock from
|
|
|
|
* the SCIF module. Before using the USB, the user must ensure that the
|
|
|
|
* USB generic clock (GCLK_USBC) is enabled at 48MHz in the SCIF module."
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
#ifdef CONFIG_SAM34_USBC
|
|
|
|
void sam_usbc_enableclk(void)
|
|
|
|
{
|
|
|
|
irqstate_t flags;
|
|
|
|
uint32_t regval;
|
|
|
|
|
|
|
|
/* Enable USBC clocking (possibly along with the PBB peripheral bridge) */
|
|
|
|
|
|
|
|
flags = irqsave();
|
|
|
|
sam_hsb_enableperipheral(PM_HSBMASK_USBC);
|
|
|
|
sam_pbb_enableperipheral(PM_PBBMASK_USBC);
|
|
|
|
|
|
|
|
/* Reset generic clock 7 */
|
|
|
|
|
|
|
|
putreg32(0, SAM_SCIF_GCCTRL7);
|
|
|
|
|
|
|
|
/* Set the generic clock source */
|
|
|
|
|
|
|
|
regval = getreg32(SAM_SCIF_GCCTRL7);
|
|
|
|
regval &= ~SCIF_GCCTRL_OSCSEL_MASK;
|
|
|
|
regval |= SAM_USBC_GCLK_SOURCE;
|
|
|
|
putreg32(regval, SAM_SCIF_GCCTRL7);
|
|
|
|
|
|
|
|
/* Set the generic clock divider */
|
|
|
|
|
|
|
|
regval = getreg32(SAM_SCIF_GCCTRL7);
|
|
|
|
regval &= ~(SCIF_GCCTRL_DIVEN | SCIF_GCCTRL_DIV_MASK);
|
|
|
|
|
|
|
|
#if BOARD_USBC_GCLK_DIV > 1
|
|
|
|
regval |= SCIF_GCCTRL_DIVEN;
|
|
|
|
regval |= SCIF_GCCTRL_DIV(((divider + 1) / 2) - 1);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
putreg32(regval, SAM_SCIF_GCCTRL7);
|
|
|
|
|
|
|
|
/* Enable the generic clock */
|
|
|
|
|
|
|
|
regval = getreg32(SAM_SCIF_GCCTRL7);
|
|
|
|
regval |= SCIF_GCCTRL_CEN;
|
|
|
|
putreg32(regval, SAM_SCIF_GCCTRL7);
|
|
|
|
irqrestore(flags);
|
|
|
|
}
|
|
|
|
#endif /* CONFIG_SAM34_USBC */
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Name: sam_usbc_disableclk
|
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Disable clocking to the USBC.
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
#ifdef CONFIG_SAM34_USBC
|
|
|
|
void sam_usbc_disableclk(void)
|
|
|
|
{
|
|
|
|
putreg32(0, SAM_SCIF_GCCTRL7);
|
|
|
|
sam_pbb_enableperipheral(PM_PBBMASK_USBC);
|
|
|
|
sam_hsb_enableperipheral(PM_HSBMASK_USBC);
|
|
|
|
}
|
|
|
|
#endif /* CONFIG_SAM34_USBC */
|