2016-08-03 17:44:48 +02:00
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/****************************************************************************
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2022-01-06 14:19:39 +01:00
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* drivers/ioexpander/ioe_dummy.c
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2016-08-03 17:44:48 +02:00
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*
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2021-03-28 17:21:53 +02:00
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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2016-08-03 17:44:48 +02:00
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*
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2021-03-28 17:21:53 +02:00
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* http://www.apache.org/licenses/LICENSE-2.0
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2016-08-03 17:44:48 +02:00
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*
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2021-03-28 17:21:53 +02:00
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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2016-08-03 17:44:48 +02:00
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <assert.h>
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#include <errno.h>
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#include <debug.h>
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#include <nuttx/kmalloc.h>
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#include <nuttx/wdog.h>
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#include <nuttx/wqueue.h>
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2022-01-06 14:19:39 +01:00
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#include <nuttx/ioexpander/ioe_dummy.h>
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2016-08-03 17:44:48 +02:00
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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2022-01-06 14:19:39 +01:00
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#define IOE_DUMMY_POLLDELAY \
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(CONFIG_IOEXPANDER_DUMMY_INT_POLLDELAY / USEC_PER_TICK)
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2016-08-03 17:44:48 +02:00
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2022-01-06 14:19:39 +01:00
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#define IOE_DUMMY_INT_ENABLED(d,p) \
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2016-08-05 00:19:52 +02:00
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(((d)->intenab & ((ioe_pinset_t)1 << (p))) != 0)
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2022-01-06 14:19:39 +01:00
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#define IOE_DUMMY_INT_DISABLED(d,p) \
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2016-08-05 00:19:52 +02:00
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(((d)->intenab & ((ioe_pinset_t)1 << (p))) == 0)
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2022-01-06 14:19:39 +01:00
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#define IOE_DUMMY_LEVEL_SENSITIVE(d,p) \
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2016-08-03 17:44:48 +02:00
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(((d)->trigger & ((ioe_pinset_t)1 << (p))) == 0)
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2022-01-06 14:19:39 +01:00
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#define IOE_DUMMY_LEVEL_HIGH(d,p) \
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2016-08-03 17:44:48 +02:00
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(((d)->level[0] & ((ioe_pinset_t)1 << (p))) != 0)
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2022-01-06 14:19:39 +01:00
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#define IOE_DUMMY_LEVEL_LOW(d,p) \
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2016-08-03 17:44:48 +02:00
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(((d)->level[1] & ((ioe_pinset_t)1 << (p))) != 0)
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2022-01-06 14:19:39 +01:00
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#define IOE_DUMMY_EDGE_SENSITIVE(d,p) \
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2016-08-03 17:44:48 +02:00
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(((d)->trigger & ((ioe_pinset_t)1 << (p))) != 0)
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2022-01-06 14:19:39 +01:00
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#define IOE_DUMMY_EDGE_RISING(d,p) \
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2016-08-03 17:44:48 +02:00
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(((d)->level[0] & ((ioe_pinset_t)1 << (p))) != 0)
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2022-01-06 14:19:39 +01:00
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#define IOE_DUMMY_EDGE_FALLING(d,p) \
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2016-08-03 17:44:48 +02:00
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(((d)->level[1] & ((ioe_pinset_t)1 << (p))) != 0)
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2022-01-06 14:19:39 +01:00
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#define IOE_DUMMY_EDGE_BOTH(d,p) \
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(IOE_DUMMY_LEVEL_RISING(d,p) && IOE_DUMMY_LEVEL_FALLING(d,p))
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2016-08-03 17:44:48 +02:00
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/****************************************************************************
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* Private Types
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****************************************************************************/
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/* This type represents on registered pin interrupt callback */
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2022-01-06 14:19:39 +01:00
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struct ioe_dummy_callback_s
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2016-08-03 17:44:48 +02:00
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{
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2020-02-10 15:49:00 +01:00
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ioe_pinset_t pinset; /* Set of pin interrupts that will generate
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* the callback. */
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ioe_callback_t cbfunc; /* The saved callback function pointer */
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FAR void *cbarg; /* Callback argument */
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2016-08-03 17:44:48 +02:00
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};
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/* This structure represents the state of the I/O Expander driver */
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2022-01-06 14:19:39 +01:00
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struct ioe_dummy_dev_s
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2016-08-03 17:44:48 +02:00
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{
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2020-02-10 15:49:00 +01:00
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struct ioexpander_dev_s dev; /* Nested structure to allow casting as
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* public GPIO expander. */
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2016-08-03 17:44:48 +02:00
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ioe_pinset_t inpins; /* Pins select as inputs */
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ioe_pinset_t invert; /* Pin value inversion */
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ioe_pinset_t outval; /* Value of output pins */
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ioe_pinset_t inval; /* Simulated input register */
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2016-08-05 00:19:52 +02:00
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ioe_pinset_t intenab; /* Interrupt enable */
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2020-02-10 15:49:00 +01:00
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ioe_pinset_t last; /* Last pin inputs (for detection of
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* changes) */
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2016-08-03 17:44:48 +02:00
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ioe_pinset_t trigger; /* Bit encoded: 0=level 1=edge */
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2020-02-10 15:49:00 +01:00
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ioe_pinset_t level[2]; /* Bit encoded: 01=high/rising,
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* 10 low/falling, 11 both */
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2016-08-03 17:44:48 +02:00
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2020-08-04 12:31:31 +02:00
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struct wdog_s wdog; /* Timer used to poll for interrupt
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2020-02-10 15:49:00 +01:00
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* simulation */
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struct work_s work; /* Supports the interrupt handling
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* "bottom half" */
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2016-08-03 17:44:48 +02:00
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/* Saved callback information for each I/O expander client */
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2022-01-06 14:19:39 +01:00
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struct ioe_dummy_callback_s cb[CONFIG_IOEXPANDER_DUMMY_INT_NCALLBACKS];
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2016-08-03 17:44:48 +02:00
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};
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/****************************************************************************
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* Private Function Prototypes
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****************************************************************************/
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/* I/O Expander Methods */
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2022-01-06 14:19:39 +01:00
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static int ioe_dummy_direction(FAR struct ioexpander_dev_s *dev,
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uint8_t pin, int dir);
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static int ioe_dummy_option(FAR struct ioexpander_dev_s *dev,
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uint8_t pin, int opt, void *regval);
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static int ioe_dummy_writepin(FAR struct ioexpander_dev_s *dev,
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uint8_t pin, bool value);
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static int ioe_dummy_readpin(FAR struct ioexpander_dev_s *dev,
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uint8_t pin, FAR bool *value);
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2016-08-03 17:44:48 +02:00
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#ifdef CONFIG_IOEXPANDER_MULTIPIN
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2022-01-06 14:19:39 +01:00
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static int ioe_dummy_multiwritepin(FAR struct ioexpander_dev_s *dev,
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FAR uint8_t *pins, FAR bool *values,
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int count);
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static int ioe_dummy_multireadpin(FAR struct ioexpander_dev_s *dev,
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FAR uint8_t *pins, FAR bool *values,
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int count);
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2016-08-03 17:44:48 +02:00
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#endif
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2022-02-17 22:14:52 +01:00
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#ifdef CONFIG_IOEXPANDER_INT_ENABLE
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2022-01-06 14:19:39 +01:00
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static FAR void *ioe_dummy_attach(FAR struct ioexpander_dev_s *dev,
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ioe_pinset_t pinset,
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ioe_callback_t callback, FAR void *arg);
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static int ioe_dummy_detach(FAR struct ioexpander_dev_s *dev,
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FAR void *handle);
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2022-02-17 22:14:52 +01:00
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#endif
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2016-08-03 17:44:48 +02:00
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2022-01-06 14:19:39 +01:00
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static ioe_pinset_t ioe_dummy_int_update(FAR struct ioe_dummy_dev_s *priv);
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static void ioe_dummy_interrupt_work(void *arg);
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static void ioe_dummy_interrupt(wdparm_t arg);
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2016-08-03 17:44:48 +02:00
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/* Since only single device is supported, the driver state structure may as
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* well be pre-allocated.
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*/
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2022-01-06 14:19:39 +01:00
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static struct ioe_dummy_dev_s g_ioexpander;
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2016-08-03 17:44:48 +02:00
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/* I/O expander vtable */
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2022-01-06 14:19:39 +01:00
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static const struct ioexpander_ops_s g_ioe_dummy_ops =
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2016-08-03 17:44:48 +02:00
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{
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2022-01-06 14:19:39 +01:00
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ioe_dummy_direction,
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ioe_dummy_option,
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ioe_dummy_writepin,
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ioe_dummy_readpin,
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2022-02-17 22:14:52 +01:00
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ioe_dummy_readpin
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2016-08-03 17:44:48 +02:00
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#ifdef CONFIG_IOEXPANDER_MULTIPIN
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2022-02-17 22:14:52 +01:00
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, ioe_dummy_multiwritepin
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, ioe_dummy_multireadpin
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, ioe_dummy_multireadpin
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#endif
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#ifdef CONFIG_IOEXPANDER_INT_ENABLE
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, ioe_dummy_attach
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, ioe_dummy_detach
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2016-08-03 17:44:48 +02:00
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#endif
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};
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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2022-01-06 14:19:39 +01:00
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* Name: ioe_dummy_direction
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2016-08-03 17:44:48 +02:00
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*
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* Description:
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* Set the direction of an ioexpander pin. Required.
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*
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* Input Parameters:
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* dev - Device-specific state data
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* pin - The index of the pin to alter in this call
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* dir - One of the IOEXPANDER_DIRECTION_ macros
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*
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* Returned Value:
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* 0 on success, else a negative error code
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*
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****************************************************************************/
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2022-01-06 14:19:39 +01:00
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static int ioe_dummy_direction(FAR struct ioexpander_dev_s *dev,
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uint8_t pin, int direction)
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2016-08-03 17:44:48 +02:00
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{
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2022-01-06 14:19:39 +01:00
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FAR struct ioe_dummy_dev_s *priv = (FAR struct ioe_dummy_dev_s *)dev;
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2016-08-03 17:44:48 +02:00
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2020-07-02 12:47:58 +02:00
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if (direction != IOEXPANDER_DIRECTION_IN &&
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direction != IOEXPANDER_DIRECTION_OUT)
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{
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return -EINVAL;
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}
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DEBUGASSERT(priv != NULL && pin < CONFIG_IOEXPANDER_NPINS);
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2016-08-03 17:44:48 +02:00
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gpioinfo("pin=%u direction=%s\n",
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pin, (direction == IOEXPANDER_DIRECTION_IN) ? "IN" : "OUT");
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/* Set the pin direction */
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if (direction == IOEXPANDER_DIRECTION_IN)
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{
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/* Configure pin as input. */
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priv->inpins |= (1 << pin);
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}
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else /* if (direction == IOEXPANDER_DIRECTION_OUT) */
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{
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/* Configure pin as output. If a bit in this register is cleared to
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* 0, the corresponding port pin is enabled as an output.
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*
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* REVISIT: The value of output has not been selected! This might
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* put a glitch on the output.
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*/
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priv->inpins &= ~(1 << pin);
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}
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return OK;
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}
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/****************************************************************************
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2022-01-06 14:19:39 +01:00
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* Name: ioe_dummy_option
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2016-08-03 17:44:48 +02:00
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*
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* Description:
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* Set pin options. Required.
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* Since all IO expanders have various pin options, this API allows setting
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* pin options in a flexible way.
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*
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* Input Parameters:
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* dev - Device-specific state data
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* pin - The index of the pin to alter in this call
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* opt - One of the IOEXPANDER_OPTION_ macros
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* val - The option's value
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*
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* Returned Value:
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* 0 on success, else a negative error code
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*
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****************************************************************************/
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2022-03-01 17:18:50 +01:00
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static int ioe_dummy_option(FAR struct ioexpander_dev_s *dev, uint8_t pin,
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int opt, FAR void *value)
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2016-08-03 17:44:48 +02:00
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{
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2022-01-06 14:19:39 +01:00
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FAR struct ioe_dummy_dev_s *priv = (FAR struct ioe_dummy_dev_s *)dev;
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2016-08-03 17:44:48 +02:00
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int ret = -ENOSYS;
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DEBUGASSERT(priv != NULL);
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gpioinfo("pin=%u option=%u\n", pin, opt);
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/* Check for pin polarity inversion. The Polarity Inversion Register
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* allows polarity inversion of pins defined as inputs by the
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* Configuration Register. If a bit in this register is set, the
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* corresponding port pin's polarity is inverted. If a bit in this
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* register is cleared, the corresponding port pin's original polarity
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* is retained.
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*/
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if (opt == IOEXPANDER_OPTION_INVERT)
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{
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2022-03-01 17:18:50 +01:00
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if ((uintptr_t)value == IOEXPANDER_VAL_INVERT)
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2016-08-03 17:44:48 +02:00
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{
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priv->invert |= (1 << pin);
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}
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else
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{
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priv->invert &= ~(1 << pin);
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}
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}
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/* Interrupt configuration */
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else if (opt == IOEXPANDER_OPTION_INTCFG)
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{
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ioe_pinset_t bit = ((ioe_pinset_t)1 << pin);
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ret = OK;
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switch ((uintptr_t)value)
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{
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case IOEXPANDER_VAL_HIGH: /* Interrupt on high level */
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2016-08-05 00:19:52 +02:00
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priv->intenab |= bit;
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2016-08-03 17:44:48 +02:00
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priv->trigger &= ~bit;
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priv->level[0] |= bit;
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priv->level[1] &= ~bit;
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break;
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case IOEXPANDER_VAL_LOW: /* Interrupt on low level */
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2016-08-05 00:19:52 +02:00
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priv->intenab |= bit;
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2016-08-03 17:44:48 +02:00
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priv->trigger &= ~bit;
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priv->level[0] &= ~bit;
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priv->level[1] |= bit;
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break;
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case IOEXPANDER_VAL_RISING: /* Interrupt on rising edge */
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2016-08-05 00:19:52 +02:00
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priv->intenab |= bit;
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2016-08-03 17:44:48 +02:00
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|
|
priv->trigger |= bit;
|
|
|
|
priv->level[0] |= bit;
|
|
|
|
priv->level[1] &= ~bit;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case IOEXPANDER_VAL_FALLING: /* Interrupt on falling edge */
|
2016-08-05 00:19:52 +02:00
|
|
|
priv->intenab |= bit;
|
2016-08-03 17:44:48 +02:00
|
|
|
priv->trigger |= bit;
|
|
|
|
priv->level[0] &= ~bit;
|
|
|
|
priv->level[1] |= bit;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case IOEXPANDER_VAL_BOTH: /* Interrupt on both edges */
|
2016-08-05 00:19:52 +02:00
|
|
|
priv->intenab |= bit;
|
2016-08-03 17:44:48 +02:00
|
|
|
priv->trigger |= bit;
|
|
|
|
priv->level[0] |= bit;
|
|
|
|
priv->level[1] |= bit;
|
|
|
|
break;
|
|
|
|
|
2016-08-05 00:19:52 +02:00
|
|
|
case IOEXPANDER_VAL_DISABLE:
|
|
|
|
priv->trigger &= ~bit;
|
|
|
|
break;
|
|
|
|
|
2016-08-03 17:44:48 +02:00
|
|
|
default:
|
|
|
|
ret = -EINVAL;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
2022-01-06 14:19:39 +01:00
|
|
|
* Name: ioe_dummy_writepin
|
2016-08-03 17:44:48 +02:00
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Set the pin level. Required.
|
|
|
|
*
|
|
|
|
* Input Parameters:
|
|
|
|
* dev - Device-specific state data
|
|
|
|
* pin - The index of the pin to alter in this call
|
|
|
|
* val - The pin level. Usually TRUE will set the pin high,
|
|
|
|
* except if OPTION_INVERT has been set on this pin.
|
|
|
|
*
|
|
|
|
* Returned Value:
|
|
|
|
* 0 on success, else a negative error code
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2022-01-06 14:19:39 +01:00
|
|
|
static int ioe_dummy_writepin(FAR struct ioexpander_dev_s *dev,
|
|
|
|
uint8_t pin, bool value)
|
2016-08-03 17:44:48 +02:00
|
|
|
{
|
2022-01-06 14:19:39 +01:00
|
|
|
FAR struct ioe_dummy_dev_s *priv = (FAR struct ioe_dummy_dev_s *)dev;
|
2016-08-03 17:44:48 +02:00
|
|
|
|
|
|
|
DEBUGASSERT(priv != NULL && pin < CONFIG_IOEXPANDER_NPINS);
|
|
|
|
|
2016-08-03 20:46:54 +02:00
|
|
|
gpioinfo("pin=%u value=%u\n", pin, (unsigned int)value);
|
2016-08-03 17:44:48 +02:00
|
|
|
|
|
|
|
/* Set output pins default value (before configuring it as output) The
|
|
|
|
* Output Port Register shows the outgoing logic levels of the pins
|
|
|
|
* defined as outputs by the Configuration Register.
|
|
|
|
*/
|
|
|
|
|
2016-08-03 19:19:16 +02:00
|
|
|
if (value && (priv->invert & (1 << pin)) == 0)
|
2016-08-03 17:44:48 +02:00
|
|
|
{
|
|
|
|
priv->outval |= (1 << pin);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
priv->outval &= ~(1 << pin);
|
|
|
|
}
|
|
|
|
|
|
|
|
return OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
2022-01-06 14:19:39 +01:00
|
|
|
* Name: ioe_dummy_readpin
|
2016-08-03 17:44:48 +02:00
|
|
|
*
|
|
|
|
* Description:
|
2020-04-07 07:42:58 +02:00
|
|
|
* Read the actual PIN level. This can be different from the last value
|
|
|
|
* written to this pin. Required.
|
2016-08-03 17:44:48 +02:00
|
|
|
*
|
|
|
|
* Input Parameters:
|
|
|
|
* dev - Device-specific state data
|
|
|
|
* pin - The index of the pin
|
|
|
|
* valptr - Pointer to a buffer where the pin level is stored. Usually TRUE
|
2020-04-07 07:42:58 +02:00
|
|
|
* if the pin is high, except if OPTION_INVERT has been set on
|
|
|
|
* this pin.
|
2016-08-03 17:44:48 +02:00
|
|
|
*
|
|
|
|
* Returned Value:
|
|
|
|
* 0 on success, else a negative error code
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2022-01-06 14:19:39 +01:00
|
|
|
static int ioe_dummy_readpin(FAR struct ioexpander_dev_s *dev,
|
|
|
|
uint8_t pin, FAR bool *value)
|
2016-08-03 17:44:48 +02:00
|
|
|
{
|
2022-01-06 14:19:39 +01:00
|
|
|
FAR struct ioe_dummy_dev_s *priv = (FAR struct ioe_dummy_dev_s *)dev;
|
2016-08-03 17:44:48 +02:00
|
|
|
ioe_pinset_t inval;
|
2016-08-03 19:19:16 +02:00
|
|
|
bool retval;
|
2016-08-03 17:44:48 +02:00
|
|
|
|
2020-04-07 07:42:58 +02:00
|
|
|
DEBUGASSERT(priv != NULL && pin < CONFIG_IOEXPANDER_NPINS &&
|
|
|
|
value != NULL);
|
2016-08-03 17:44:48 +02:00
|
|
|
|
|
|
|
gpioinfo("pin=%u\n", pin);
|
|
|
|
|
|
|
|
/* Is this an output pin? */
|
|
|
|
|
|
|
|
if ((priv->inpins & (1 << pin)) != 0)
|
|
|
|
{
|
|
|
|
inval = priv->inval;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
inval = priv->outval;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Return 0 or 1 to indicate the state of pin */
|
|
|
|
|
2016-08-03 19:19:16 +02:00
|
|
|
retval = (((inval >> pin) & 1) != 0);
|
2016-08-03 20:46:54 +02:00
|
|
|
*value = ((priv->invert & (1 << pin)) != 0) ? !retval : retval;
|
|
|
|
return OK;
|
2016-08-03 17:44:48 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
2022-01-06 14:19:39 +01:00
|
|
|
* Name: ioe_dummy_multiwritepin
|
2016-08-03 17:44:48 +02:00
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Set the pin level for multiple pins. This routine may be faster than
|
|
|
|
* individual pin accesses. Optional.
|
|
|
|
*
|
|
|
|
* Input Parameters:
|
|
|
|
* dev - Device-specific state data
|
|
|
|
* pins - The list of pin indexes to alter in this call
|
|
|
|
* val - The list of pin levels.
|
|
|
|
*
|
|
|
|
* Returned Value:
|
|
|
|
* 0 on success, else a negative error code
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
#ifdef CONFIG_IOEXPANDER_MULTIPIN
|
2022-01-06 14:19:39 +01:00
|
|
|
static int ioe_dummy_multiwritepin(FAR struct ioexpander_dev_s *dev,
|
|
|
|
FAR uint8_t *pins, FAR bool *values,
|
|
|
|
int count)
|
2016-08-03 17:44:48 +02:00
|
|
|
{
|
2022-01-06 14:19:39 +01:00
|
|
|
FAR struct ioe_dummy_dev_s *priv = (FAR struct ioe_dummy_dev_s *)dev;
|
2016-08-03 17:44:48 +02:00
|
|
|
uint8_t pin;
|
|
|
|
int i;
|
|
|
|
|
2016-08-03 20:46:54 +02:00
|
|
|
gpioinfo("count=%d\n", count);
|
|
|
|
DEBUGASSERT(priv != NULL && pins != NULL && values != NULL && count > 0);
|
|
|
|
|
2016-08-03 17:44:48 +02:00
|
|
|
/* Apply the user defined changes */
|
|
|
|
|
|
|
|
for (i = 0; i < count; i++)
|
|
|
|
{
|
|
|
|
pin = pins[i];
|
|
|
|
DEBUGASSERT(pin < CONFIG_IOEXPANDER_NPINS);
|
|
|
|
|
2016-08-03 19:19:16 +02:00
|
|
|
if (values[i] && (priv->invert & (1 << pin)) == 0)
|
2016-08-03 17:44:48 +02:00
|
|
|
{
|
|
|
|
priv->outval |= (1 << pin);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
priv->outval &= ~(1 << pin);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return OK;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/****************************************************************************
|
2022-01-06 14:19:39 +01:00
|
|
|
* Name: ioe_dummy_multireadpin
|
2016-08-03 17:44:48 +02:00
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Read the actual level for multiple pins. This routine may be faster than
|
|
|
|
* individual pin accesses. Optional.
|
|
|
|
*
|
|
|
|
* Input Parameters:
|
|
|
|
* dev - Device-specific state data
|
|
|
|
* pin - The list of pin indexes to read
|
|
|
|
* valptr - Pointer to a buffer where the pin levels are stored.
|
|
|
|
*
|
|
|
|
* Returned Value:
|
|
|
|
* 0 on success, else a negative error code
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
#ifdef CONFIG_IOEXPANDER_MULTIPIN
|
2022-01-06 14:19:39 +01:00
|
|
|
static int ioe_dummy_multireadpin(FAR struct ioexpander_dev_s *dev,
|
|
|
|
FAR uint8_t *pins, FAR bool *values,
|
|
|
|
int count)
|
2016-08-03 17:44:48 +02:00
|
|
|
{
|
2022-01-06 14:19:39 +01:00
|
|
|
FAR struct ioe_dummy_dev_s *priv = (FAR struct ioe_dummy_dev_s *)dev;
|
2016-08-03 17:44:48 +02:00
|
|
|
ioe_pinset_t inval;
|
|
|
|
uint8_t pin;
|
2016-08-03 19:19:16 +02:00
|
|
|
bool pinval;
|
2016-08-03 17:44:48 +02:00
|
|
|
int i;
|
|
|
|
|
|
|
|
gpioinfo("count=%d\n", count);
|
2016-08-03 20:46:54 +02:00
|
|
|
DEBUGASSERT(priv != NULL && pins != NULL && values != NULL && count > 0);
|
2016-08-03 17:44:48 +02:00
|
|
|
|
|
|
|
/* Update the input status with the 8 bits read from the expander */
|
|
|
|
|
|
|
|
for (i = 0; i < count; i++)
|
|
|
|
{
|
|
|
|
pin = pins[i];
|
|
|
|
DEBUGASSERT(pin < CONFIG_IOEXPANDER_NPINS);
|
|
|
|
|
|
|
|
/* Is this an output pin? */
|
|
|
|
|
|
|
|
if ((priv->inpins & (1 << pin)) != 0)
|
|
|
|
{
|
|
|
|
inval = priv->inval;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
inval = priv->outval;
|
|
|
|
}
|
|
|
|
|
2016-08-03 19:19:16 +02:00
|
|
|
pinval = ((inval & (1 << pin)) != 0);
|
|
|
|
values[i] = ((priv->invert & (1 << pin)) != 0) ? !pinval : pinval;
|
2016-08-03 17:44:48 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
return OK;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/****************************************************************************
|
2022-01-06 14:19:39 +01:00
|
|
|
* Name: ioe_dummy_attach
|
2016-08-03 17:44:48 +02:00
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Attach and enable a pin interrupt callback function.
|
|
|
|
*
|
|
|
|
* Input Parameters:
|
|
|
|
* dev - Device-specific state data
|
|
|
|
* pinset - The set of pin events that will generate the callback
|
|
|
|
* callback - The pointer to callback function. NULL will detach the
|
|
|
|
* callback.
|
|
|
|
* arg - User-provided callback argument
|
|
|
|
*
|
|
|
|
* Returned Value:
|
|
|
|
* A non-NULL handle value is returned on success. This handle may be
|
|
|
|
* used later to detach and disable the pin interrupt.
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2022-02-17 22:14:52 +01:00
|
|
|
#ifdef CONFIG_IOEXPANDER_INT_ENABLE
|
2022-01-06 14:19:39 +01:00
|
|
|
static FAR void *ioe_dummy_attach(FAR struct ioexpander_dev_s *dev,
|
|
|
|
ioe_pinset_t pinset,
|
|
|
|
ioe_callback_t callback, FAR void *arg)
|
2016-08-03 17:44:48 +02:00
|
|
|
{
|
2022-01-06 14:19:39 +01:00
|
|
|
FAR struct ioe_dummy_dev_s *priv = (FAR struct ioe_dummy_dev_s *)dev;
|
2016-08-03 17:44:48 +02:00
|
|
|
FAR void *handle = NULL;
|
|
|
|
int i;
|
|
|
|
|
2016-08-03 20:46:54 +02:00
|
|
|
gpioinfo("pinset=%lx callback=%p arg=%p\n",
|
|
|
|
(unsigned long)pinset, callback, arg);
|
|
|
|
|
2016-08-03 17:44:48 +02:00
|
|
|
/* Find and available in entry in the callback table */
|
|
|
|
|
2022-01-06 14:19:39 +01:00
|
|
|
for (i = 0; i < CONFIG_IOEXPANDER_DUMMY_INT_NCALLBACKS; i++)
|
2016-08-03 17:44:48 +02:00
|
|
|
{
|
2020-02-10 15:49:00 +01:00
|
|
|
/* Is this entry available (i.e., no callback attached) */
|
|
|
|
|
|
|
|
if (priv->cb[i].cbfunc == NULL)
|
|
|
|
{
|
|
|
|
/* Yes.. use this entry */
|
|
|
|
|
|
|
|
priv->cb[i].pinset = pinset;
|
|
|
|
priv->cb[i].cbfunc = callback;
|
|
|
|
priv->cb[i].cbarg = arg;
|
|
|
|
handle = &priv->cb[i];
|
|
|
|
break;
|
|
|
|
}
|
2016-08-03 17:44:48 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
return handle;
|
|
|
|
}
|
2022-02-17 22:14:52 +01:00
|
|
|
#endif
|
2016-08-03 17:44:48 +02:00
|
|
|
|
|
|
|
/****************************************************************************
|
2022-01-06 14:19:39 +01:00
|
|
|
* Name: ioe_dummy_detach
|
2016-08-03 17:44:48 +02:00
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Detach and disable a pin interrupt callback function.
|
|
|
|
*
|
|
|
|
* Input Parameters:
|
|
|
|
* dev - Device-specific state data
|
2022-01-06 14:19:39 +01:00
|
|
|
* handle - The non-NULL opaque value return by ioe_dummy_attch()
|
2016-08-03 17:44:48 +02:00
|
|
|
*
|
|
|
|
* Returned Value:
|
|
|
|
* 0 on success, else a negative error code
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2022-02-17 22:14:52 +01:00
|
|
|
#ifdef CONFIG_IOEXPANDER_INT_ENABLE
|
2022-01-06 14:19:39 +01:00
|
|
|
static int ioe_dummy_detach(FAR struct ioexpander_dev_s *dev,
|
|
|
|
FAR void *handle)
|
2016-08-03 17:44:48 +02:00
|
|
|
{
|
2022-01-06 14:19:39 +01:00
|
|
|
FAR struct ioe_dummy_dev_s *priv = (FAR struct ioe_dummy_dev_s *)dev;
|
|
|
|
FAR struct ioe_dummy_callback_s *cb =
|
|
|
|
(FAR struct ioe_dummy_callback_s *)handle;
|
2016-08-03 17:44:48 +02:00
|
|
|
|
2016-08-03 20:46:54 +02:00
|
|
|
gpioinfo("handle=%p\n", handle);
|
|
|
|
|
2016-08-03 17:44:48 +02:00
|
|
|
DEBUGASSERT(priv != NULL && cb != NULL);
|
2022-01-06 14:19:39 +01:00
|
|
|
DEBUGASSERT((uintptr_t)cb >= (uintptr_t)&priv->cb[0] && (uintptr_t)cb <=
|
|
|
|
(uintptr_t)&priv->cb[CONFIG_IOEXPANDER_DUMMY_INT_NCALLBACKS - 1]);
|
2016-08-03 17:44:48 +02:00
|
|
|
UNUSED(priv);
|
|
|
|
|
|
|
|
cb->pinset = 0;
|
|
|
|
cb->cbfunc = NULL;
|
|
|
|
cb->cbarg = NULL;
|
|
|
|
return OK;
|
|
|
|
}
|
2022-02-17 22:14:52 +01:00
|
|
|
#endif
|
2016-08-03 17:44:48 +02:00
|
|
|
|
|
|
|
/****************************************************************************
|
2022-01-06 14:19:39 +01:00
|
|
|
* Name: ioe_dummy_int_update
|
2016-08-03 17:44:48 +02:00
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Check for pending interrupts.
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2022-01-06 14:19:39 +01:00
|
|
|
static ioe_pinset_t ioe_dummy_int_update(FAR struct ioe_dummy_dev_s *priv)
|
2016-08-03 17:44:48 +02:00
|
|
|
{
|
2016-08-03 20:46:54 +02:00
|
|
|
ioe_pinset_t toggles;
|
2016-08-03 17:44:48 +02:00
|
|
|
ioe_pinset_t diff;
|
|
|
|
ioe_pinset_t input;
|
|
|
|
ioe_pinset_t intstat;
|
2016-08-03 19:19:16 +02:00
|
|
|
bool pinval;
|
2016-08-03 17:44:48 +02:00
|
|
|
int pin;
|
2016-08-03 20:46:54 +02:00
|
|
|
int i;
|
|
|
|
|
|
|
|
/* First, toggle all input bits that have associated, attached interrupt
|
|
|
|
* handler. This is a crude simulation for toggle interrupt inputs.
|
|
|
|
*/
|
|
|
|
|
|
|
|
toggles = 0;
|
2022-01-06 14:19:39 +01:00
|
|
|
for (i = 0; i < CONFIG_IOEXPANDER_DUMMY_INT_NCALLBACKS; i++)
|
2016-08-03 20:46:54 +02:00
|
|
|
{
|
|
|
|
/* Is there a callback attached? */
|
|
|
|
|
|
|
|
if (priv->cb[i].cbfunc != NULL)
|
|
|
|
{
|
|
|
|
/* Yes, add the input pins to set of pins to toggle */
|
|
|
|
|
|
|
|
toggles |= (priv->cb[i].pinset & priv->inpins);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
priv->inval = (priv->inval & ~toggles) | (~priv->inval & toggles);
|
2016-08-03 17:44:48 +02:00
|
|
|
|
|
|
|
/* Check the changed bits from last read (Only applies to input pins) */
|
|
|
|
|
|
|
|
input = priv->inval;
|
|
|
|
diff = priv->last ^ input;
|
2016-08-03 21:10:20 +02:00
|
|
|
if (diff != 0)
|
2016-08-03 17:44:48 +02:00
|
|
|
{
|
2016-08-03 21:10:20 +02:00
|
|
|
gpioinfo("toggles=%lx inval=%lx last=%lx diff=%lx\n",
|
|
|
|
(unsigned long)toggles, (unsigned long)priv->inval,
|
|
|
|
(unsigned long)priv->last, (unsigned long)diff);
|
2016-08-03 17:44:48 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
priv->last = input;
|
|
|
|
intstat = 0;
|
|
|
|
|
|
|
|
/* Check for changes in pins that could generate an interrupt. */
|
|
|
|
|
|
|
|
for (pin = 0; pin < CONFIG_IOEXPANDER_NPINS; pin++)
|
|
|
|
{
|
2016-08-05 00:19:52 +02:00
|
|
|
/* Get the value of the pin (accounting for inversion) */
|
|
|
|
|
|
|
|
pinval = ((input & 1) != 0);
|
|
|
|
if ((priv->invert & (1 << pin)) != 0)
|
|
|
|
{
|
|
|
|
pinval = !pinval;
|
|
|
|
}
|
|
|
|
|
2022-01-06 14:19:39 +01:00
|
|
|
if (IOE_DUMMY_INT_DISABLED(priv, pin))
|
2016-08-05 00:19:52 +02:00
|
|
|
{
|
|
|
|
/* Interrupts disabled on this pin. Do nothing.. just skip to the
|
|
|
|
* next pin.
|
|
|
|
*/
|
|
|
|
}
|
2022-01-06 14:19:39 +01:00
|
|
|
else if (IOE_DUMMY_EDGE_SENSITIVE(priv, pin))
|
2016-08-03 17:44:48 +02:00
|
|
|
{
|
2016-08-03 20:46:54 +02:00
|
|
|
/* Edge triggered. Was there a change in the level? */
|
|
|
|
|
|
|
|
if ((diff & 1) != 0)
|
2016-08-03 19:19:16 +02:00
|
|
|
{
|
2016-08-03 20:46:54 +02:00
|
|
|
/* Set interrupt as a function of edge type */
|
|
|
|
|
2022-01-06 14:19:39 +01:00
|
|
|
if ((!pinval && IOE_DUMMY_EDGE_FALLING(priv, pin)) ||
|
|
|
|
(pinval && IOE_DUMMY_EDGE_RISING(priv, pin)))
|
2016-08-03 20:46:54 +02:00
|
|
|
{
|
|
|
|
intstat |= 1 << pin;
|
|
|
|
}
|
2016-08-03 17:44:48 +02:00
|
|
|
}
|
|
|
|
}
|
2022-01-06 14:19:39 +01:00
|
|
|
else /* if (IOE_DUMMY_LEVEL_SENSITIVE(priv, pin)) */
|
2016-08-03 17:44:48 +02:00
|
|
|
{
|
2016-08-05 15:17:42 +02:00
|
|
|
/* Level triggered. Set intstat if match in level type. */
|
2016-08-03 17:44:48 +02:00
|
|
|
|
2022-01-06 14:19:39 +01:00
|
|
|
if ((pinval && IOE_DUMMY_LEVEL_HIGH(priv, pin)) ||
|
|
|
|
(!pinval && IOE_DUMMY_LEVEL_LOW(priv, pin)))
|
2016-08-03 17:44:48 +02:00
|
|
|
{
|
|
|
|
intstat |= 1 << pin;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
diff >>= 1;
|
|
|
|
input >>= 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
return intstat;
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
2022-01-06 14:19:39 +01:00
|
|
|
* Name: ioe_dummy_interrupt_work
|
2016-08-03 17:44:48 +02:00
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* Handle GPIO interrupt events (this function actually executes in the
|
|
|
|
* context of the worker thread).
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2022-01-06 14:19:39 +01:00
|
|
|
static void ioe_dummy_interrupt_work(void *arg)
|
2016-08-03 17:44:48 +02:00
|
|
|
{
|
2022-01-06 14:19:39 +01:00
|
|
|
FAR struct ioe_dummy_dev_s *priv = (FAR struct ioe_dummy_dev_s *)arg;
|
2016-08-03 17:44:48 +02:00
|
|
|
ioe_pinset_t intstat;
|
|
|
|
int ret;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
DEBUGASSERT(priv != NULL);
|
|
|
|
|
|
|
|
/* Update the input status with the 32 bits read from the expander */
|
|
|
|
|
2022-01-06 14:19:39 +01:00
|
|
|
intstat = ioe_dummy_int_update(priv);
|
2016-08-03 20:46:54 +02:00
|
|
|
if (intstat != 0)
|
2016-08-03 17:44:48 +02:00
|
|
|
{
|
2016-08-03 20:46:54 +02:00
|
|
|
gpioinfo("intstat=%lx\n", (unsigned long)intstat);
|
2016-08-03 17:44:48 +02:00
|
|
|
|
2016-08-03 20:46:54 +02:00
|
|
|
/* Perform pin interrupt callbacks */
|
|
|
|
|
2022-01-06 14:19:39 +01:00
|
|
|
for (i = 0; i < CONFIG_IOEXPANDER_DUMMY_INT_NCALLBACKS; i++)
|
2016-08-03 17:44:48 +02:00
|
|
|
{
|
2016-08-03 20:46:54 +02:00
|
|
|
/* Is this entry valid (i.e., callback attached)? */
|
2016-08-03 17:44:48 +02:00
|
|
|
|
2016-08-03 20:46:54 +02:00
|
|
|
if (priv->cb[i].cbfunc != NULL)
|
2016-08-03 17:44:48 +02:00
|
|
|
{
|
2016-08-03 20:46:54 +02:00
|
|
|
/* Did any of the requested pin interrupts occur? */
|
|
|
|
|
|
|
|
ioe_pinset_t match = intstat & priv->cb[i].pinset;
|
|
|
|
if (match != 0)
|
|
|
|
{
|
|
|
|
/* Yes.. perform the callback */
|
2016-08-03 17:44:48 +02:00
|
|
|
|
2020-01-02 17:49:34 +01:00
|
|
|
priv->cb[i].cbfunc(&priv->dev, match,
|
|
|
|
priv->cb[i].cbarg);
|
2016-08-03 20:46:54 +02:00
|
|
|
}
|
2016-08-03 17:44:48 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Re-start the poll timer */
|
|
|
|
|
2022-01-06 14:19:39 +01:00
|
|
|
ret = wd_start(&priv->wdog, IOE_DUMMY_POLLDELAY,
|
|
|
|
ioe_dummy_interrupt, (wdparm_t)priv);
|
2016-08-03 17:44:48 +02:00
|
|
|
if (ret < 0)
|
|
|
|
{
|
|
|
|
gpioerr("ERROR: Failed to start poll timer\n");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
2022-01-06 14:19:39 +01:00
|
|
|
* Name: ioe_dummy_interrupt
|
2016-08-03 17:44:48 +02:00
|
|
|
*
|
|
|
|
* Description:
|
|
|
|
* The poll timer has expired; check for missed interrupts
|
|
|
|
*
|
|
|
|
* Input Parameters:
|
|
|
|
* Standard wdog expiration arguments.
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2022-01-06 14:19:39 +01:00
|
|
|
static void ioe_dummy_interrupt(wdparm_t arg)
|
2016-08-03 17:44:48 +02:00
|
|
|
{
|
2022-01-06 14:19:39 +01:00
|
|
|
FAR struct ioe_dummy_dev_s *priv;
|
2016-08-03 17:44:48 +02:00
|
|
|
|
2022-01-06 14:19:39 +01:00
|
|
|
priv = (FAR struct ioe_dummy_dev_s *)arg;
|
2016-08-03 17:44:48 +02:00
|
|
|
DEBUGASSERT(priv != NULL);
|
|
|
|
|
|
|
|
/* Defer interrupt processing to the worker thread. This is not only
|
|
|
|
* much kinder in the use of system resources but is probably necessary
|
|
|
|
* to access the I/O expander device.
|
|
|
|
*
|
|
|
|
* Notice that further GPIO interrupts are disabled until the work is
|
|
|
|
* actually performed. This is to prevent overrun of the worker thread.
|
2022-01-06 14:19:39 +01:00
|
|
|
* Interrupts are re-enabled in ioe_dummy_interrupt_work() when the work is
|
2016-08-03 17:44:48 +02:00
|
|
|
* completed.
|
|
|
|
*/
|
|
|
|
|
|
|
|
if (work_available(&priv->work))
|
|
|
|
{
|
2020-04-07 07:42:58 +02:00
|
|
|
/* Schedule interrupt related work on the high priority worker
|
|
|
|
* thread.
|
|
|
|
*/
|
2016-08-03 17:44:48 +02:00
|
|
|
|
2022-01-06 14:19:39 +01:00
|
|
|
work_queue(HPWORK, &priv->work, ioe_dummy_interrupt_work,
|
2016-08-03 17:44:48 +02:00
|
|
|
(FAR void *)priv, 0);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/****************************************************************************
|
|
|
|
* Public Functions
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
/****************************************************************************
|
2022-01-06 14:19:39 +01:00
|
|
|
* Name: ioe_dummy_initialize
|
2016-08-03 17:44:48 +02:00
|
|
|
*
|
|
|
|
* Description:
|
2020-04-07 07:42:58 +02:00
|
|
|
* Instantiate and configure the I/O Expander device driver to use the
|
|
|
|
* provided I2C device instance.
|
2016-08-03 17:44:48 +02:00
|
|
|
*
|
|
|
|
* Input Parameters:
|
|
|
|
* i2c - An I2C driver instance
|
|
|
|
* minor - The device i2c address
|
|
|
|
* config - Persistent board configuration data
|
|
|
|
*
|
|
|
|
* Returned Value:
|
|
|
|
* an ioexpander_dev_s instance on success, NULL on failure.
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
2022-01-06 14:19:39 +01:00
|
|
|
FAR struct ioexpander_dev_s *ioe_dummy_initialize(void)
|
2016-08-03 17:44:48 +02:00
|
|
|
{
|
2022-01-06 14:19:39 +01:00
|
|
|
FAR struct ioe_dummy_dev_s *priv = &g_ioexpander;
|
2016-08-03 17:44:48 +02:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
/* Initialize the device state structure */
|
|
|
|
|
2022-01-06 14:19:39 +01:00
|
|
|
priv->dev.ops = &g_ioe_dummy_ops;
|
2016-08-03 17:44:48 +02:00
|
|
|
|
|
|
|
/* Initial interrupt state: Edge triggered on both edges */
|
|
|
|
|
|
|
|
priv->trigger = PINSET_ALL; /* All edge triggered */
|
|
|
|
priv->level[0] = PINSET_ALL; /* All rising edge */
|
|
|
|
priv->level[1] = PINSET_ALL; /* All falling edge */
|
|
|
|
|
2022-01-06 14:19:39 +01:00
|
|
|
ret = wd_start(&priv->wdog, IOE_DUMMY_POLLDELAY,
|
|
|
|
ioe_dummy_interrupt, (wdparm_t)priv);
|
2016-08-03 17:44:48 +02:00
|
|
|
if (ret < 0)
|
|
|
|
{
|
|
|
|
gpioerr("ERROR: Failed to start poll timer\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
return &priv->dev;
|
|
|
|
}
|