2019-08-19 17:16:08 +02:00
|
|
|
|
/****************************************************************************
|
|
|
|
|
* boards/arm/stm32l4/nucleo-l476rg/include/nucleo-l476rg.h
|
2016-03-10 18:21:35 +01:00
|
|
|
|
*
|
2021-03-19 12:39:00 +01:00
|
|
|
|
* Licensed to the Apache Software Foundation (ASF) under one or more
|
|
|
|
|
* contributor license agreements. See the NOTICE file distributed with
|
|
|
|
|
* this work for additional information regarding copyright ownership. The
|
|
|
|
|
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
|
|
|
|
* "License"); you may not use this file except in compliance with the
|
|
|
|
|
* License. You may obtain a copy of the License at
|
2016-03-10 18:21:35 +01:00
|
|
|
|
*
|
2021-03-19 12:39:00 +01:00
|
|
|
|
* http://www.apache.org/licenses/LICENSE-2.0
|
2016-03-10 18:21:35 +01:00
|
|
|
|
*
|
2021-03-19 12:39:00 +01:00
|
|
|
|
* Unless required by applicable law or agreed to in writing, software
|
|
|
|
|
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
|
|
|
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
|
|
|
|
* License for the specific language governing permissions and limitations
|
|
|
|
|
* under the License.
|
2016-03-10 18:21:35 +01:00
|
|
|
|
*
|
2019-08-19 17:16:08 +02:00
|
|
|
|
****************************************************************************/
|
2016-03-10 18:21:35 +01:00
|
|
|
|
|
2019-08-19 17:16:08 +02:00
|
|
|
|
#ifndef __BOARDS_ARM_STM32L4_NUCLEO_L476RG_INCLUDE_NUCLEO_L476RG_H
|
|
|
|
|
#define __BOARDS_ARM_STM32L4_NUCLEO_L476RG_INCLUDE_NUCLEO_L476RG_H
|
2016-03-10 18:21:35 +01:00
|
|
|
|
|
2019-08-19 17:16:08 +02:00
|
|
|
|
/****************************************************************************
|
2016-03-10 18:21:35 +01:00
|
|
|
|
* Included Files
|
2019-08-19 17:16:08 +02:00
|
|
|
|
****************************************************************************/
|
2016-03-10 18:21:35 +01:00
|
|
|
|
|
|
|
|
|
#include <nuttx/config.h>
|
|
|
|
|
#ifndef __ASSEMBLY__
|
|
|
|
|
# include <stdint.h>
|
|
|
|
|
#endif
|
|
|
|
|
|
2019-08-19 17:16:08 +02:00
|
|
|
|
/****************************************************************************
|
2016-03-10 18:21:35 +01:00
|
|
|
|
* Pre-processor Definitions
|
2019-08-19 17:16:08 +02:00
|
|
|
|
****************************************************************************/
|
2016-03-10 18:21:35 +01:00
|
|
|
|
|
2016-04-30 05:13:32 +02:00
|
|
|
|
#if 1
|
2016-04-30 17:04:38 +02:00
|
|
|
|
# define HSI_CLOCK_CONFIG /* HSI-16 clock configuration */
|
2016-04-30 05:13:32 +02:00
|
|
|
|
#elif 0
|
2016-04-30 17:04:38 +02:00
|
|
|
|
/* Make sure you installed one! */
|
|
|
|
|
|
|
|
|
|
# define HSE_CLOCK_CONFIG /* HSE with 8 MHz xtal */
|
2016-04-30 05:13:32 +02:00
|
|
|
|
#else
|
2016-04-30 17:04:38 +02:00
|
|
|
|
# define MSI_CLOCK_CONFIG /* MSI @ 4 MHz autotrimmed via LSE */
|
2016-04-30 05:13:32 +02:00
|
|
|
|
#endif
|
|
|
|
|
|
2019-08-19 17:16:08 +02:00
|
|
|
|
/* Clocking *****************************************************************/
|
2016-03-10 18:21:35 +01:00
|
|
|
|
|
2016-04-30 05:13:32 +02:00
|
|
|
|
#if defined(HSI_CLOCK_CONFIG)
|
2021-03-20 13:01:22 +01:00
|
|
|
|
/* The NUCLEOL476RG supports both HSE and LSE crystals (X2 and X3). However,
|
|
|
|
|
* as shipped, the X3 crystal is not populated. Therefore the Nucleo-L476RG
|
2016-03-10 18:21:35 +01:00
|
|
|
|
* will need to run off the 16MHz HSI clock, or the 32khz-synced MSI.
|
|
|
|
|
*
|
2021-03-20 13:01:22 +01:00
|
|
|
|
* System Clock source : PLL (HSI)
|
|
|
|
|
* SYSCLK(Hz) : 80000000 Determined by PLL configuration
|
|
|
|
|
* HCLK(Hz) : 80000000 (STM32L4_RCC_CFGR_HPRE) (Max 80 MHz)
|
|
|
|
|
* AHB Prescaler : 1 (STM32L4_RCC_CFGR_HPRE) (Max 80 MHz)
|
|
|
|
|
* APB1 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE1) (Max 80 MHz)
|
|
|
|
|
* APB2 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE2) (Max 80 MHz)
|
|
|
|
|
* HSI Frequency(Hz) : 16000000 (nominal)
|
|
|
|
|
* PLLM : 1 (STM32L4_PLLCFG_PLLM)
|
|
|
|
|
* PLLN : 10 (STM32L4_PLLCFG_PLLN)
|
|
|
|
|
* PLLP : 0 (STM32L4_PLLCFG_PLLP)
|
|
|
|
|
* PLLQ : 0 (STM32L4_PLLCFG_PLLQ)
|
|
|
|
|
* PLLR : 2 (STM32L4_PLLCFG_PLLR)
|
|
|
|
|
* PLLSAI1N : 12
|
|
|
|
|
* PLLSAI1Q : 4
|
|
|
|
|
* Flash Latency(WS) : 4
|
|
|
|
|
* Prefetch Buffer : OFF
|
|
|
|
|
* 48MHz for USB OTG FS, : Doable if required using PLLSAI1 or MSI
|
2016-03-10 18:21:35 +01:00
|
|
|
|
* SDIO and RNG clock
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
/* HSI - 16 MHz RC factory-trimmed
|
|
|
|
|
* LSI - 32 KHz RC
|
|
|
|
|
* MSI - variable up to 48 MHz, synchronized to LSE
|
|
|
|
|
* HSE - not installed
|
|
|
|
|
* LSE - 32.768 kHz installed
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#define STM32L4_HSI_FREQUENCY 16000000ul
|
|
|
|
|
#define STM32L4_LSI_FREQUENCY 32000
|
|
|
|
|
#define STM32L4_LSE_FREQUENCY 32768
|
|
|
|
|
|
|
|
|
|
#define STM32L4_BOARD_USEHSI 1
|
|
|
|
|
|
2016-04-30 05:13:32 +02:00
|
|
|
|
/* XXX sysclk mux = pllclk */
|
|
|
|
|
|
|
|
|
|
/* XXX pll source mux = hsi */
|
|
|
|
|
|
2016-03-10 18:21:35 +01:00
|
|
|
|
/* REVISIT: Trimming of the HSI and MSI is not yet supported. */
|
|
|
|
|
|
|
|
|
|
/* Main PLL Configuration.
|
|
|
|
|
*
|
|
|
|
|
* Formulae:
|
|
|
|
|
*
|
2021-03-20 13:01:22 +01:00
|
|
|
|
* VCO input frequency = PLL input clock frequency / PLLM,
|
|
|
|
|
* 1 <= PLLM <= 8
|
|
|
|
|
* VCO output frequency = VCO input frequency × PLLN,
|
|
|
|
|
* 8 <= PLLN <= 86,
|
|
|
|
|
* frequency range 64 to 344 MHz
|
|
|
|
|
* PLL output P (SAI3) clock frequency = VCO frequency / PLLP,
|
|
|
|
|
* PLLP = 7, or 17,
|
|
|
|
|
* or 0 to disable
|
|
|
|
|
* PLL output Q (48M1) clock frequency = VCO frequency / PLLQ,
|
|
|
|
|
* PLLQ = 2, 4, 6, or 8,
|
|
|
|
|
* or 0 to disable
|
|
|
|
|
* PLL output R (CLK) clock frequency = VCO frequency / PLLR,
|
|
|
|
|
* PLLR = 2, 4, 6, or 8,
|
|
|
|
|
* or 0 to disable
|
2016-03-10 18:21:35 +01:00
|
|
|
|
*
|
|
|
|
|
* PLL output P is used for SAI
|
|
|
|
|
* PLL output Q is used for OTG FS, SDMMC, RNG
|
|
|
|
|
* PLL output R is used for SYSCLK
|
|
|
|
|
* PLLP = 0 (not used)
|
|
|
|
|
* PLLQ = 0 (not used)
|
|
|
|
|
* PLLR = 2
|
|
|
|
|
* PLLN = 10
|
|
|
|
|
* PLLM = 1
|
|
|
|
|
*
|
|
|
|
|
* We will configure like this
|
|
|
|
|
*
|
|
|
|
|
* PLL source is HSI
|
|
|
|
|
*
|
|
|
|
|
* PLL_REF = STM32L4_HSI_FREQUENCY / PLLM
|
|
|
|
|
* = 16,000,000 / 1
|
|
|
|
|
* = 16,000,000
|
|
|
|
|
*
|
|
|
|
|
* PLL_VCO = PLL_REF * PLLN
|
|
|
|
|
* = 16,000,000 * 10
|
|
|
|
|
* = 160,000,000
|
|
|
|
|
*
|
|
|
|
|
* PLL_CLK = PLL_VCO / PLLR
|
|
|
|
|
* = 160,000,000 / 2 = 80,000,000
|
|
|
|
|
* PLL_48M1 = disabled
|
|
|
|
|
* PLL_SAI3 = disabled
|
|
|
|
|
*
|
|
|
|
|
* ----------------------------------------
|
|
|
|
|
*
|
|
|
|
|
* PLLSAI1 Configuration
|
|
|
|
|
*
|
|
|
|
|
* The clock input and M divider are identical to the main PLL.
|
|
|
|
|
* However the multiplier and postscalers are independent.
|
|
|
|
|
* The PLLSAI1 is configured only if CONFIG_STM32L4_SAI1PLL is defined
|
|
|
|
|
*
|
|
|
|
|
* SAI1VCO input frequency = PLL input clock frequency
|
2021-03-20 13:01:22 +01:00
|
|
|
|
* SAI1VCO output frequency = SAI1VCO input frequency × PLLSAI1N,
|
|
|
|
|
* 8 <= PLLSAI1N <= 86,
|
|
|
|
|
* frequency range 64 to 344 MHz
|
|
|
|
|
* SAI1PLL output P (SAI1) clock frequency = SAI1VCO frequency / PLLSAI1P,
|
|
|
|
|
* PLLP = 7, or 17,
|
|
|
|
|
* or 0 to disable
|
|
|
|
|
* SAI1PLL output Q (48M2) clock frequency = SAI1VCO frequency / PLLSAI1Q,
|
|
|
|
|
* PLLQ = 2, 4, 6, or 8,
|
|
|
|
|
* or 0 to disable
|
|
|
|
|
* SAI1PLL output R (ADC1) clock frequency = SAI1VCO frequency / PLLSAI1R,
|
|
|
|
|
* PLLR = 2, 4, 6, or 8,
|
|
|
|
|
* or 0 to disable
|
2016-03-10 18:21:35 +01:00
|
|
|
|
*
|
|
|
|
|
* We will configure like this
|
2017-06-28 21:21:20 +02:00
|
|
|
|
*
|
2016-03-10 18:21:35 +01:00
|
|
|
|
* PLLSAI1 disabled
|
|
|
|
|
*
|
|
|
|
|
* ----------------------------------------
|
|
|
|
|
*
|
|
|
|
|
* PLLSAI2 Configuration
|
|
|
|
|
*
|
|
|
|
|
* The clock input and M divider are identical to the main PLL.
|
|
|
|
|
* However the multiplier and postscalers are independent.
|
|
|
|
|
* The PLLSAI2 is configured only if CONFIG_STM32L4_SAI2PLL is defined
|
|
|
|
|
*
|
|
|
|
|
* SAI2VCO input frequency = PLL input clock frequency
|
2021-03-20 13:01:22 +01:00
|
|
|
|
* SAI2VCO output frequency = SAI2VCO input frequency × PLLSAI2N,
|
|
|
|
|
* 8 <= PLLSAI1N <= 86,
|
|
|
|
|
* frequency range 64 to 344 MHz
|
|
|
|
|
* SAI2PLL output P (SAI2) clock frequency = SAI2VCO frequency / PLLSAI2P,
|
|
|
|
|
* PLLP = 7, or 17,
|
|
|
|
|
* or 0 to disable
|
|
|
|
|
* SAI2PLL output R (ADC2) clock frequency = SAI2VCO frequency / PLLSAI2R,
|
|
|
|
|
* PLLR = 2, 4, 6, or 8,
|
|
|
|
|
* or 0 to disable
|
2016-03-10 18:21:35 +01:00
|
|
|
|
*
|
|
|
|
|
* We will configure like this
|
2017-06-28 21:21:20 +02:00
|
|
|
|
*
|
2016-03-10 18:21:35 +01:00
|
|
|
|
* PLLSAI2 disabled
|
|
|
|
|
*
|
|
|
|
|
* ----------------------------------------
|
|
|
|
|
*
|
2021-03-20 13:01:22 +01:00
|
|
|
|
* TODO:
|
|
|
|
|
* The STM32L is a low power peripheral and all these clocks should be
|
|
|
|
|
* configurable at runtime.
|
2016-03-10 18:21:35 +01:00
|
|
|
|
*
|
|
|
|
|
* ----------------------------------------
|
|
|
|
|
*
|
2021-03-20 13:01:22 +01:00
|
|
|
|
* TODO These clock sources can be configured in Kconfig
|
|
|
|
|
* (this is not a board feature)
|
2016-03-10 18:21:35 +01:00
|
|
|
|
* USART1
|
|
|
|
|
* USART2
|
|
|
|
|
* USART3
|
|
|
|
|
* UART4
|
|
|
|
|
* UART5
|
|
|
|
|
* LPUART1
|
|
|
|
|
* I2C1
|
|
|
|
|
* I2C2
|
|
|
|
|
* I2C3
|
|
|
|
|
* LPTIM1
|
|
|
|
|
* LPTIM2
|
|
|
|
|
* SAI1
|
|
|
|
|
* SAI2
|
|
|
|
|
* CLK48
|
|
|
|
|
* ADC
|
|
|
|
|
* SWPMI
|
|
|
|
|
* DFSDM
|
|
|
|
|
*/
|
|
|
|
|
|
2019-10-28 00:21:32 +01:00
|
|
|
|
/* Prescaler common to all PLL inputs; will be 1 (XXX source is implicitly
|
|
|
|
|
* as per comment above HSI) .
|
|
|
|
|
*/
|
2016-03-30 22:28:50 +02:00
|
|
|
|
|
2016-03-10 18:21:35 +01:00
|
|
|
|
#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1)
|
2016-03-30 22:28:50 +02:00
|
|
|
|
|
|
|
|
|
/* 'main' PLL config; we use this to generate our system clock via the R
|
|
|
|
|
* output. We set it up as 16 MHz / 1 * 10 / 2 = 80 MHz
|
|
|
|
|
*
|
2021-03-20 13:01:22 +01:00
|
|
|
|
* XXX NOTE:
|
|
|
|
|
* currently the main PLL is implicitly turned on and is implicitly
|
|
|
|
|
* the system clock; this should be configurable since not all
|
|
|
|
|
* applications may want things done this way.
|
2016-03-30 22:28:50 +02:00
|
|
|
|
*/
|
|
|
|
|
|
2016-03-10 18:21:35 +01:00
|
|
|
|
#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(10)
|
|
|
|
|
#define STM32L4_PLLCFG_PLLP 0
|
|
|
|
|
#undef STM32L4_PLLCFG_PLLP_ENABLED
|
2016-03-26 00:44:32 +01:00
|
|
|
|
#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2
|
|
|
|
|
#define STM32L4_PLLCFG_PLLQ_ENABLED
|
2016-03-10 18:21:35 +01:00
|
|
|
|
#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR(2)
|
|
|
|
|
#define STM32L4_PLLCFG_PLLR_ENABLED
|
|
|
|
|
|
2016-03-30 22:28:50 +02:00
|
|
|
|
/* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't
|
|
|
|
|
* do that with the main PLL's N value. We set N = 12, and enable
|
|
|
|
|
* the Q output (ultimately for CLK48) with /4. So,
|
|
|
|
|
* 16 MHz / 1 * 12 / 4 = 48 MHz
|
|
|
|
|
*
|
|
|
|
|
* XXX NOTE: currently the SAIPLL /must/ be explicitly selected in the
|
|
|
|
|
* menuconfig, or else all this is a moot point, and the various 48 MHz
|
|
|
|
|
* peripherals will not work (RNG at present). I would suggest removing
|
|
|
|
|
* that option from Kconfig altogether, and simply making it an option
|
|
|
|
|
* that is selected via a #define here, like all these other params.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12)
|
2016-03-10 18:21:35 +01:00
|
|
|
|
#define STM32L4_PLLSAI1CFG_PLLP 0
|
|
|
|
|
#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED
|
2016-03-26 00:44:32 +01:00
|
|
|
|
#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4
|
|
|
|
|
#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED
|
2016-03-30 22:28:50 +02:00
|
|
|
|
#define STM32L4_PLLSAI1CFG_PLLR 0
|
2016-03-10 18:21:35 +01:00
|
|
|
|
#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED
|
|
|
|
|
|
2016-03-30 22:28:50 +02:00
|
|
|
|
/* 'SAIPLL2' is not used in this application */
|
|
|
|
|
|
|
|
|
|
#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8)
|
2016-03-10 18:21:35 +01:00
|
|
|
|
#define STM32L4_PLLSAI2CFG_PLLP 0
|
|
|
|
|
#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED
|
2016-03-30 22:28:50 +02:00
|
|
|
|
#define STM32L4_PLLSAI2CFG_PLLR 0
|
2016-03-10 18:21:35 +01:00
|
|
|
|
#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED
|
|
|
|
|
|
|
|
|
|
#define STM32L4_SYSCLK_FREQUENCY 80000000ul
|
|
|
|
|
|
2016-03-26 00:44:32 +01:00
|
|
|
|
/* CLK48 will come from PLLSAI1 (implicitly Q) */
|
|
|
|
|
|
|
|
|
|
#define STM32L4_USE_CLK48
|
|
|
|
|
#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1
|
|
|
|
|
|
2016-03-30 22:28:50 +02:00
|
|
|
|
/* enable the LSE oscillator, used automatically trim the MSI, and for RTC */
|
|
|
|
|
|
2016-04-30 05:13:32 +02:00
|
|
|
|
#define STM32L4_USE_LSE 1
|
2016-03-30 22:28:50 +02:00
|
|
|
|
|
2016-03-10 18:21:35 +01:00
|
|
|
|
/* AHB clock (HCLK) is SYSCLK (80MHz) */
|
|
|
|
|
|
|
|
|
|
#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
|
|
|
|
|
#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY
|
|
|
|
|
|
|
|
|
|
/* APB1 clock (PCLK1) is HCLK/1 (80MHz) */
|
|
|
|
|
|
|
|
|
|
#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */
|
2019-10-28 00:21:32 +01:00
|
|
|
|
#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1)
|
2016-03-10 18:21:35 +01:00
|
|
|
|
|
|
|
|
|
/* Timers driven from APB1 will be twice PCLK1 */
|
2019-10-28 00:21:32 +01:00
|
|
|
|
|
2016-03-10 18:21:35 +01:00
|
|
|
|
/* REVISIT : this can be configured */
|
|
|
|
|
|
2019-10-28 00:21:32 +01:00
|
|
|
|
#define STM32L4_APB1_TIM2_CLKIN (2 * STM32L4_PCLK1_FREQUENCY)
|
|
|
|
|
#define STM32L4_APB1_TIM3_CLKIN (2 * STM32L4_PCLK1_FREQUENCY)
|
|
|
|
|
#define STM32L4_APB1_TIM4_CLKIN (2 * STM32L4_PCLK1_FREQUENCY)
|
|
|
|
|
#define STM32L4_APB1_TIM5_CLKIN (2 * STM32L4_PCLK1_FREQUENCY)
|
|
|
|
|
#define STM32L4_APB1_TIM6_CLKIN (2 * STM32L4_PCLK1_FREQUENCY)
|
|
|
|
|
#define STM32L4_APB1_TIM7_CLKIN (2 * STM32L4_PCLK1_FREQUENCY)
|
2016-03-10 18:21:35 +01:00
|
|
|
|
|
|
|
|
|
/* APB2 clock (PCLK2) is HCLK (80MHz) */
|
|
|
|
|
|
|
|
|
|
#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */
|
2019-10-28 00:21:32 +01:00
|
|
|
|
#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1)
|
2016-03-10 18:21:35 +01:00
|
|
|
|
|
|
|
|
|
/* Timers driven from APB2 will be twice PCLK2 */
|
2019-10-28 00:21:32 +01:00
|
|
|
|
|
2016-03-10 18:21:35 +01:00
|
|
|
|
/* REVISIT : this can be configured */
|
|
|
|
|
|
|
|
|
|
#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
|
|
|
|
|
#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
|
2017-08-25 15:02:21 +02:00
|
|
|
|
#define STM32L4_APB2_TIM15_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
|
|
|
|
|
#define STM32L4_APB2_TIM16_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
|
|
|
|
|
#define STM32L4_APB2_TIM17_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
|
2016-03-10 18:21:35 +01:00
|
|
|
|
|
|
|
|
|
/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
|
|
|
|
|
* otherwise frequency is 2xAPBx.
|
2017-08-25 15:02:21 +02:00
|
|
|
|
* Note: TIM1,8,15,16,17 are on APB2, others on APB1
|
2016-03-10 18:21:35 +01:00
|
|
|
|
*/
|
2019-10-28 00:21:32 +01:00
|
|
|
|
|
2016-03-10 18:21:35 +01:00
|
|
|
|
/* REVISIT : this can be configured */
|
|
|
|
|
|
|
|
|
|
/* TODO SDMMC */
|
|
|
|
|
|
2016-04-30 05:13:32 +02:00
|
|
|
|
#elif defined(HSE_CLOCK_CONFIG)
|
|
|
|
|
|
2016-04-30 17:04:38 +02:00
|
|
|
|
/* Use the HSE */
|
2016-04-30 05:13:32 +02:00
|
|
|
|
|
|
|
|
|
#define STM32L4_BOARD_USEHSE 1
|
|
|
|
|
|
|
|
|
|
/* XXX sysclk mux = pllclk */
|
|
|
|
|
|
|
|
|
|
/* XXX pll source mux = hse */
|
|
|
|
|
|
2016-04-30 17:04:38 +02:00
|
|
|
|
/* Prescaler common to all PLL inputs */
|
2016-04-30 05:13:32 +02:00
|
|
|
|
|
|
|
|
|
#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1)
|
|
|
|
|
|
|
|
|
|
/* 'main' PLL config; we use this to generate our system clock */
|
|
|
|
|
|
|
|
|
|
#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(20)
|
|
|
|
|
#define STM32L4_PLLCFG_PLLP 0
|
|
|
|
|
#undef STM32L4_PLLCFG_PLLP_ENABLED
|
|
|
|
|
#define STM32L4_PLLCFG_PLLQ 0
|
|
|
|
|
#undef STM32L4_PLLCFG_PLLQ_ENABLED
|
|
|
|
|
#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2
|
|
|
|
|
#define STM32L4_PLLCFG_PLLR_ENABLED
|
|
|
|
|
|
|
|
|
|
/* 'SAIPLL1' is used to generate the 48 MHz clock */
|
|
|
|
|
|
|
|
|
|
#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12)
|
|
|
|
|
#define STM32L4_PLLSAI1CFG_PLLP 0
|
|
|
|
|
#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED
|
|
|
|
|
#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2
|
|
|
|
|
#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED
|
|
|
|
|
#define STM32L4_PLLSAI1CFG_PLLR 0
|
|
|
|
|
#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED
|
|
|
|
|
|
|
|
|
|
/* 'SAIPLL2' is not used in this application */
|
|
|
|
|
|
|
|
|
|
#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8)
|
|
|
|
|
#define STM32L4_PLLSAI2CFG_PLLP 0
|
|
|
|
|
#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED
|
|
|
|
|
#define STM32L4_PLLSAI2CFG_PLLR 0
|
|
|
|
|
#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED
|
|
|
|
|
|
|
|
|
|
#define STM32L4_SYSCLK_FREQUENCY 80000000ul
|
|
|
|
|
|
2016-04-30 17:04:38 +02:00
|
|
|
|
/* Enable CLK48; get it from PLLSAI1 */
|
2016-04-30 05:13:32 +02:00
|
|
|
|
|
|
|
|
|
#define STM32L4_USE_CLK48
|
|
|
|
|
#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1
|
|
|
|
|
|
2016-04-30 17:04:38 +02:00
|
|
|
|
/* Enable LSE (for the RTC) */
|
2016-04-30 05:13:32 +02:00
|
|
|
|
|
|
|
|
|
#define STM32L4_USE_LSE 1
|
|
|
|
|
|
2016-04-30 17:04:38 +02:00
|
|
|
|
/* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */
|
2016-04-30 05:13:32 +02:00
|
|
|
|
|
|
|
|
|
#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
|
|
|
|
|
#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY
|
|
|
|
|
|
2016-04-30 17:04:38 +02:00
|
|
|
|
/* Configure the APB1 prescaler */
|
2016-04-30 05:13:32 +02:00
|
|
|
|
|
|
|
|
|
#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */
|
|
|
|
|
#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1)
|
|
|
|
|
|
|
|
|
|
#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
|
|
|
|
|
#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
|
|
|
|
|
#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
|
|
|
|
|
#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
|
|
|
|
|
#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
|
|
|
|
|
#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
|
|
|
|
|
|
2016-04-30 17:04:38 +02:00
|
|
|
|
/* Configure the APB2 prescaler */
|
2016-04-30 05:13:32 +02:00
|
|
|
|
|
|
|
|
|
#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */
|
|
|
|
|
#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1)
|
|
|
|
|
|
|
|
|
|
#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
|
|
|
|
|
#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
|
2017-08-25 15:02:21 +02:00
|
|
|
|
#define STM32L4_APB2_TIM15_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
|
|
|
|
|
#define STM32L4_APB2_TIM16_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
|
|
|
|
|
#define STM32L4_APB2_TIM17_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
|
2016-04-30 05:13:32 +02:00
|
|
|
|
|
|
|
|
|
#elif defined(MSI_CLOCK_CONFIG)
|
|
|
|
|
|
2016-04-30 17:04:38 +02:00
|
|
|
|
/* Use the MSI; frequ = 4 MHz; autotrim from LSE */
|
2016-04-30 05:13:32 +02:00
|
|
|
|
|
|
|
|
|
#define STM32L4_BOARD_USEMSI 1
|
|
|
|
|
#define STM32L4_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M
|
|
|
|
|
|
|
|
|
|
/* XXX sysclk mux = pllclk */
|
|
|
|
|
|
|
|
|
|
/* XXX pll source mux = msi */
|
|
|
|
|
|
|
|
|
|
/* prescaler common to all PLL inputs */
|
|
|
|
|
|
|
|
|
|
#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1)
|
|
|
|
|
|
|
|
|
|
/* 'main' PLL config; we use this to generate our system clock */
|
|
|
|
|
|
|
|
|
|
#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(40)
|
|
|
|
|
#define STM32L4_PLLCFG_PLLP 0
|
|
|
|
|
#undef STM32L4_PLLCFG_PLLP_ENABLED
|
|
|
|
|
#define STM32L4_PLLCFG_PLLQ 0
|
|
|
|
|
#undef STM32L4_PLLCFG_PLLQ_ENABLED
|
|
|
|
|
#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2
|
|
|
|
|
#define STM32L4_PLLCFG_PLLR_ENABLED
|
|
|
|
|
|
|
|
|
|
/* 'SAIPLL1' is used to generate the 48 MHz clock */
|
|
|
|
|
|
|
|
|
|
#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24)
|
|
|
|
|
#define STM32L4_PLLSAI1CFG_PLLP 0
|
|
|
|
|
#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED
|
|
|
|
|
#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2
|
|
|
|
|
#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED
|
|
|
|
|
#define STM32L4_PLLSAI1CFG_PLLR 0
|
|
|
|
|
#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED
|
|
|
|
|
|
|
|
|
|
/* 'SAIPLL2' is not used in this application */
|
|
|
|
|
|
|
|
|
|
#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8)
|
|
|
|
|
#define STM32L4_PLLSAI2CFG_PLLP 0
|
|
|
|
|
#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED
|
|
|
|
|
#define STM32L4_PLLSAI2CFG_PLLR 0
|
|
|
|
|
#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED
|
|
|
|
|
|
|
|
|
|
#define STM32L4_SYSCLK_FREQUENCY 80000000ul
|
|
|
|
|
|
2016-04-30 17:04:38 +02:00
|
|
|
|
/* Enable CLK48; get it from PLLSAI1 */
|
2016-04-30 05:13:32 +02:00
|
|
|
|
|
|
|
|
|
#define STM32L4_USE_CLK48
|
|
|
|
|
#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1
|
|
|
|
|
|
2016-04-30 17:04:38 +02:00
|
|
|
|
/* Enable LSE (for the RTC) */
|
2016-04-30 05:13:32 +02:00
|
|
|
|
|
|
|
|
|
#define STM32L4_USE_LSE 1
|
|
|
|
|
|
2016-04-30 17:04:38 +02:00
|
|
|
|
/* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */
|
2016-04-30 05:13:32 +02:00
|
|
|
|
|
|
|
|
|
#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
|
|
|
|
|
#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY
|
|
|
|
|
|
2016-04-30 17:04:38 +02:00
|
|
|
|
/* Configure the APB1 prescaler */
|
2016-04-30 05:13:32 +02:00
|
|
|
|
|
|
|
|
|
#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */
|
|
|
|
|
#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1)
|
|
|
|
|
|
|
|
|
|
#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
|
|
|
|
|
#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
|
|
|
|
|
#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
|
|
|
|
|
#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
|
|
|
|
|
#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
|
|
|
|
|
#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
|
|
|
|
|
|
2016-04-30 17:04:38 +02:00
|
|
|
|
/* Configure the APB2 prescaler */
|
2016-04-30 05:13:32 +02:00
|
|
|
|
|
|
|
|
|
#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */
|
|
|
|
|
#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1)
|
|
|
|
|
|
|
|
|
|
#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
|
|
|
|
|
#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
|
2017-08-25 15:02:21 +02:00
|
|
|
|
#define STM32L4_APB2_TIM15_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
|
|
|
|
|
#define STM32L4_APB2_TIM16_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
|
|
|
|
|
#define STM32L4_APB2_TIM17_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
|
2016-04-30 05:13:32 +02:00
|
|
|
|
|
|
|
|
|
#endif
|
|
|
|
|
|
2016-07-08 23:39:55 +02:00
|
|
|
|
/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
|
|
|
|
|
* otherwise frequency is 2xAPBx.
|
|
|
|
|
* Note: TIM1,8,15,16,17 are on APB2, others on APB1
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#define BOARD_TIM1_FREQUENCY STM32L4_HCLK_FREQUENCY
|
|
|
|
|
#define BOARD_TIM2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2)
|
|
|
|
|
#define BOARD_TIM3_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2)
|
|
|
|
|
#define BOARD_TIM4_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2)
|
|
|
|
|
#define BOARD_TIM5_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2)
|
|
|
|
|
#define BOARD_TIM6_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2)
|
|
|
|
|
#define BOARD_TIM7_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2)
|
|
|
|
|
#define BOARD_TIM8_FREQUENCY STM32L4_HCLK_FREQUENCY
|
|
|
|
|
#define BOARD_TIM15_FREQUENCY STM32L4_HCLK_FREQUENCY
|
|
|
|
|
#define BOARD_TIM16_FREQUENCY STM32L4_HCLK_FREQUENCY
|
|
|
|
|
#define BOARD_TIM17_FREQUENCY STM32L4_HCLK_FREQUENCY
|
2019-10-28 00:21:32 +01:00
|
|
|
|
#define STM32L4_LPTIM1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2)
|
|
|
|
|
#define STM32L4_LPTIM2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2)
|
2016-07-08 23:39:55 +02:00
|
|
|
|
|
2019-08-19 17:16:08 +02:00
|
|
|
|
/****************************************************************************
|
2016-03-10 18:21:35 +01:00
|
|
|
|
* Public Data
|
2019-08-19 17:16:08 +02:00
|
|
|
|
****************************************************************************/
|
2016-03-10 18:21:35 +01:00
|
|
|
|
|
|
|
|
|
#ifndef __ASSEMBLY__
|
|
|
|
|
|
|
|
|
|
#undef EXTERN
|
|
|
|
|
#if defined(__cplusplus)
|
|
|
|
|
#define EXTERN extern "C"
|
|
|
|
|
extern "C"
|
|
|
|
|
{
|
|
|
|
|
#else
|
|
|
|
|
#define EXTERN extern
|
|
|
|
|
#endif
|
|
|
|
|
|
2019-08-19 17:16:08 +02:00
|
|
|
|
/****************************************************************************
|
2016-03-10 18:21:35 +01:00
|
|
|
|
* Public Function Prototypes
|
2019-08-19 17:16:08 +02:00
|
|
|
|
****************************************************************************/
|
2016-03-10 18:21:35 +01:00
|
|
|
|
|
|
|
|
|
#undef EXTERN
|
|
|
|
|
#if defined(__cplusplus)
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#endif /* __ASSEMBLY__ */
|
2020-01-31 19:07:39 +01:00
|
|
|
|
#endif /* __BOARDS_ARM_STM32L4_NUCLEO_L476RG_INCLUDE_NUCLEO_L476RG_H */
|