2019-08-15 18:19:17 +02:00
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/****************************************************************************
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2020-03-07 12:36:39 +01:00
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* boards/arm/sama5/sama5d3-xplained/include/board_sdram.h
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2014-03-30 00:51:06 +01:00
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*
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2020-03-07 12:36:39 +01:00
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* Copyright (C) 2014 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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2014-03-30 00:51:06 +01:00
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*
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2020-03-07 12:36:39 +01:00
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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2014-03-30 00:51:06 +01:00
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*
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2020-03-07 12:36:39 +01:00
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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2014-03-30 00:51:06 +01:00
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*
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2019-08-15 18:19:17 +02:00
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****************************************************************************/
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2014-03-30 00:51:06 +01:00
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2019-08-15 18:19:17 +02:00
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#ifndef __BOARDS_ARM_SAMA5_SAMA5D3_XPLAINED_INCLUDE_BOARD_SDRAM_H
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#define __BOARDS_ARM_SAMA5_SAMA5D3_XPLAINED_INCLUDE_BOARD_SDRAM_H
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2014-03-30 00:51:06 +01:00
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2019-08-15 18:19:17 +02:00
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/****************************************************************************
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2014-03-30 00:51:06 +01:00
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* Included Files
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2019-08-15 18:19:17 +02:00
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****************************************************************************/
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2014-03-30 00:51:06 +01:00
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#include <nuttx/config.h>
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#include "sam_pmc.h"
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2019-08-15 18:19:17 +02:00
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/****************************************************************************
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2015-04-08 17:15:17 +02:00
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* Pre-processor Definitions
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2019-08-15 18:19:17 +02:00
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****************************************************************************/
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2014-03-30 00:51:06 +01:00
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2019-08-15 18:19:17 +02:00
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/* Clocking *****************************************************************/
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/* After power-on reset, the SAMA5 device is running on a 12MHz internal RC.
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* When booting from SDRAM, NuttX is loaded in SDRAM by an intermediate
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* bootloader.
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* That bootloader had to have already configured the PLL and SDRAM for
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* proper operation.
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*
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* In this case, we do not reconfigure the clocking.
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* Rather, we need to query the register settings to determine the clock
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* frequencies.
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* We can only assume that the Main clock source is the on-board 12MHz
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* crystal.
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*/
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2014-08-03 18:17:50 +02:00
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#define BOARD_MAINCK_FREQUENCY BOARD_MAINOSC_FREQUENCY
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#define BOARD_PLLA_FREQUENCY (sam_pllack_frequency(BOARD_MAINOSC_FREQUENCY))
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#define BOARD_PLLADIV2_FREQUENCY (sam_plladiv2_frequency(BOARD_MAINOSC_FREQUENCY))
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#define BOARD_PCK_FREQUENCY (sam_pck_frequency(BOARD_MAINOSC_FREQUENCY))
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#define BOARD_MCK_FREQUENCY (sam_mck_frequency(BOARD_MAINOSC_FREQUENCY))
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2014-06-20 19:40:36 +02:00
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/* On some SAMA5's, the clocking to peripherals may be divided down from MCK,
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* but not for the SAMA5D3.
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*/
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2014-07-29 15:12:36 +02:00
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#define BOARD_PIT_FREQUENCY BOARD_MCK_FREQUENCY
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#define BOARD_USART_FREQUENCY BOARD_MCK_FREQUENCY
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2014-03-30 00:51:06 +01:00
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#if defined(CONFIG_SAMA5_EHCI) || defined(CONFIG_SAMA5_OHCI) || \
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defined(CONFIG_SAMA5_UDPHS)
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/* The USB Host High Speed requires a 480 MHz clock (UPLLCK) for the embedded
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* High-speed transceivers. UPLLCK is the output of the 480 MHz UTMI PLL
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* (UPLL). The source clock of the UTMI PLL is the Main OSC output: Either
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* the 12MHz internal RC oscillator on a an external 12MHz crystal. The
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* Main OSC must be 12MHz because the UPLL has a built-in 40x multiplier.
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*
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* For High-speed operations, the user has to perform the following:
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*
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* 1) Enable UHP peripheral clock, bit (1 << AT91C_ID_UHPHS) in
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* PMC_PCER register.
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* 2) Write CKGR_PLLCOUNT field in PMC_UCKR register.
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* 3) Enable UPLL, bit AT91C_CKGR_UPLLEN in PMC_UCKR register.
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* 4) Wait until UTMI_PLL is locked. LOCKU bit in PMC_SR register
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* 5) Enable BIAS, bit AT91C_CKGR_BIASEN in PMC_UCKR register.
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* 6) Select UPLLCK as Input clock of OHCI part, USBS bit in PMC_USB
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* register.
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* 7) Program the OHCI clocks (UHP48M and UHP12M) with USBDIV field in
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* PMC_USB register. USBDIV must be 9 (division by 10) if UPLLCK is
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* selected.
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* 8) Enable OHCI clocks, UHP bit in PMC_SCER register.
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*
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* Steps 2 through 7 performed here. 1 and 8 are performed in the EHCI
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* driver is initialized.
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*/
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# define BOARD_USE_UPLL 1 /* Use UPLL for clock source */
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# define BOARD_CKGR_UCKR_UPLLCOUNT (15) /* Maximum value */
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# define BOARD_CKGR_UCKR_BIASCOUNT (15) /* Maximum value */
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2014-07-03 20:28:11 +02:00
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/* REVISIT: The divisor of 10 produces a rate that is too high. Division
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* by 5, however, seems to work just fine. No idea why?
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*/
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# define BOARD_UPLL_OHCI_DIV (5) /* Divide by 5 */
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#endif
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/* ADC Configuration
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*
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* ADCClock = MCK / ((PRESCAL+1) * 2)
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* PRESCAL = (MCK / (2 * ADCClock) - 1)
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*/
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#define BOARD_ADCCLK_FREQUENCY (8000000) /* ADCCLK: MCK / ((7+1)*2) */
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#define BOARD_ADCCLK_FREQUENCY \
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((BOARD_PLLADIV2_FREQUENCY / (2 *BOARD_PLLADIV2_FREQUENCY)) - 1)
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#define BOARD_ADC_PRESCAL (7)
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#define BOARD_TSD_STARTUP (40) /* 40 nanoseconds */
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#define BOARD_TSD_TRACKTIM (2000) /* Min 1<>s at 8MHz */
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#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (units nanoseconds) */
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/* HSMCI clocking
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*
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* Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK)
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* divided by (2*(CLKDIV) + CLOCKODD + 2).
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*
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* CLKFULLDIV = 2*CLKDIV + CLOCKODD;
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* MCI_SPEED = MCK / (CLKFULLDIV + 2)
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* CLKFULLDIV = MCK / MCI_SPEED - 2
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*
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* CLKDIV = CLKFULLDIV >> 1
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* CLOCKODD = CLKFULLDIV & 1
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*
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* Where CLKDIV has a range of 0-255.
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*/
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/* Initial clock: 400 KHz (target) */
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#define HSMCI_INIT_CLKDIV sam_hsmci_clkdiv(400000)
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/* MMC transfer clock: 20 MHz (target) */
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#define HSMCI_MMCXFR_CLKDIV sam_hsmci_clkdiv(20000000)
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/* SD transfer clock: 25 MHz (target) */
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#define HSMCI_SDXFR_CLKDIV sam_hsmci_clkdiv(25000000)
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#define HSMCI_SDWIDEXFR_CLKDIV HSMCI_SDXFR_CLKDIV
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2019-08-15 18:19:17 +02:00
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/****************************************************************************
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2014-03-30 00:51:06 +01:00
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* Public Data
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****************************************************************************/
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2014-03-30 00:51:06 +01:00
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#ifndef __ASSEMBLY__
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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2019-08-15 18:19:17 +02:00
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/****************************************************************************
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2014-03-30 00:51:06 +01:00
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* Public Function Prototypes
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2019-08-15 18:19:17 +02:00
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****************************************************************************/
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2014-03-30 00:51:06 +01:00
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#undef EXTERN
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#if defined(__cplusplus)
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}
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#endif
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#endif /* !__ASSEMBLY__ */
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2020-01-31 19:07:39 +01:00
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#endif /* __BOARDS_ARM_SAMA5_SAMA5D3_XPLAINED_INCLUDE_BOARD_SDRAM_H */
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