sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Initialize global mutext/sem by NXMUTEX_INITIALIZER and SEM_INITIALIZER

Browse Source 
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
This commit is contained in:
anjiahao 2022-09-06 14:18:45 +08:00 committed by Masayuki Ishikawa
parent 9f029194e1
commit d07792a343
225 changed files with 1930 additions and 2163 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
arch/arm/src/cxd56xx/cxd56_adc.c
View File

@ -223,6 +223,7 @@ static struct cxd56adc_dev_s g_lpadc0priv =
.wm = NULL,
.filter = NULL,
.notify = NULL,
.lock = NXMUTEX_INITIALIZER,
.crefs = 0,
};
#endif
@ -239,6 +240,7 @@ static struct cxd56adc_dev_s g_lpadc1priv =
.wm = NULL,
.filter = NULL,
.notify = NULL,
.lock = NXMUTEX_INITIALIZER,
.crefs = 0,
};
#endif
@ -255,6 +257,7 @@ static struct cxd56adc_dev_s g_lpadc2priv =
.wm = NULL,
.filter = NULL,
.notify = NULL,
.lock = NXMUTEX_INITIALIZER,
.crefs = 0,
};
#endif
@ -271,6 +274,7 @@ static struct cxd56adc_dev_s g_lpadc3priv =
.wm = NULL,
.filter = NULL,
.notify = NULL,
.lock = NXMUTEX_INITIALIZER,
.crefs = 0,
};
#endif
@ -287,6 +291,7 @@ static struct cxd56adc_dev_s g_hpadc0priv =
.wm = NULL,
.filter = NULL,
.notify = NULL,
.lock = NXMUTEX_INITIALIZER,
.crefs = 0,
};
#endif
@ -303,6 +308,7 @@ static struct cxd56adc_dev_s g_hpadc1priv =
.wm = NULL,
.filter = NULL,
.notify = NULL,
.lock = NXMUTEX_INITIALIZER,
.crefs = 0,
};
#endif
@ -1107,9 +1113,8 @@ int cxd56_adcinitialize(void)
aerr("Failed to register driver(lpadc0): %d\n", ret);
return ret;
}
nxmutex_init(&g_lpadc0priv.lock);
#endif
#if defined (CONFIG_CXD56_LPADC1) || defined (CONFIG_CXD56_LPADC0_1) || defined (CONFIG_CXD56_LPADC_ALL)
ret = register_driver("/dev/lpadc1", &g_adcops, 0666, &g_lpadc1priv);
if (ret < 0)
@ -1117,9 +1122,8 @@ int cxd56_adcinitialize(void)
aerr("Failed to register driver(lpadc1): %d\n", ret);
return ret;
}
nxmutex_init(&g_lpadc1priv.lock);
#endif
#if defined (CONFIG_CXD56_LPADC2) || defined (CONFIG_CXD56_LPADC_ALL)
ret = register_driver("/dev/lpadc2", &g_adcops, 0666, &g_lpadc2priv);
if (ret < 0)
@ -1127,9 +1131,8 @@ int cxd56_adcinitialize(void)
aerr("Failed to register driver(lpadc2): %d\n", ret);
return ret;
}
nxmutex_init(&g_lpadc2priv.lock);
#endif
#if defined (CONFIG_CXD56_LPADC3) || defined (CONFIG_CXD56_LPADC_ALL)
ret = register_driver("/dev/lpadc3", &g_adcops, 0666, &g_lpadc3priv);
if (ret < 0)
@ -1137,9 +1140,8 @@ int cxd56_adcinitialize(void)
aerr("Failed to register driver(lpadc3): %d\n", ret);
return ret;
}
nxmutex_init(&g_lpadc3priv.lock);
#endif
#ifdef CONFIG_CXD56_HPADC0
ret = register_driver("/dev/hpadc0", &g_adcops, 0666, &g_hpadc0priv);
if (ret < 0)
@ -1147,9 +1149,8 @@ int cxd56_adcinitialize(void)
aerr("Failed to register driver(hpadc0): %d\n", ret);
return ret;
}
nxmutex_init(&g_hpadc0priv.lock);
#endif
#ifdef CONFIG_CXD56_HPADC1
ret = register_driver("/dev/hpadc1", &g_adcops, 0666, &g_hpadc1priv);
if (ret < 0)
@ -1157,8 +1158,6 @@ int cxd56_adcinitialize(void)
aerr("Failed to register driver(hpadc1): %d\n", ret);
return ret;
}
nxmutex_init(&g_hpadc1priv.lock);
#endif
return ret;

9
arch/arm/src/cxd56xx/cxd56_charger.c
View File

@ -103,7 +103,10 @@ static const struct file_operations g_chargerops =
#endif
};
static struct charger_dev_s g_chargerdev;
static struct charger_dev_s g_chargerdev =
{
.batlock = NXMUTEX_INITIALIZER,
};
/****************************************************************************
* Private Functions
@ -621,10 +624,6 @@ int cxd56_charger_initialize(const char *devpath)
struct charger_dev_s *priv = &g_chargerdev;
int ret;
/* Initialize the CXD5247 device structure */
nxmutex_init(&priv->batlock);
/* Register battery driver */
ret = register_driver(devpath, &g_chargerops, 0666, priv);

4
arch/arm/src/cxd56xx/cxd56_dmac.c
View File

@ -290,7 +290,7 @@ struct dma_channel_s
/* This is the array of all DMA channels */
static struct dma_channel_s g_dmach[NCHANNELS];
static mutex_t g_dmalock;
static mutex_t g_dmalock = NXMUTEX_INITIALIZER;
static int dma_init(int ch);
static int dma_uninit(int ch);
@ -726,8 +726,6 @@ void weak_function arm_dma_initialize(void)
g_dmach[i].chan = i;
up_enable_irq(irq_map[i]);
}
nxmutex_init(&g_dmalock);
}
/****************************************************************************

11
arch/arm/src/cxd56xx/cxd56_emmc.c
View File

@ -137,8 +137,11 @@ static const struct block_operations g_bops =
NULL /* ioctl */
};
static sem_t g_waitsem;
struct cxd56_emmc_state_s g_emmcdev;
static sem_t g_waitsem = SEM_INITIALIZER(0);
struct cxd56_emmc_state_s g_emmcdev =
{
.lock = NXMUTEX_INITIALIZER,
};
/****************************************************************************
* Private Functions
@ -939,10 +942,6 @@ int cxd56_emmcinitialize(void)
priv = &g_emmcdev;
memset(priv, 0, sizeof(struct cxd56_emmc_state_s));
nxmutex_init(&priv->lock);
nxsem_init(&g_waitsem, 0, 0);
ret = emmc_hwinitialize();
if (ret != OK)
{

7
arch/arm/src/cxd56xx/cxd56_farapi.c
View File

@ -113,8 +113,8 @@ extern struct modulelist_s _image_modlist_base[];
* Private Data
****************************************************************************/
static sem_t g_farwait;
static mutex_t g_farlock;
static sem_t g_farwait = SEM_INITIALIZER(0);
static mutex_t g_farlock = NXMUTEX_INITIALIZER;
static struct pm_cpu_wakelock_s g_wlock =
{
.count = 0,
@ -288,10 +288,7 @@ void cxd56_farapiinitialize(void)
PANIC();
# endif
}
#endif
nxmutex_init(&g_farlock);
nxsem_init(&g_farwait, 0, 0);
cxd56_iccinit(CXD56_PROTO_MBX);
cxd56_iccinit(CXD56_PROTO_FLG);

9
arch/arm/src/cxd56xx/cxd56_gauge.c
View File

@ -88,7 +88,10 @@ static const struct file_operations g_gaugeops =
#endif
};
static struct bat_gauge_dev_s g_gaugedev;
static struct bat_gauge_dev_s g_gaugedev =
{
.batlock = NXMUTEX_INITIALIZER,
};
/****************************************************************************
* Private Functions
@ -345,10 +348,6 @@ int cxd56_gauge_initialize(const char *devpath)
struct bat_gauge_dev_s *priv = &g_gaugedev;
int ret;
/* Initialize the CXD5247 device structure */
nxmutex_init(&priv->batlock);
/* Register battery driver */
ret = register_driver(devpath, &g_gaugeops, 0666, priv);

11
arch/arm/src/cxd56xx/cxd56_ge2d.c
View File

@ -64,8 +64,8 @@ static const struct file_operations g_ge2dfops =
.ioctl = ge2d_ioctl
};
static sem_t g_wait;
static mutex_t g_lock;
static sem_t g_wait = SEM_INITIALIZER(0);
static mutex_t g_lock = NXMUTEX_INITIALIZER;
/****************************************************************************
* Private Functions
@ -184,9 +184,6 @@ int cxd56_ge2dinitialize(const char *devname)
{
int ret;
nxmutex_init(&g_lock);
nxsem_init(&g_wait, 0, 0);
ret = register_driver(devname, &g_ge2dfops, 0666, NULL);
if (ret != 0)
{
@ -215,9 +212,5 @@ void cxd56_ge2duninitialize(const char *devname)
irq_detach(CXD56_IRQ_GE2D);
cxd56_img_ge2d_clock_disable();
nxmutex_destroy(&g_lock);
nxsem_destroy(&g_wait);
unregister_driver(devname);
}

9
arch/arm/src/cxd56xx/cxd56_hostif.c
View File

@ -130,7 +130,10 @@ static int hif_unlink(struct inode *inode);
/* Host interface driver */
static struct cxd56_hifdrv_s g_hifdrv;
static struct cxd56_hifdrv_s g_hifdrv =
{
.sync = SEM_INITIALIZER(0),
};
/* Host interface operations */
@ -379,8 +382,6 @@ static int hif_initialize(struct hostif_buff_s *buffer)
DEBUGASSERT(buffer);
memset(drv, 0, sizeof(struct cxd56_hifdrv_s));
/* Get the number of devices */
for (num = 0; num < MAX_BUFFER_NUM; num++)
@ -441,8 +442,6 @@ static int hif_initialize(struct hostif_buff_s *buffer)
cxd56_iccinit(CXD56_PROTO_HOSTIF);
nxsem_init(&drv->sync, 0, 0);
ret = cxd56_iccregisterhandler(CXD56_PROTO_HOSTIF, hif_rxhandler, NULL);
return ret;

33
arch/arm/src/cxd56xx/cxd56_powermgr.c
View File

@ -166,10 +166,10 @@ static int cxd56_pmmsghandler(int cpuid, int protoid, uint32_t pdata,
static struct cxd56_pm_target_id_s g_target_id_table;
static struct file g_queuedesc;
static sem_t g_bootsync;
static mutex_t g_regcblock;
static mutex_t g_freqlock;
static sem_t g_freqlockwait;
static sem_t g_bootsync = SEM_INITIALIZER(0);
static mutex_t g_regcblock = NXMUTEX_INITIALIZER;
static mutex_t g_freqlock = NXMUTEX_INITIALIZER;
static sem_t g_freqlockwait = SEM_INITIALIZER(0);
static dq_queue_t g_cbqueue;
static sq_queue_t g_freqlockqueue;
static sq_queue_t g_wakelockqueue;
@ -818,36 +818,11 @@ int cxd56_pm_hotsleep(int idletime)
int cxd56_pm_initialize(void)
{
int taskid;
int ret;
dq_init(&g_cbqueue);
sq_init(&g_freqlockqueue);
sq_init(&g_wakelockqueue);
ret = nxmutex_init(&g_regcblock);
if (ret < 0)
{
return ret;
}
ret = nxmutex_init(&g_freqlock);
if (ret < 0)
{
return ret;
}
ret = nxsem_init(&g_freqlockwait, 0, 0);
if (ret < 0)
{
return ret;
}
ret = nxsem_init(&g_bootsync, 0, 0);
if (ret < 0)
{
return ret;
}
taskid = task_create("cxd56_pm_task", CXD56_PM_TASK_PRIO,
CXD56_PM_TASK_STACKSIZE, cxd56_pm_maintask,
NULL);

36
arch/arm/src/cxd56xx/cxd56_scu.c
View File

@ -315,7 +315,17 @@ static void seq_handleisopdoneintr(struct cxd56_scudev_s *priv,
* Private Data
****************************************************************************/
struct cxd56_scudev_s g_scudev;
struct cxd56_scudev_s g_scudev =
{
.syncwait = SEM_INITIALIZER(0),
.synclock = NXMUTEX_INITIALIZER,
.oneshotwait =
{
SEM_INITIALIZER(0),
SEM_INITIALIZER(0),
SEM_INITIALIZER(0),
},
};
/****************************************************************************
* Public Data
@ -3417,23 +3427,10 @@ void seq_close(struct seq_s *seq)
void scu_initialize(void)
{
struct cxd56_scudev_s *priv = &g_scudev;
int i;
#ifdef CONFIG_CXD56_UDMAC
cxd56_udmainitialize();
#endif
memset(priv, 0, sizeof(struct cxd56_scudev_s));
nxmutex_init(&priv->synclock);
nxsem_init(&priv->syncwait, 0, 0);
for (i = 0; i < 3; i++)
{
nxsem_init(&priv->oneshotwait[i], 0, 0);
}
scufifo_initialize();
/**
@ -3486,9 +3483,6 @@ void scu_initialize(void)
void scu_uninitialize(void)
{
struct cxd56_scudev_s *priv = &g_scudev;
int i;
/* Request don't sleep */
seq_inhibitrequest(REQ_SLEEP, true);
@ -3496,12 +3490,4 @@ void scu_uninitialize(void)
up_disable_irq(CXD56_IRQ_SCU_3);
cxd56_scuseq_clock_disable();
nxsem_destroy(&priv->syncwait);
nxmutex_destroy(&priv->synclock);
for (i = 0; i < 3; i++)
{
nxsem_destroy(&priv->oneshotwait[i]);
}
}

5
arch/arm/src/cxd56xx/cxd56_sdhci.c
View File

@ -464,6 +464,7 @@ struct cxd56_sdiodev_s g_sdhcdev =
.dmasendsetup = cxd56_sdio_sendsetup,
#endif
},
.waitsem = SEM_INITIALIZER(0),
};
/* Register logging support */
@ -1315,10 +1316,6 @@ static void cxd56_sdio_sdhci_reset(struct sdio_dev_s *dev)
/* Initialize the SDHC slot structure data structure */
/* Initialize semaphores */
nxsem_init(&priv->waitsem, 0, 0);
/* The next phase of the hardware reset would be to set the SYSCTRL INITA
* bit to send 80 clock ticks for card to power up and then reset the card
* with CMD0. This is done elsewhere.

38
arch/arm/src/cxd56xx/cxd56_spi.c
View File

@ -77,7 +77,6 @@ struct cxd56_spidev_s
uint8_t port; /* Port number */
int initialized; /* Initialized flag */
#ifdef CONFIG_CXD56_DMAC
bool dmaenable; /* Use DMA or not */
DMA_HANDLE rxdmach; /* RX DMA channel handle */
DMA_HANDLE txdmach; /* TX DMA channel handle */
sem_t dmasem; /* Wait for DMA to complete */
@ -188,6 +187,10 @@ static struct cxd56_spidev_s g_spi4dev =
.initialized = 0,
#ifdef CONFIG_CXD56_SPI_INTERRUPTS
.spiirq = CXD56_IRQ_IMG_SPI,
#endif
.lock = NXMUTEX_INITIALIZER,
#ifdef CONFIG_CXD56_DMAC
.dmasem = SEM_INITIALIZER(0),
#endif
};
@ -231,6 +234,10 @@ static struct cxd56_spidev_s g_spi5dev =
.initialized = 0,
#ifdef CONFIG_CXD56_SPI_INTERRUPTS
.spiirq = CXD56_IRQ_IMG_WSPI,
#endif
.lock = NXMUTEX_INITIALIZER,
#ifdef CONFIG_CXD56_DMAC
.dmasem = SEM_INITIALIZER(0),
#endif
};
#endif
@ -273,6 +280,10 @@ static struct cxd56_spidev_s g_spi0dev =
.initialized = 0,
#ifdef CONFIG_CXD56_SPI_INTERRUPTS
.spiirq = CXD56_IRQ_SPIM,
#endif
.lock = NXMUTEX_INITIALIZER,
#ifdef CONFIG_CXD56_DMAC
.dmasem = SEM_INITIALIZER(0),
#endif
};
#endif
@ -315,6 +326,10 @@ static struct cxd56_spidev_s g_spi3dev =
.initialized = 0,
#ifdef CONFIG_CXD56_SPI_INTERRUPTS
.spiirq = CXD56_IRQ_SCU_SPI,
#endif
.lock = NXMUTEX_INITIALIZER,
#ifdef CONFIG_CXD56_DMAC
.dmasem = SEM_INITIALIZER(0),
#endif
};
#endif
@ -863,15 +878,13 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
void *rxbuffer, size_t nwords)
{
#ifdef CONFIG_CXD56_DMAC
struct cxd56_spidev_s *priv = (struct cxd56_spidev_s *)dev;
#ifdef CONFIG_CXD56_SPI_DMATHRESHOLD
size_t dmath = CONFIG_CXD56_SPI_DMATHRESHOLD;
#else
size_t dmath = 0;
#endif
if (priv->dmaenable && dmath < nwords)
if (dmath < nwords)
{
spi_dmaexchange(dev, txbuffer, rxbuffer, nwords);
}
@ -1204,7 +1217,6 @@ struct spi_dev_s *cxd56_spibus_initialize(int port)
/* DMA settings */
#ifdef CONFIG_CXD56_DMAC
priv->dmaenable = false;
priv->txdmach = NULL;
priv->rxdmach = NULL;
#endif
@ -1244,10 +1256,6 @@ struct spi_dev_s *cxd56_spibus_initialize(int port)
spi_setfrequency((struct spi_dev_s *)priv, 400000);
/* Initialize the SPI mutex that enforces mutually exclusive access */
nxmutex_init(&priv->lock);
#ifdef CONFIG_CXD56_SPI3_SCUSEQ
/* Enable the SPI, but not enable port 3 when SCU support enabled.
* Because this enabler will be controlled by SCU.
@ -1328,12 +1336,6 @@ void cxd56_spi_dmaconfig(int port, int chtype, DMA_HANDLE handle,
priv->txdmach = handle;
memcpy(&priv->txconfig, conf, sizeof(dma_config_t));
if (!priv->dmaenable)
{
nxsem_init(&priv->dmasem, 0, 0);
priv->dmaenable = true;
}
}
else if ((chtype == CXD56_SPI_DMAC_CHTYPE_RX) && (!priv->rxdmach))
{
@ -1341,12 +1343,6 @@ void cxd56_spi_dmaconfig(int port, int chtype, DMA_HANDLE handle,
priv->rxdmach = handle;
memcpy(&priv->rxconfig, conf, sizeof(dma_config_t));
if (!priv->dmaenable)
{
nxsem_init(&priv->dmasem, 0, 0);
priv->dmaenable = true;
}
}
}
}

9
arch/arm/src/cxd56xx/cxd56_sysctl.c
View File

@ -66,8 +66,8 @@ static int sysctl_rxhandler(int cpuid, int protoid,
* Private Data
****************************************************************************/
static mutex_t g_lock;
static sem_t g_sync;
static mutex_t g_lock = NXMUTEX_INITIALIZER;
static sem_t g_sync = SEM_INITIALIZER(0);
static int g_errcode = 0;
static const struct file_operations g_sysctlfops =
@ -159,11 +159,6 @@ int cxd56_sysctlcmd(uint8_t id, uint32_t data)
void cxd56_sysctlinitialize(void)
{
cxd56_iccinit(CXD56_PROTO_SYSCTL);
nxmutex_init(&g_lock);
nxsem_init(&g_sync, 0, 0);
cxd56_iccregisterhandler(CXD56_PROTO_SYSCTL, sysctl_rxhandler, NULL);
register_driver("/dev/sysctl", &g_sysctlfops, 0666, NULL);
}

5
arch/arm/src/cxd56xx/cxd56_uart0.c
View File

@ -97,7 +97,7 @@ static const struct file_operations g_uart0fops =
.write = uart0_write
};
static mutex_t g_lock;
static mutex_t g_lock = NXMUTEX_INITIALIZER;
/****************************************************************************
* Private Functions
@ -233,8 +233,6 @@ int cxd56_uart0initialize(const char *devname)
{
int ret;
nxmutex_init(&g_lock);
ret = register_driver(devname, &g_uart0fops, 0666, NULL);
if (ret != 0)
{
@ -251,7 +249,6 @@ int cxd56_uart0initialize(const char *devname)
void cxd56_uart0uninitialize(const char *devname)
{
unregister_driver(devname);
nxmutex_destroy(&g_lock);
}
#endif /* CONFIG_CXD56_UART0 */

9
arch/arm/src/cxd56xx/cxd56_udmac.c
View File

@ -78,7 +78,11 @@ struct dma_controller_s
/* This is the overall state of the DMA controller */
static struct dma_controller_s g_dmac;
static struct dma_controller_s g_dmac =
{
.lock = NXMUTEX_INITIALIZER,
.chansem = SEM_INITIALIZER(CXD56_DMA_NCHANNELS),
};
/* This is the array of all DMA channels */
@ -239,9 +243,6 @@ void cxd56_udmainitialize(void)
/* Initialize the channel list */
nxmutex_init(&g_dmac.lock);
nxsem_init(&g_dmac.chansem, 0, CXD56_DMA_NCHANNELS);
for (i = 0; i < CXD56_DMA_NCHANNELS; i++)
{
g_dmach[i].chan = i;

9
arch/arm/src/efm32/efm32_dma.c
View File

@ -78,7 +78,11 @@ struct dma_controller_s
/* This is the overall state of the DMA controller */
static struct dma_controller_s g_dmac;
static struct dma_controller_s g_dmac =
{
.lock = NXMUTEX_INITIALIZER,
.chansem = SEM_INITIALIZER(EFM32_DMA_NCHANNELS),
};
/* This is the array of all DMA channels */
@ -266,9 +270,6 @@ void weak_function arm_dma_initialize(void)
/* Initialize the channel list */
nxmutex_init(&g_dmac.lock);
nxsem_init(&g_dmac.chansem, 0, EFM32_DMA_NCHANNELS);
for (i = 0; i < EFM32_DMA_NCHANNELS; i++)
{
g_dmach[i].chan = i;

40
arch/arm/src/efm32/efm32_spi.c
View File

@ -226,7 +226,15 @@ static const struct spi_ops_s g_spiops =
#ifdef CONFIG_EFM32_USART0_ISSPI
/* Support for SPI on USART0 */
static struct efm32_spidev_s g_spi0dev;
static struct efm32_spidev_s g_spi0dev =
{
#ifdef CONFIG_EFM32_SPI_DMA
.rxdmasem = SEM_INITIALIZER(0),
.txdmasem = SEM_INITIALIZER(0),
#endif
.lock = NXMUTEX_INITIALIZER,
};
static const struct efm32_spiconfig_s g_spi0config =
{
.base = EFM32_USART0_BASE,
@ -249,7 +257,15 @@ static const struct efm32_spiconfig_s g_spi0config =
#ifdef CONFIG_EFM32_USART1_ISSPI
/* Support for SPI on USART1 */
static struct efm32_spidev_s g_spi1dev;
static struct efm32_spidev_s g_spi1dev =
{
#ifdef CONFIG_EFM32_SPI_DMA
.rxdmasem = SEM_INITIALIZER(0),
.txdmasem = SEM_INITIALIZER(0),
#endif
.lock = NXMUTEX_INITIALIZER,
};
static const struct efm32_spiconfig_s g_spi1config =
{
.base = EFM32_USART1_BASE,
@ -272,7 +288,15 @@ static const struct efm32_spiconfig_s g_spi1config =
#ifdef CONFIG_EFM32_USART2_ISSPI
/* Support for SPI on USART2 */
static struct efm32_spidev_s g_spi2dev;
static struct efm32_spidev_s g_spi2dev =
{
#ifdef CONFIG_EFM32_SPI_DMA
.rxdmasem = SEM_INITIALIZER(0),
.txdmasem = SEM_INITIALIZER(0),
#endif
.lock = NXMUTEX_INITIALIZER,
};
static const struct efm32_spiconfig_s g_spi2config =
{
.base = EFM32_USART2_BASE,
@ -1577,10 +1601,6 @@ static int spi_portinitialize(struct efm32_spidev_s *priv)
spi_putreg(config, EFM32_USART_CMD_OFFSET, USART_CMD_MASTEREN);
/* Initialize the SPI mutex that enforces mutually exclusive access */
nxmutex_init(&priv->lock);
#ifdef CONFIG_EFM32_SPI_DMA
/* Allocate two DMA channels... one for the RX and one for the TX side of
* the transfer.
@ -1601,12 +1621,6 @@ static int spi_portinitialize(struct efm32_spidev_s *priv)
port);
goto errout_with_rxdmach;
}
/* Initialized semaphores used to wait for DMA completion */
nxsem_init(&priv->rxdmasem, 0, 0);
nxsem_init(&priv->txdmasem, 0, 0);
#endif
/* Enable SPI */

11
arch/arm/src/efm32/efm32_usbhost.c
View File

@ -484,7 +484,11 @@ static inline int efm32_hw_initialize(struct efm32_usbhost_s *priv);
* single global instance.
*/
static struct efm32_usbhost_s g_usbhost;
static struct efm32_usbhost_s g_usbhost =
{
.lock = NXMUTEX_INITIALIZER,
.pscsem = SEM_INITIALIZER(0),
};
/* This is the connection/enumeration interface */
@ -5259,11 +5263,6 @@ static inline void efm32_sw_initialize(struct efm32_usbhost_s *priv)
usbhost_devaddr_initialize(&priv->rhport);
/* Initialize semaphores & mutex */
nxsem_init(&priv->pscsem, 0, 0);
nxmutex_init(&priv->lock);
/* Initialize the driver state data */
priv->smstate = SMSTATE_DETACHED;

18
arch/arm/src/gd32f4/gd32f4xx_dma.c
View File

@ -90,82 +90,98 @@ static struct gd32_dma_channel_s g_dmachan[DMA_NCHANNELS] =
{
.chan_num = GD32_DMA_CH0,
.irq = GD32_IRQ_DMA0_CHANNEL0,
.chsem = SEM_INITIALIZER(1),
.dmabase = GD32_DMA0,
},
{
.chan_num = GD32_DMA_CH1,
.irq = GD32_IRQ_DMA0_CHANNEL1,
.chsem = SEM_INITIALIZER(1),
.dmabase = GD32_DMA0,
},
{
.chan_num = GD32_DMA_CH2,
.irq = GD32_IRQ_DMA0_CHANNEL2,
.chsem = SEM_INITIALIZER(1),
.dmabase = GD32_DMA0,
},
{
.chan_num = GD32_DMA_CH3,
.irq = GD32_IRQ_DMA0_CHANNEL3,
.chsem = SEM_INITIALIZER(1),
.dmabase = GD32_DMA0,
},
{
.chan_num = GD32_DMA_CH4,
.irq = GD32_IRQ_DMA0_CHANNEL4,
.chsem = SEM_INITIALIZER(1),
.dmabase = GD32_DMA0,
},
{
.chan_num = GD32_DMA_CH5,
.irq = GD32_IRQ_DMA0_CHANNEL5,
.chsem = SEM_INITIALIZER(1),
.dmabase = GD32_DMA0,
},
{
.chan_num = GD32_DMA_CH6,
.irq = GD32_IRQ_DMA0_CHANNEL6,
.chsem = SEM_INITIALIZER(1),
.dmabase = GD32_DMA0,
},
{
.chan_num = GD32_DMA_CH7,
.irq = GD32_IRQ_DMA0_CHANNEL7,
.chsem = SEM_INITIALIZER(1),
.dmabase = GD32_DMA0,
},
{
.chan_num = GD32_DMA_CH0,
.irq = GD32_IRQ_DMA1_CHANNEL0,
.chsem = SEM_INITIALIZER(1),
.dmabase = GD32_DMA1,
},
{
.chan_num = GD32_DMA_CH1,
.irq = GD32_IRQ_DMA1_CHANNEL1,
.chsem = SEM_INITIALIZER(1),
.dmabase = GD32_DMA1,
},
{
.chan_num = GD32_DMA_CH2,
.irq = GD32_IRQ_DMA1_CHANNEL2,
.chsem = SEM_INITIALIZER(1),
.dmabase = GD32_DMA1,
},
{
.chan_num = GD32_DMA_CH3,
.irq = GD32_IRQ_DMA1_CHANNEL3,
.chsem = SEM_INITIALIZER(1),
.dmabase = GD32_DMA1,
},
{
.chan_num = GD32_DMA_CH4,
.irq = GD32_IRQ_DMA1_CHANNEL4,
.chsem = SEM_INITIALIZER(1),
.dmabase = GD32_DMA1,
},
{
.chan_num = GD32_DMA_CH5,
.irq = GD32_IRQ_DMA1_CHANNEL5,
.chsem = SEM_INITIALIZER(1),
.dmabase = GD32_DMA1,
},
{
.chan_num = GD32_DMA_CH6,
.irq = GD32_IRQ_DMA1_CHANNEL6,
.chsem = SEM_INITIALIZER(1),
.dmabase = GD32_DMA1,
},
{
.chan_num = GD32_DMA_CH7,
.irq = GD32_IRQ_DMA1_CHANNEL7,
.chsem = SEM_INITIALIZER(1),
.dmabase = GD32_DMA1,
},
};
@ -517,8 +533,6 @@ void weak_function arm_dma_initialize(void)
DEBUGASSERT(dmachan != NULL);
nxsem_init(&dmachan->chsem, 0, 1);
/* Attach DMA interrupt vectors */
irq_attach(dmachan->irq, gd32_dma_interrupt, dmachan);

30
arch/arm/src/gd32f4/gd32f4xx_spi.c
View File

@ -298,6 +298,7 @@ static struct gd32_spidev_s g_spi0dev =
},
.spibase = GD32_SPI0,
.spiclock = GD32_PCLK2_FREQUENCY,
.lock = NXMUTEX_INITIALIZER,
#ifdef CONFIG_GD32F4_SPI_INTERRUPT
.spiirq = GD32_IRQ_SPI0,
#endif
@ -314,6 +315,8 @@ static struct gd32_spidev_s g_spi0dev =
.rxch = 0,
.txch = 0,
# endif
.rxsem = SEM_INITIALIZER(0),
.txsem = SEM_INITIALIZER(0),
#endif
};
#endif
@ -363,6 +366,7 @@ static struct gd32_spidev_s g_spi1dev =
},
.spibase = GD32_SPI1,
.spiclock = GD32_PCLK1_FREQUENCY,
.lock = NXMUTEX_INITIALIZER,
#ifdef CONFIG_GD32F4_SPI_INTERRUPT
.spiirq = GD32_IRQ_SPI1,
#endif
@ -379,6 +383,8 @@ static struct gd32_spidev_s g_spi1dev =
.rxch = 0,
.txch = 0,
# endif
.rxsem = SEM_INITIALIZER(0),
.txsem = SEM_INITIALIZER(0),
#endif
};
#endif
@ -428,6 +434,7 @@ static struct gd32_spidev_s g_spi2dev =
},
.spibase = GD32_SPI2,
.spiclock = GD32_PCLK1_FREQUENCY,
.lock = NXMUTEX_INITIALIZER,
#ifdef CONFIG_GD32F4_SPI_INTERRUPT
.spiirq = GD32_IRQ_SPI2,
#endif
@ -444,6 +451,8 @@ static struct gd32_spidev_s g_spi2dev =
.rxch = 0,
.txch = 0,
# endif
.rxsem = SEM_INITIALIZER(0),
.txsem = SEM_INITIALIZER(0),
#endif
};
#endif
@ -493,6 +502,7 @@ static struct gd32_spidev_s g_spi3dev =
},
.spibase = GD32_SPI3,
.spiclock = GD32_PCLK2_FREQUENCY,
.lock = NXMUTEX_INITIALIZER,
#ifdef CONFIG_GD32F4_SPI_INTERRUPT
.spiirq = GD32_IRQ_SPI3,
#endif
@ -509,6 +519,8 @@ static struct gd32_spidev_s g_spi3dev =
.rxch = 0,
.txch = 0,
# endif
.rxsem = SEM_INITIALIZER(0),
.txsem = SEM_INITIALIZER(0),
#endif
};
#endif
@ -558,6 +570,7 @@ static struct gd32_spidev_s g_spi4dev =
},
.spibase = GD32_SPI4,
.spiclock = GD32_PCLK2_FREQUENCY,
.lock = NXMUTEX_INITIALIZER,
#ifdef CONFIG_GD32F4_SPI_INTERRUPT
.spiirq = GD32_IRQ_SPI4,
#endif
@ -574,6 +587,8 @@ static struct gd32_spidev_s g_spi4dev =
.rxch = 0,
.txch = 0,
# endif
.rxsem = SEM_INITIALIZER(0),
.txsem = SEM_INITIALIZER(0),
#endif
};
#endif
@ -623,6 +638,7 @@ static struct gd32_spidev_s g_spi5dev =
},
.spibase = GD32_SPI5,
.spiclock = GD32_PCLK2_FREQUENCY,
.lock = NXMUTEX_INITIALIZER,
#ifdef CONFIG_GD32F5_SPI_INTERRUPT
.spiirq = GD32_IRQ_SPI5,
#endif
@ -639,6 +655,8 @@ static struct gd32_spidev_s g_spi5dev =
.rxch = 0,
.txch = 0,
# endif
.rxsem = SEM_INITIALIZER(0),
.txsem = SEM_INITIALIZER(0),
#endif
};
#endif
@ -2041,23 +2059,11 @@ static void spi_bus_initialize(struct gd32_spidev_s *priv)
spi_setfrequency((struct spi_dev_s *)priv, 400000);
/* Initialize the SPI lock that enforces mutually exclusive access */
nxmutex_init(&priv->lock);
#ifdef CONFIG_GD32F4_SPI_DMA
/* Initialize the SPI semaphores that is used to wait for DMA completion.
* This semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
if (priv->rxch && priv->txch)
{
if (priv->txdma == NULL && priv->rxdma == NULL)
{
nxsem_init(&priv->rxsem, 0, 0);
nxsem_init(&priv->txsem, 0, 0);
/* Get DMA channels */
priv->rxdma = gd32_dma_channel_alloc(priv->rxch);

9
arch/arm/src/imx1/imx_spi.c
View File

@ -209,7 +209,9 @@ static struct imx_spidev_s g_spidev[] =
{
.ops = &g_spiops,
.base = IMX_CSPI1_VBASE,
.lock = NXMUTEX_INITIALIZER,
#ifndef CONFIG_SPI_POLLWAIT
.waitsem = SEM_INITIALIZER(0),
.irq = IMX_IRQ_CSPI1,
#endif
},
@ -218,7 +220,9 @@ static struct imx_spidev_s g_spidev[] =
{
.ops = &g_spiops,
.base = IMX_CSPI2_VBASE,
.lock = NXMUTEX_INITIALIZER,
#ifndef CONFIG_SPI_POLLWAIT
.waitsem = SEM_INITIALIZER(0),
.irq = IMX_IRQ_CSPI2,
#endif
},
@ -1108,11 +1112,6 @@ struct spi_dev_s *imx_spibus_initialize(int port)
/* Initialize the state structure */
#ifndef CONFIG_SPI_POLLWAIT
nxsem_init(&priv->waitsem, 0, 0);
#endif
nxmutex_init(&priv->lock);
/* Initialize control register:
* min frequency, ignore ready, master mode, mode=0, 8-bit
*/

17
arch/arm/src/imx6/imx_ecspi.c
View File

@ -268,7 +268,9 @@ static struct imx_spidev_s g_spidev[] =
.ops = &g_spiops,
.base = IMX_ECSPI1_VBASE,
.spindx = SPI1_NDX,
.lock = NXMUTEX_INITIALIZER,
#ifndef CONFIG_SPI_POLLWAIT
.waitsem = SEM_INITIALIZER(0),
.irq = IMX_IRQ_ECSPI1,
#endif
.select = imx_spi1select,
@ -284,7 +286,9 @@ static struct imx_spidev_s g_spidev[] =
.ops = &g_spiops,
.base = IMX_ECSPI2_VBASE,
.spindx = SPI2_NDX,
.lock = NXMUTEX_INITIALIZER,
#ifndef CONFIG_SPI_POLLWAIT
.waitsem = SEM_INITIALIZER(0),
.irq = IMX_IRQ_ECSPI2,
#endif
.select = imx_spi2select,
@ -300,7 +304,9 @@ static struct imx_spidev_s g_spidev[] =
.ops = &g_spiops,
.base = IMX_ECSPI3_VBASE,
.spindx = SPI3_NDX,
.lock = NXMUTEX_INITIALIZER,
#ifndef CONFIG_SPI_POLLWAIT
.waitsem = SEM_INITIALIZER(0),
.irq = IMX_IRQ_ECSPI3,
#endif
.select = imx_spi3select,
@ -316,7 +322,9 @@ static struct imx_spidev_s g_spidev[] =
.ops = &g_spiops,
.base = IMX_ECSPI4_VBASE,
.spindx = SPI4_NDX,
.lock = NXMUTEX_INITIALIZER,
#ifndef CONFIG_SPI_POLLWAIT
.waitsem = SEM_INITIALIZER(0),
.irq = IMX_IRQ_ECSPI4,
#endif
.select = imx_spi4select,
@ -332,7 +340,9 @@ static struct imx_spidev_s g_spidev[] =
.ops = &g_spiops,
.base = IMX_ECSPI5_VBASE,
.spindx = SPI5_NDX,
.lock = NXMUTEX_INITIALIZER,
#ifndef CONFIG_SPI_POLLWAIT
.waitsem = SEM_INITIALIZER(0),
.irq = IMX_IRQ_ECSPI5,
#endif
.select = imx_spi5select,
@ -1282,13 +1292,6 @@ struct spi_dev_s *imx_spibus_initialize(int port)
/* Initialize the state structure */
/* Initialize Semaphores */
#ifndef CONFIG_SPI_POLLWAIT
nxsem_init(&priv->waitsem, 0, 0);
#endif
nxmutex_init(&priv->lock);
/* Initialize control register:
* min frequency, ignore ready, master mode, mode=0, 8-bit
*/

14
arch/arm/src/imxrt/imxrt_edma.c
View File

@ -155,7 +155,13 @@ struct imxrt_edma_s
/* The state of the eDMA */
static struct imxrt_edma_s g_edma;
static struct imxrt_edma_s g_edma =
{
.chlock = NXMUTEX_INITIALIZER,
#if CONFIG_IMXRT_EDMA_NTCD > 0
.dsem = SEM_INITIALIZER(CONFIG_IMXRT_EDMA_NTCD),
#endif
};
#if CONFIG_IMXRT_EDMA_NTCD > 0
/* This is a singly-linked list of free TCDs */
@ -740,18 +746,12 @@ void weak_function arm_dma_initialize(void)
/* Initialize data structures */
memset(&g_edma, 0, sizeof(struct imxrt_edma_s));
for (i = 0; i < IMXRT_EDMA_NCHANNELS; i++)
{
g_edma.dmach[i].chan = i;
}
/* Initialize mutex & semaphores */
nxmutex_init(&g_edma.chlock);
#if CONFIG_IMXRT_EDMA_NTCD > 0
nxsem_init(&g_edma.dsem, 0, CONFIG_IMXRT_EDMA_NTCD);
/* Initialize the list of free TCDs from the pool of pre-allocated TCDs. */
imxrt_tcd_initialize();

16
arch/arm/src/imxrt/imxrt_ehci.c
View File

@ -567,7 +567,12 @@ static int imxrt_reset(void);
* single global instance.
*/
static struct imxrt_ehci_s g_ehci;
static struct imxrt_ehci_s g_ehci =
{
.lock = NXMUTEX_INITIALIZER,
.pscsem = SEM_INITIALIZER(0),
.ep0.iocsem = SEM_INITIALIZER(1),
};
/* This is the connection/enumeration interface */
@ -4993,15 +4998,6 @@ struct usbhost_connection_s *imxrt_ehci_initialize(int controller)
usbhost_vtrace1(EHCI_VTRACE1_INITIALIZING, 0);
/* Initialize the EHCI state data structure */
nxmutex_init(&g_ehci.lock);
nxsem_init(&g_ehci.pscsem, 0, 0);
/* Initialize EP0 */
nxsem_init(&g_ehci.ep0.iocsem, 0, 1);
/* Initialize the root hub port structures */
for (i = 0; i < IMXRT_EHCI_NRHPORT; i++)

8
arch/arm/src/imxrt/imxrt_enc.c
View File

@ -403,6 +403,7 @@ static struct imxrt_enc_lowerhalf_s imxrt_enc1_priv =
.ops = &g_qecallbacks,
.config = &imxrt_enc1_config,
.data = &imxrt_enc1_data,
.lock = NXMUTEX_INITIALIZER,
};
#endif
@ -441,6 +442,7 @@ static struct imxrt_enc_lowerhalf_s imxrt_enc2_priv =
.ops = &g_qecallbacks,
.config = &imxrt_enc2_config,
.data = &imxrt_enc2_data,
.lock = NXMUTEX_INITIALIZER,
};
#endif
@ -479,6 +481,7 @@ static struct imxrt_enc_lowerhalf_s imxrt_enc3_priv =
.ops = &g_qecallbacks,
.config = &imxrt_enc3_config,
.data = &imxrt_enc3_data,
.lock = NXMUTEX_INITIALIZER,
};
#endif
@ -517,6 +520,7 @@ static struct imxrt_enc_lowerhalf_s imxrt_enc4_priv =
.ops = &g_qecallbacks,
.config = &imxrt_enc4_config,
.data = &imxrt_enc4_data,
.lock = NXMUTEX_INITIALIZER,
};
#endif
@ -1225,10 +1229,6 @@ int imxrt_qeinitialize(const char *devpath, int enc)
return -ENODEV;
}
/* Initialize private data */
nxmutex_init(&priv->lock);
/* Register the upper-half driver */
int ret = qe_register(devpath, (struct qe_lowerhalf_s *)priv);

7
arch/arm/src/imxrt/imxrt_flexspi.c
View File

@ -113,6 +113,7 @@ static struct imxrt_flexspidev_s g_flexspi0dev =
.ops = &g_flexspi0ops,
},
.base = (struct flexspi_type_s *) IMXRT_FLEXSPIC_BASE,
.lock = NXMUTEX_INITIALIZER,
};
#define FREQ_1MHz (1000000ul)
@ -1268,12 +1269,6 @@ struct flexspi_dev_s *imxrt_flexspi_initialize(int intf)
{
/* No perform one time initialization */
/* Initialize the FlexSPI mutex that enforces mutually exclusive
* access to the FlexSPI registers.
*/
nxmutex_init(&priv->lock);
/* Perform hardware initialization. Puts the FlexSPI into an active
* state.
*/

24
arch/arm/src/imxrt/imxrt_lpspi.c
View File

@ -248,9 +248,12 @@ static struct imxrt_lpspidev_s g_lpspi1dev =
#ifdef CONFIG_IMXRT_LPSPI_INTERRUPTS
.spiirq = IMXRT_IRQ_LPSPI1,
#endif
.lock = NXMUTEX_INITIALIZER,
#ifdef CONFIG_IMXRT_LPSPI1_DMA
.rxch = IMXRT_DMACHAN_LPSPI1_RX,
.txch = IMXRT_DMACHAN_LPSPI1_TX,
.rxsem = SEM_INITIALIZER(0),
.txsem = SEM_INITIALIZER(0),
#endif
};
#endif
@ -294,9 +297,12 @@ static struct imxrt_lpspidev_s g_lpspi2dev =
#ifdef CONFIG_IMXRT_LPSPI_INTERRUPTS
.spiirq = IMXRT_IRQ_LPSPI2,
#endif
.lock = NXMUTEX_INITIALIZER,
#ifdef CONFIG_IMXRT_LPSPI2_DMA
.rxch = IMXRT_DMACHAN_LPSPI2_RX,
.txch = IMXRT_DMACHAN_LPSPI2_TX,
.rxsem = SEM_INITIALIZER(0),
.txsem = SEM_INITIALIZER(0),
#endif
};
#endif
@ -340,9 +346,12 @@ static struct imxrt_lpspidev_s g_lpspi3dev =
#ifdef CONFIG_IMXRT_LPSPI_INTERRUPTS
.spiirq = IMXRT_IRQ_LPSPI3,
#endif
.lock = NXMUTEX_INITIALIZER,
#ifdef CONFIG_IMXRT_LPSPI3_DMA
.rxch = IMXRT_DMACHAN_LPSPI3_RX,
.txch = IMXRT_DMACHAN_LPSPI3_TX,
.rxsem = SEM_INITIALIZER(0),
.txsem = SEM_INITIALIZER(0),
#endif
};
#endif
@ -386,9 +395,12 @@ static struct imxrt_lpspidev_s g_lpspi4dev =
#ifdef CONFIG_IMXRT_LPSPI_INTERRUPTS
.spiirq = IMXRT_IRQ_LPSPI4,
#endif
.lock = NXMUTEX_INITIALIZER,
#ifdef CONFIG_IMXRT_LPSPI4_DMA
.rxch = IMXRT_DMACHAN_LPSPI4_RX,
.txch = IMXRT_DMACHAN_LPSPI4_TX,
.rxsem = SEM_INITIALIZER(0),
.txsem = SEM_INITIALIZER(0),
#endif
};
#endif
@ -1691,10 +1703,6 @@ static void imxrt_lpspi_bus_initialize(struct imxrt_lpspidev_s *priv)
imxrt_lpspi_setmode((struct spi_dev_s *)priv, SPIDEV_MODE0);
/* Initialize the SPI mutex that enforces mutually exclusive access */
nxmutex_init(&priv->lock);
/* Enable LPSPI */
imxrt_lpspi_modifyreg32(priv, IMXRT_LPSPI_CR_OFFSET, 0, LPSPI_CR_MEN);
@ -2021,18 +2029,10 @@ struct spi_dev_s *imxrt_lpspibus_initialize(int bus)
}
#ifdef CONFIG_IMXRT_LPSPI_DMA
/* Initialize the SPI semaphores that is used to wait for DMA completion.
* This semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
if (priv->rxch && priv->txch)
{
if (priv->txdma == NULL && priv->rxdma == NULL)
{
nxsem_init(&priv->rxsem, 0, 0);
nxsem_init(&priv->txsem, 0, 0);
priv->txdma = imxrt_dmach_alloc(priv->txch | DMAMUX_CHCFG_ENBL,
0);
priv->rxdma = imxrt_dmach_alloc(priv->rxch | DMAMUX_CHCFG_ENBL,

2
arch/arm/src/imxrt/imxrt_rtc_lowerhalf.c
View File

@ -129,6 +129,7 @@ static const struct rtc_ops_s g_rtc_ops =
static struct imxrt_lowerhalf_s g_rtc_lowerhalf =
{
.ops = &g_rtc_ops,
.devlock = NXMUTEX_INITIALIZER,
};
/****************************************************************************
@ -514,7 +515,6 @@ static int imxrt_rdalarm(struct rtc_lowerhalf_s *lower,
struct rtc_lowerhalf_s *imxrt_rtc_lowerhalf(void)
{
nxmutex_init(&g_rtc_lowerhalf.devlock);
return (struct rtc_lowerhalf_s *)&g_rtc_lowerhalf;
}

11
arch/arm/src/imxrt/imxrt_serial.c
View File

@ -846,6 +846,7 @@ static struct imxrt_uart_s g_lpuart1priv =
#ifdef CONFIG_LPUART1_TXDMA
.dma_txreqsrc = IMXRT_DMACHAN_LPUART1_TX,
.txdmasem = SEM_INITIALIZER(1),
#endif
#ifdef CONFIG_LPUART1_RXDMA
.dma_rxreqsrc = IMXRT_DMACHAN_LPUART1_RX,
@ -914,6 +915,7 @@ static struct imxrt_uart_s g_lpuart2priv =
#ifdef CONFIG_LPUART2_TXDMA
.dma_txreqsrc = IMXRT_DMACHAN_LPUART2_TX,
.txdmasem = SEM_INITIALIZER(1),
#endif
#ifdef CONFIG_LPUART2_RXDMA
.dma_rxreqsrc = IMXRT_DMACHAN_LPUART2_RX,
@ -980,6 +982,7 @@ static struct imxrt_uart_s g_lpuart3priv =
#ifdef CONFIG_LPUART3_TXDMA
.dma_txreqsrc = IMXRT_DMACHAN_LPUART3_TX,
.txdmasem = SEM_INITIALIZER(1),
#endif
#ifdef CONFIG_LPUART3_RXDMA
.dma_rxreqsrc = IMXRT_DMACHAN_LPUART3_RX,
@ -1046,6 +1049,7 @@ static struct imxrt_uart_s g_lpuart4priv =
#ifdef CONFIG_LPUART4_TXDMA
.dma_txreqsrc = IMXRT_DMACHAN_LPUART4_TX,
.txdmasem = SEM_INITIALIZER(1),
#endif
#ifdef CONFIG_LPUART4_RXDMA
.dma_rxreqsrc = IMXRT_DMACHAN_LPUART4_RX,
@ -1112,6 +1116,7 @@ static struct imxrt_uart_s g_lpuart5priv =
#ifdef CONFIG_LPUART5_TXDMA
.dma_txreqsrc = IMXRT_DMACHAN_LPUART5_TX,
.txdmasem = SEM_INITIALIZER(1),
#endif
#ifdef CONFIG_LPUART5_RXDMA
.dma_rxreqsrc = IMXRT_DMACHAN_LPUART5_RX,
@ -1178,6 +1183,7 @@ static struct imxrt_uart_s g_lpuart6priv =
#ifdef CONFIG_LPUART6_TXDMA
.dma_txreqsrc = IMXRT_DMACHAN_LPUART6_TX,
.txdmasem = SEM_INITIALIZER(1),
#endif
#ifdef CONFIG_LPUART6_RXDMA
.dma_rxreqsrc = IMXRT_DMACHAN_LPUART6_RX,
@ -1244,6 +1250,7 @@ static struct imxrt_uart_s g_lpuart7priv =
#ifdef CONFIG_LPUART7_TXDMA
.dma_txreqsrc = IMXRT_DMACHAN_LPUART7_TX,
.txdmasem = SEM_INITIALIZER(1),
#endif
#ifdef CONFIG_LPUART7_RXDMA
.dma_rxreqsrc = IMXRT_DMACHAN_LPUART7_RX,
@ -1310,6 +1317,7 @@ static struct imxrt_uart_s g_lpuart8priv =
#ifdef CONFIG_LPUART8_TXDMA
.dma_txreqsrc = IMXRT_DMACHAN_LPUART8_TX,
.txdmasem = SEM_INITIALIZER(1),
#endif
#ifdef CONFIG_LPUART8_RXDMA
.dma_rxreqsrc = IMXRT_DMACHAN_LPUART8_RX,
@ -1457,8 +1465,6 @@ static int imxrt_dma_setup(struct uart_dev_s *dev)
{
return -EBUSY;
}
nxsem_init(&priv->txdmasem, 0, 1);
}
/* Enable Tx DMA for the UART */
@ -1659,7 +1665,6 @@ static void imxrt_dma_shutdown(struct uart_dev_s *dev)
imxrt_dmach_free(priv->txdma);
priv->txdma = NULL;
nxsem_destroy(&priv->txdmasem);
}
#endif
}

11
arch/arm/src/imxrt/imxrt_usdhc.c
View File

@ -422,7 +422,8 @@ struct imxrt_dev_s g_sdhcdev[IMXRT_MAX_SDHC_DEV_SLOTS] =
.dmasendsetup = imxrt_sendsetup,
#endif
#endif
}
},
.waitsem = SEM_INITIALIZER(0),
},
#endif
@ -479,7 +480,8 @@ struct imxrt_dev_s g_sdhcdev[IMXRT_MAX_SDHC_DEV_SLOTS] =
.dmarecvsetup = imxrt_recvsetup,
.dmasendsetup = imxrt_sendsetup,
#endif
}
},
.waitsem = SEM_INITIALIZER(0),
}
#endif
#endif
@ -3215,11 +3217,8 @@ struct sdio_dev_s *imxrt_usdhc_initialize(int slotno)
DEBUGASSERT(slotno < IMXRT_MAX_SDHC_DEV_SLOTS);
struct imxrt_dev_s *priv = &g_sdhcdev[slotno];
/* Initialize the USDHC slot structure data structure
* Initialize semaphores
*/
/* Initialize the USDHC slot structure data structure */
nxsem_init(&priv->waitsem, 0, 0);
switch (priv->addr)
{
case IMXRT_USDHC1_BASE:

14
arch/arm/src/kinetis/kinetis_edma.c
View File

@ -157,7 +157,13 @@ struct kinetis_edma_s
/* The state of the eDMA */
static struct kinetis_edma_s g_edma;
static struct kinetis_edma_s g_edma =
{
.chlock = NXMUTEX_INITIALIZER,
#if CONFIG_KINETIS_EDMA_NTCD > 0
.dsem = SEM_INITIALIZER(CONFIG_KINETIS_EDMA_NTCD),
#endif
};
#if CONFIG_KINETIS_EDMA_NTCD > 0
/* This is a singly-linked list of free TCDs */
@ -721,18 +727,12 @@ void weak_function arm_dma_initialize(void)
/* Initialize data structures */
memset(&g_edma, 0, sizeof(struct kinetis_edma_s));
for (i = 0; i < KINETIS_EDMA_NCHANNELS; i++)
{
g_edma.dmach[i].chan = i;
}
/* Initialize mutex & semaphore */
nxmutex_init(&g_edma.chlock);
#if CONFIG_KINETIS_EDMA_NTCD > 0
nxsem_init(&g_edma.dsem, 0, CONFIG_KINETIS_EDMA_NTCD);
/* Initialize the list of free TCDs from the pool of pre-allocated TCDs. */
kinetis_tcd_initialize();

5
arch/arm/src/kinetis/kinetis_sdhc.c
View File

@ -397,6 +397,7 @@ struct kinetis_dev_s g_sdhcdev =
#endif
#endif
},
.waitsem = SEM_INITIALIZER(0),
};
/* Register logging support */
@ -2851,10 +2852,6 @@ struct sdio_dev_s *sdhc_initialize(int slotno)
/* Initialize the SDHC slot structure data structure */
/* Initialize semaphores */
nxsem_init(&priv->waitsem, 0, 0);
/* In addition to the system clock, the SDHC module needs a clock for the
* base for the external card clock. There are four possible sources for
* this clock, selected by the SIM's SOPT2 register:

20
arch/arm/src/kinetis/kinetis_spi.c
View File

@ -226,6 +226,7 @@ static struct kinetis_spidev_s g_spi0dev =
&g_spi0ops
},
.spibase = KINETIS_SPI0_BASE,
.lock = NXMUTEX_INITIALIZER,
.ctarsel = KINETIS_SPI_CTAR0_OFFSET,
#ifdef CONFIG_KINETIS_SPI_DMA
# ifdef CONFIG_KINETIS_SPI0_DMA
@ -235,6 +236,8 @@ static struct kinetis_spidev_s g_spi0dev =
.rxch = 0,
.txch = 0,
# endif
.rxsem = SEM_INITIALIZER(0),
.txsem = SEM_INITIALIZER(0),
#endif
};
#endif
@ -275,6 +278,7 @@ static struct kinetis_spidev_s g_spi1dev =
&g_spi1ops
},
.spibase = KINETIS_SPI1_BASE,
.lock = NXMUTEX_INITIALIZER,
.ctarsel = KINETIS_SPI_CTAR0_OFFSET,
#ifdef CONFIG_KINETIS_SPI_DMA
# ifdef CONFIG_KINETIS_SPI1_DMA
@ -284,6 +288,8 @@ static struct kinetis_spidev_s g_spi1dev =
.rxch = 0,
.txch = 0,
# endif
.rxsem = SEM_INITIALIZER(0),
.txsem = SEM_INITIALIZER(0),
#endif
};
#endif
@ -324,6 +330,7 @@ static struct kinetis_spidev_s g_spi2dev =
&g_spi2ops
},
.spibase = KINETIS_SPI2_BASE,
.lock = NXMUTEX_INITIALIZER,
.ctarsel = KINETIS_SPI_CTAR0_OFFSET,
#ifdef CONFIG_KINETIS_SPI_DMA
# ifdef CONFIG_KINETIS_SPI2_DMA
@ -333,6 +340,8 @@ static struct kinetis_spidev_s g_spi2dev =
.rxch = 0,
.txch = 0,
# endif
.rxsem = SEM_INITIALIZER(0),
.txsem = SEM_INITIALIZER(0),
#endif
};
#endif
@ -1666,22 +1675,11 @@ struct spi_dev_s *kinetis_spibus_initialize(int port)
priv->frequency = 0;
spi_setfrequency(&priv->spidev, KINETIS_SPI_CLK_INIT);
/* Initialize the SPI mutex that enforces mutually exclusive access */
nxmutex_init(&priv->lock);
#ifdef CONFIG_KINETIS_SPI_DMA
/* Initialize the SPI semaphores that is used to wait for DMA completion.
* This semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
if (priv->rxch && priv->txch)
{
if (priv->txdma == NULL && priv->rxdma == NULL)
{
nxsem_init(&priv->rxsem, 0, 0);
nxsem_init(&priv->txsem, 0, 0);
priv->txdma = kinetis_dmach_alloc(priv->txch | DMAMUX_CHCFG_ENBL,
0);
priv->rxdma = kinetis_dmach_alloc(priv->rxch | DMAMUX_CHCFG_ENBL,

16
arch/arm/src/kinetis/kinetis_usbhshost.c
View File

@ -588,7 +588,12 @@ static int kinetis_reset(void);
* single global instance.
*/
static struct kinetis_ehci_s g_ehci;
static struct kinetis_ehci_s g_ehci =
{
.lock = NXMUTEX_INITIALIZER,
.pscsem = SEM_INITIALIZER(0),
.ep0.iocsem = SEM_INITIALIZER(1),
};
/* This is the connection/enumeration interface */
@ -5067,15 +5072,6 @@ struct usbhost_connection_s *kinetis_ehci_initialize(int controller)
usbhost_vtrace1(EHCI_VTRACE1_INITIALIZING, 0);
/* Initialize the EHCI state data structure */
nxmutex_init(&g_ehci.lock);
nxsem_init(&g_ehci.pscsem, 0, 0);
/* Initialize EP0 */
nxsem_init(&g_ehci.ep0.iocsem, 0, 1);
/* Initialize the root hub port structures */
for (i = 0; i < KINETIS_EHCI_NRHPORT; i++)

6
arch/arm/src/kl/kl_spi.c
View File

@ -126,6 +126,7 @@ static struct kl_spidev_s g_spi0dev =
&g_spi0ops
},
.spibase = KL_SPI0_BASE,
.lock = NXMUTEX_INITIALIZER,
};
#endif
@ -158,6 +159,7 @@ static struct kl_spidev_s g_spi1dev =
&g_spi1ops
},
.spibase = KL_SPI1_BASE,
.lock = NXMUTEX_INITIALIZER,
};
#endif
@ -688,10 +690,6 @@ struct spi_dev_s *kl_spibus_initialize(int port)
/* Select a default frequency of approx. 400KHz */
spi_setfrequency((struct spi_dev_s *)priv, 400000);
/* Initialize the SPI mutex that enforces mutually exclusive access */
nxmutex_init(&priv->lock);
return &priv->spidev;
}

7
arch/arm/src/lc823450/lc823450_dma.c
View File

@ -122,7 +122,10 @@ static int phydmastart(struct lc823450_phydmach_s *pdmach);
* Private Data
****************************************************************************/
static struct lc823450_dma_s g_dma;
static struct lc823450_dma_s g_dma =
{
.lock = NXMUTEX_INITIALIZER,
};
volatile uint8_t g_dma_inprogress;
/****************************************************************************
@ -342,8 +345,6 @@ void arm_dma_initialize(void)
sq_init(&g_dma.phydmach[i].req_q);
}
nxmutex_init(&g_dma.lock);
if (irq_attach(LC823450_IRQ_DMAC, dma_interrupt, NULL) != 0)
{
return;

13
arch/arm/src/lc823450/lc823450_i2s.c
View File

@ -234,12 +234,12 @@ static const struct i2s_ops_s g_i2sops =
};
static DMA_HANDLE _hrxdma;
static sem_t _sem_rxdma;
static sem_t _sem_buf_over;
static sem_t _sem_rxdma = SEM_INITIALIZER(0);
static sem_t _sem_buf_over = SEM_INITIALIZER(0);
static DMA_HANDLE _htxdma;
static sem_t _sem_txdma;
static sem_t _sem_buf_under;
static sem_t _sem_txdma = SEM_INITIALIZER(0);
static sem_t _sem_buf_under = SEM_INITIALIZER(0);
/****************************************************************************
* Public Data
@ -1034,12 +1034,7 @@ struct i2s_dev_s *lc823450_i2sdev_initialize(void)
#endif
_hrxdma = lc823450_dmachannel(DMA_CHANNEL_VIRTUAL);
nxsem_init(&_sem_rxdma, 0, 0);
nxsem_init(&_sem_buf_over, 0, 0);
_htxdma = lc823450_dmachannel(DMA_CHANNEL_VIRTUAL);
nxsem_init(&_sem_txdma, 0, 0);
nxsem_init(&_sem_buf_under, 0, 0);
#ifdef CONFIG_SMP
cpu_set_t cpuset0;

14
arch/arm/src/lc823450/lc823450_sddrv_dep.c
View File

@ -81,9 +81,17 @@
#ifdef CONFIG_LC823450_SDC_DMA
static DMA_HANDLE _hrdma[2];
static sem_t _sem_rwait[2];
static sem_t _sem_rwait[2] =
{
SEM_INITIALIZER(0),
SEM_INITIALIZER(0),
};
static DMA_HANDLE _hwdma[2];
static sem_t _sem_wwait[2];
static sem_t _sem_wwait[2] =
{
SEM_INITIALIZER(0),
SEM_INITIALIZER(0),
};
#endif /* CONFIG_LC823450_SDC_DMA */
static uint64_t _sddep_timeout = (10 * 100); /* 10sec (in tick) */
@ -281,9 +289,7 @@ SINT_T sddep_os_init(struct sddrcfg_s *cfg)
#ifdef CONFIG_LC823450_SDC_DMA
_hrdma[ch] = lc823450_dmachannel(DMA_CHANNEL_VIRTUAL);
nxsem_init(&_sem_rwait[ch], 0, 0);
_hwdma[ch] = lc823450_dmachannel(DMA_CHANNEL_VIRTUAL);
nxsem_init(&_sem_wwait[ch], 0, 0);
#endif /* CONFIG_LC823450_SDC_DMA */
return 0;
}

14
arch/arm/src/lc823450/lc823450_serial.c
View File

@ -253,6 +253,10 @@ static struct up_dev_s g_uart0priv =
.parity = CONFIG_UART0_PARITY,
.bits = CONFIG_UART0_BITS,
.stopbits2 = CONFIG_UART0_2STOP,
#ifdef CONFIG_HSUART
.rxdma_wait = SEM_INITIALIZER(0),
.txdma_wait = SEM_INITIALIZER(1),
#endif
};
static uart_dev_t g_uart0port =
@ -283,6 +287,10 @@ static struct up_dev_s g_uart1priv =
.parity = CONFIG_UART1_PARITY,
.bits = CONFIG_UART1_BITS,
.stopbits2 = CONFIG_UART1_2STOP,
#ifdef CONFIG_HSUART
.rxdma_wait = SEM_INITIALIZER(0),
.txdma_wait = SEM_INITIALIZER(1),
#endif
};
static uart_dev_t g_uart1port =
@ -313,6 +321,10 @@ static struct up_dev_s g_uart2priv =
.parity = CONFIG_UART2_PARITY,
.bits = CONFIG_UART2_BITS,
.stopbits2 = CONFIG_UART2_2STOP,
#ifdef CONFIG_HSUART
.rxdma_wait = SEM_INITIALIZER(0),
.txdma_wait = SEM_INITIALIZER(1),
#endif
};
static uart_dev_t g_uart2port =
@ -1329,11 +1341,9 @@ void arm_serialinit(void)
#ifdef TTYS1_DEV
uart_register("/dev/ttyS1", &TTYS1_DEV);
#ifdef CONFIG_HSUART
nxsem_init(&g_uart1priv.txdma_wait, 0, 1);
g_uart1priv.htxdma = lc823450_dmachannel(DMA_CHANNEL_UART1TX);
lc823450_dmarequest(g_uart1priv.htxdma, DMA_REQUEST_UART1TX);
nxsem_init(&g_uart1priv.rxdma_wait, 0, 0);
g_uart1priv.hrxdma = lc823450_dmachannel(DMA_CHANNEL_UART1RX);
lc823450_dmarequest(g_uart1priv.hrxdma, DMA_REQUEST_UART1RX);

11
arch/arm/src/lc823450/lc823450_spi.c
View File

@ -130,6 +130,12 @@ static struct lc823450_spidev_s g_spidev =
{
&g_spiops
},
#ifndef CONFIG_SPI_OWNBUS
.lock = NXMUTEX_INITIALIZER,
#endif
#ifdef CONFIG_LC823450_SPI_DMA
.dma_wait = SEM_INITIALIZER(0),
#endif
};
/****************************************************************************
@ -523,10 +529,6 @@ struct spi_dev_s *lc823450_spibus_initialize(int port)
modifyreg32(MCLKCNTAPB, 0, MCLKCNTAPB_PORT5_CLKEN);
modifyreg32(MRSTCNTAPB, 0, MRSTCNTAPB_PORT5_RSTB);
#ifndef CONFIG_SPI_OWNBUS
nxmutex_init(&priv->lock);
#endif
/* Initialize SPI mode. It must be done before starting SPI transfer */
/* PO: SPI Mode3 (default) */
@ -543,7 +545,6 @@ struct spi_dev_s *lc823450_spibus_initialize(int port)
lc823450_spiinitialize();
#ifdef CONFIG_LC823450_SPI_DMA
nxsem_init(&priv->dma_wait, 0, 0);
priv->hdma = lc823450_dmachannel(DMA_CHANNEL_SIOTX);
lc823450_dmarequest(priv->hdma, DMA_REQUEST_SIOTX);

5
arch/arm/src/lc823450/lc823450_usbdev.c
View File

@ -189,7 +189,7 @@ extern int lc823450_dvfs_boost(int timeout);
static struct lc823450_usbdev_s g_usbdev;
static DMA_HANDLE g_hdma;
static sem_t dma_wait;
static sem_t dma_wait = SEM_INITIALIZER(0);
#ifdef CONFIG_USBMSC_OPT
static struct lc823450_dma_llist g_dma_list[16];
@ -1453,7 +1453,6 @@ void arm_usbinitialize(void)
return;
}
nxsem_init(&dma_wait, 0, 0);
g_hdma = lc823450_dmachannel(DMA_CHANNEL_USBDEV);
lc823450_dmarequest(g_hdma, DMA_REQUEST_USBDEV);
@ -1722,7 +1721,6 @@ void usbdev_msc_read_enter()
privep->epcmd &= ~USB_EPCMD_EMPTY_EN;
epcmd_write(CONFIG_USBMSC_EPBULKIN, (privep->epcmd));
lc823450_dmareauest_dir(g_hdma, DMA_REQUEST_USBDEV, 1);
nxsem_init(&dma_wait, 0, 0);
}
/****************************************************************************
@ -1825,7 +1823,6 @@ void usbdev_msc_write_enter0(void)
privep->epcmd &= ~USB_EPCMD_READY_EN;
epcmd_write(CONFIG_USBMSC_EPBULKOUT, (privep->epcmd));
lc823450_dmareauest_dir(g_hdma, DMA_REQUEST_USBDEV, 0);
nxsem_init(&dma_wait, 0, 0);
}
/****************************************************************************

7
arch/arm/src/lpc17xx_40xx/lpc17_40_gpdma.c
View File

@ -84,7 +84,10 @@ struct lpc17_40_gpdma_s
/* The state of the LPC17 DMA block */
static struct lpc17_40_gpdma_s g_gpdma;
static struct lpc17_40_gpdma_s g_gpdma =
{
.lock = NXMUTEX_INITIALIZER,
};
/****************************************************************************
* Public Data
@ -291,8 +294,6 @@ void weak_function arm_dma_initialize(void)
/* Initialize the DMA state structure */
nxmutex_init(&g_gpdma.lock);
for (i = 0; i < LPC17_40_NDMACH; i++)
{
g_gpdma.dmach[i].chn = i; /* Channel number */

28
arch/arm/src/lpc17xx_40xx/lpc17_40_i2c.c
View File

@ -147,13 +147,25 @@ static int lpc17_40_i2c_reset(struct i2c_master_s * dev);
****************************************************************************/
#ifdef CONFIG_LPC17_40_I2C0
static struct lpc17_40_i2cdev_s g_i2c0dev;
static struct lpc17_40_i2cdev_s g_i2c0dev =
{
.lock = NXMUTEX_INITIALIZER,
.wait = SEM_INITIALIZER(0),
};
#endif
#ifdef CONFIG_LPC17_40_I2C1
static struct lpc17_40_i2cdev_s g_i2c1dev;
static struct lpc17_40_i2cdev_s g_i2c1dev =
{
.lock = NXMUTEX_INITIALIZER,
.wait = SEM_INITIALIZER(0),
};
#endif
#ifdef CONFIG_LPC17_40_I2C2
static struct lpc17_40_i2cdev_s g_i2c2dev;
static struct lpc17_40_i2cdev_s g_i2c2dev =
{
.lock = NXMUTEX_INITIALIZER,
.wait = SEM_INITIALIZER(0),
};
#endif
struct i2c_ops_s lpc17_40_i2c_ops =
@ -617,11 +629,6 @@ struct i2c_master_s *lpc17_40_i2cbus_initialize(int port)
putreg32(I2C_CONSET_I2EN, priv->base + LPC17_40_I2C_CONSET_OFFSET);
/* Initialize mutex & semaphores */
nxmutex_init(&priv->lock);
nxsem_init(&priv->wait, 0, 0);
/* Attach Interrupt Handler */
irq_attach(priv->irqid, lpc17_40_i2c_interrupt, priv);
@ -652,11 +659,6 @@ int lpc17_40_i2cbus_uninitialize(struct i2c_master_s * dev)
putreg32(I2C_CONCLRT_I2ENC, priv->base + LPC17_40_I2C_CONCLR_OFFSET);
/* Reset data structures */
nxmutex_destroy(&priv->lock);
nxsem_destroy(&priv->wait);
/* Cancel the watchdog timer */
wd_cancel(&priv->timeout);

5
arch/arm/src/lpc17xx_40xx/lpc17_40_sdcard.c
View File

@ -444,6 +444,7 @@ struct lpc17_40_dev_s g_scard_dev =
#endif
#endif
},
.waitsem = SEM_INITIALIZER(0),
};
/* Register logging support */
@ -2719,10 +2720,6 @@ struct sdio_dev_s *sdio_initialize(int slotno)
/* Initialize the SD card slot structure */
/* Initialize semaphores */
nxsem_init(&priv->waitsem, 0, 0);
#ifdef CONFIG_LPC17_40_SDCARD_DMA
/* Configure the SDCARD DMA request */

5
arch/arm/src/lpc17xx_40xx/lpc17_40_spi.c
View File

@ -142,6 +142,7 @@ static struct lpc17_40_spidev_s g_spidev =
{
&g_spiops
},
.lock = NXMUTEX_INITIALIZER,
};
/****************************************************************************
@ -563,10 +564,6 @@ struct spi_dev_s *lpc17_40_spibus_initialize(int port)
/* Select a default frequency of approx. 400KHz */
spi_setfrequency((struct spi_dev_s *)priv, 400000);
/* Initialize the SPI mutex that enforces mutually exclusive access */
nxmutex_init(&priv->lock);
return &priv->spidev;
}

7
arch/arm/src/lpc17xx_40xx/lpc17_40_ssp.c
View File

@ -184,6 +184,7 @@ static struct lpc17_40_sspdev_s g_ssp0dev =
#ifdef CONFIG_LPC17_40_SSP_INTERRUPTS
.sspirq = LPC17_40_IRQ_SSP0,
#endif
.lock = NXMUTEX_INITIALIZER,
};
#endif /* CONFIG_LPC17_40_SSP0 */
@ -219,6 +220,7 @@ static struct lpc17_40_sspdev_s g_ssp1dev =
#ifdef CONFIG_LPC17_40_SSP_INTERRUPTS
.sspirq = LPC17_40_IRQ_SSP1,
#endif
.lock = NXMUTEX_INITIALIZER,
};
#endif /* CONFIG_LPC17_40_SSP1 */
@ -254,6 +256,7 @@ static struct lpc17_40_sspdev_s g_ssp2dev =
#ifdef CONFIG_LPC17_40_SSP_INTERRUPTS
.sspirq = LPC17_40_IRQ_SSP2,
#endif
.lock = NXMUTEX_INITIALIZER,
};
#endif /* CONFIG_LPC17_40_SSP2 */
@ -993,10 +996,6 @@ struct spi_dev_s *lpc17_40_sspbus_initialize(int port)
ssp_setfrequency((struct spi_dev_s *)priv, 400000);
/* Initialize the SPI mutex that enforces mutually exclusive access */
nxmutex_init(&priv->lock);
/* Enable the SPI */
regval = ssp_getreg(priv, LPC17_40_SSP_CR1_OFFSET);

11
arch/arm/src/lpc17xx_40xx/lpc17_40_usbhost.c
View File

@ -411,7 +411,11 @@ static inline void lpc17_40_ep0init(struct lpc17_40_usbhost_s *priv);
* single global instance.
*/
static struct lpc17_40_usbhost_s g_usbhost;
static struct lpc17_40_usbhost_s g_usbhost =
{
.lock = NXMUTEX_INITIALIZER,
.pscsem = SEM_INITIALIZER(0),
};
/* This is the connection/enumeration interface */
@ -3736,11 +3740,6 @@ struct usbhost_connection_s *lpc17_40_usbhost_initialize(int controller)
usbhost_devaddr_initialize(&priv->rhport);
/* Initialize semaphores & mutex */
nxsem_init(&priv->pscsem, 0, 0);
nxmutex_init(&priv->lock);
#ifndef CONFIG_USBHOST_INT_DISABLE
priv->ininterval = MAX_PERINTERVAL;
priv->outinterval = MAX_PERINTERVAL;

28
arch/arm/src/lpc2378/lpc23xx_i2c.c
View File

@ -153,13 +153,25 @@ static int lpc2378_i2c_reset(struct i2c_master_s * dev);
****************************************************************************/
#ifdef CONFIG_LPC2378_I2C0
static struct lpc2378_i2cdev_s g_i2c0dev;
static struct lpc2378_i2cdev_s g_i2c0dev =
{
.lock = NXMUTEX_INITIALIZER,
.wait = SEM_INITIALIZER(0),
};
#endif
#ifdef CONFIG_LPC2378_I2C1
static struct lpc2378_i2cdev_s g_i2c1dev;
static struct lpc2378_i2cdev_s g_i2c1dev =
{
.lock = NXMUTEX_INITIALIZER,
.wait = SEM_INITIALIZER(0),
};
#endif
#ifdef CONFIG_LPC2378_I2C2
static struct lpc2378_i2cdev_s g_i2c2dev;
static struct lpc2378_i2cdev_s g_i2c2dev =
{
.lock = NXMUTEX_INITIALIZER,
.wait = SEM_INITIALIZER(0),
};
#endif
struct i2c_ops_s lpc2378_i2c_ops =
@ -580,11 +592,6 @@ struct i2c_master_s *lpc2378_i2cbus_initialize(int port)
putreg32(I2C_CONSET_I2EN, priv->base + I2C_CONSET_OFFSET);
/* Initialize mutex & semaphores */
nxmutex_init(&priv->lock);
nxsem_init(&priv->wait, 0, 0);
/* Attach Interrupt Handler */
irq_attach(priv->irqid, lpc2378_i2c_interrupt, priv);
@ -615,11 +622,6 @@ int lpc2378_i2cbus_uninitialize(struct i2c_master_s * dev)
putreg32(I2C_CONCLRT_I2ENC, priv->base + I2C_CONCLR_OFFSET);
/* Reset data structures */
nxmutex_destroy(&priv->lock);
nxsem_destroy(&priv->wait);
/* Cancel the watchdog timer */
wd_cancel(&priv->timeout);

5
arch/arm/src/lpc2378/lpc23xx_spi.c
View File

@ -161,6 +161,7 @@ static struct lpc23xx_spidev_s g_spidev =
{
&g_spiops
},
.lock = NXMUTEX_INITIALIZER,
};
/****************************************************************************
@ -588,10 +589,6 @@ struct spi_dev_s *lpc23_spibus_initialize(int port)
/* Select a default frequency of approx. 400KHz */
spi_setfrequency((struct spi_dev_s *)priv, 400000);
/* Initialize the SPI mutex that enforces mutually exclusive access */
nxmutex_init(&priv->lock);
return &priv->spidev;
}

16
arch/arm/src/lpc31xx/lpc31_ehci.c
View File

@ -565,7 +565,12 @@ static int lpc31_reset(void);
* global instance.
*/
static struct lpc31_ehci_s g_ehci;
static struct lpc31_ehci_s g_ehci =
{
.lock = NXMUTEX_INITIALIZER,
.pscsem = SEM_INITIALIZER(0),
.ep0.iocsem = SEM_INITIALIZER(1),
};
/* This is the connection/enumeration interface */
@ -5016,15 +5021,6 @@ struct usbhost_connection_s *lpc31_ehci_initialize(int controller)
usbhost_vtrace1(EHCI_VTRACE1_INITIALIZING, 0);
/* Initialize the EHCI state data structure */
nxmutex_init(&g_ehci.lock);
nxsem_init(&g_ehci.pscsem, 0, 0);
/* Initialize EP0 */
nxsem_init(&g_ehci.ep0.iocsem, 0, 1);
/* Initialize the root hub port structures */
for (i = 0; i < LPC31_EHCI_NRHPORT; i++)

17
arch/arm/src/lpc31xx/lpc31_i2c.c
View File

@ -90,7 +90,17 @@ struct lpc31_i2cdev_s
#define I2C_STATE_HEADER 2
#define I2C_STATE_TRANSFER 3
static struct lpc31_i2cdev_s i2cdevices[2];
static struct lpc31_i2cdev_s i2cdevices[2] =
{
{
.lock = NXMUTEX_INITIALIZER,
.wait = SEM_INITIALIZER(0),
},
{
.lock = NXMUTEX_INITIALIZER,
.wait = SEM_INITIALIZER(0),
},
};
/****************************************************************************
* Private Function Prototypes
@ -556,11 +566,6 @@ struct i2c_master_s *lpc31_i2cbus_initialize(int port)
priv->rstid = (port == 0) ? RESETID_I2C0RST : RESETID_I2C1RST;
priv->irqid = (port == 0) ? LPC31_IRQ_I2C0 : LPC31_IRQ_I2C1;
/* Initialize mutex & semaphores */
nxmutex_init(&priv->lock);
nxsem_init(&priv->wait, 0, 0);
/* Enable I2C system clocks */
lpc31_enableclock(priv->clkid);

5
arch/arm/src/lpc31xx/lpc31_spi.c
View File

@ -157,6 +157,7 @@ static struct lpc31_spidev_s g_spidev =
{
&g_spiops
},
.lock = NXMUTEX_INITIALIZER,
};
#ifdef CONFIG_LPC31_SPI_REGDEBUG
@ -964,10 +965,6 @@ struct spi_dev_s *lpc31_spibus_initialize(int port)
lpc31_softreset(RESETID_SPIRSTAPB);
lpc31_softreset(RESETID_SPIRSTIP);
/* Initialize the SPI mutex that enforces mutually exclusive access */
nxmutex_init(&priv->lock);
/* Reset the SPI block */
spi_putreg(SPI_CONFIG_SOFTRST, LPC31_SPI_CONFIG);

16
arch/arm/src/lpc43xx/lpc43_ehci.c
View File

@ -555,7 +555,12 @@ static int lpc43_reset(void);
* global instance.
*/
static struct lpc43_ehci_s g_ehci;
static struct lpc43_ehci_s g_ehci =
{
.lock = NXMUTEX_INITIALIZER,
.pscsem = SEM_INITIALIZER(0),
.ep0.iocsem = SEM_INITIALIZER(1),
};
/* This is the connection/enumeration interface */
@ -4840,15 +4845,6 @@ struct usbhost_connection_s *lpc43_ehci_initialize(int controller)
usbhost_vtrace1(EHCI_VTRACE1_INITIALIZING, 0);
/* Initialize the EHCI state data structure */
nxmutex_init(&g_ehci.lock);
nxsem_init(&g_ehci.pscsem, 0, 0);
/* Initialize EP0 */
nxsem_init(&g_ehci.ep0.iocsem, 0, 1);
/* Initialize the root hub port structures */
for (i = 0; i < LPC43_EHCI_NRHPORT; i++)

7
arch/arm/src/lpc43xx/lpc43_gpdma.c
View File

@ -84,7 +84,10 @@ struct lpc43_gpdma_s
/* The state of the LPC43 DMA block */
static struct lpc43_gpdma_s g_gpdma;
static struct lpc43_gpdma_s g_gpdma =
{
.lock = NXMUTEX_INITIALIZER,
};
/****************************************************************************
* Public Data
@ -291,8 +294,6 @@ void weak_function arm_dma_initialize(void)
/* Initialize the DMA state structure */
nxmutex_init(&g_gpdma.lock);
for (i = 0; i < LPC43_NDMACH; i++)
{
g_gpdma.dmach[i].chn = i; /* Channel number */

17
arch/arm/src/lpc43xx/lpc43_i2c.c
View File

@ -118,10 +118,18 @@ struct lpc43_i2cdev_s
};
#ifdef CONFIG_LPC43_I2C0
static struct lpc43_i2cdev_s g_i2c0dev;
static struct lpc43_i2cdev_s g_i2c0dev =
{
.lock = NXMUTEX_INITIALIZER,
.wait = SEM_INITIALIZER(0),
};
#endif
#ifdef CONFIG_LPC43_I2C1
static struct lpc43_i2cdev_s g_i2c1dev;
static struct lpc43_i2cdev_s g_i2c1dev =
{
.lock = NXMUTEX_INITIALIZER,
.wait = SEM_INITIALIZER(0),
};
#endif
/****************************************************************************
@ -528,11 +536,6 @@ struct i2c_master_s *lpc43_i2cbus_initialize(int port)
putreg32(I2C_CONSET_I2EN, priv->base + LPC43_I2C_CONSET_OFFSET);
/* Initialize mutex & semaphores */
nxmutex_init(&priv->lock);
nxsem_init(&priv->wait, 0, 0);
/* Attach Interrupt Handler */
irq_attach(priv->irqid, lpc43_i2c_interrupt, priv);

5
arch/arm/src/lpc43xx/lpc43_sdmmc.c
View File

@ -380,6 +380,7 @@ struct lpc43_dev_s g_scard_dev =
.dmasendsetup = lpc43_dmasendsetup,
#endif
},
.waitsem = SEM_INITIALIZER(0),
};
#ifdef CONFIG_LPC43_SDMMC_DMA
@ -2824,10 +2825,6 @@ struct sdio_dev_s *lpc43_sdmmc_initialize(int slotno)
lpc43_putreg(LPC43_SDMMC_DELAY_DEFAULT, LPC43_SDMMC_DELAY);
/* Initialize semaphores */
nxsem_init(&priv->waitsem, 0, 0);
/* Configure GPIOs for 4-bit, wide-bus operation */
lpc43_pin_config(GPIO_SD_D0);

5
arch/arm/src/lpc43xx/lpc43_spi.c
View File

@ -133,6 +133,7 @@ static struct lpc43_spidev_s g_spidev =
{
&g_spiops
},
.lock = NXMUTEX_INITIALIZER,
};
/****************************************************************************
@ -532,10 +533,6 @@ static struct spi_dev_s *lpc43_spiport_initialize(int port)
/* Select a default frequency of approx. 400KHz */
spi_setfrequency((struct spi_dev_s *)priv, 400000);
/* Initialize the SPI mutex that enforces mutually exclusive access */
nxmutex_init(&priv->lock);
return &priv->spidev;
}
#endif /* CONFIG_LPC43_SPI */

10
arch/arm/src/lpc43xx/lpc43_ssp.c
View File

@ -148,10 +148,11 @@ static struct lpc43_sspdev_s g_ssp0dev =
&g_spi0ops
},
.sspbase = LPC43_SSP0_BASE,
.sspbasefreq = BOARD_SSP0_BASEFREQ
.sspbasefreq = BOARD_SSP0_BASEFREQ,
#ifdef CONFIG_LPC43_SSP_INTERRUPTS
.sspirq = LPC43_IRQ_SSP0,
#endif
.lock = NXMUTEX_INITIALIZER,
};
#endif /* CONFIG_LPC43_SSP0 */
@ -188,10 +189,11 @@ static struct lpc43_sspdev_s g_ssp1dev =
&g_spi1ops
},
.sspbase = LPC43_SSP1_BASE,
.sspbasefreq = BOARD_SSP1_BASEFREQ
.sspbasefreq = BOARD_SSP1_BASEFREQ,
#ifdef CONFIG_LPC43_SSP_INTERRUPTS
.sspirq = LPC43_IRQ_SSP1,
#endif
.lock = NXMUTEX_INITIALIZER,
};
#endif /* CONFIG_LPC43_SSP1 */
@ -827,10 +829,6 @@ struct spi_dev_s *lpc43_sspbus_initialize(int port)
ssp_setfrequency((struct spi_dev_s *)priv, 400000);
/* Initialize the SPI mutex that enforces mutually exclusive access */
nxmutex_init(&priv->lock);
/* Enable the SPI */
regval = ssp_getreg(priv, LPC43_SSP_CR1_OFFSET);

9
arch/arm/src/lpc54xx/lpc54_dma.c
View File

@ -73,7 +73,10 @@ struct lpc54_dma_s
/* The state of the LPC54 DMA block */
static struct lpc54_dma_s g_dma;
static struct lpc54_dma_s g_dma =
{
.lock = NXMUTEX_INITIALIZER,
};
/* The SRAMBASE register must be configured with an address (preferably in
* on-chip SRAM) where DMA descriptors will be stored. Each DMA channel has
@ -232,10 +235,6 @@ void weak_function arm_dma_initialize(void)
putreg32(DMA_ALL_CHANNELS, LPC54_DMA_INTA0);
putreg32(DMA_ALL_CHANNELS, LPC54_DMA_INTB0);
/* Initialize the DMA state structure */
nxmutex_init(&g_dma.lock);
/* Set the SRAMBASE to the beginning a array of DMA descriptors, one for
* each DMA channel.
*/

96
arch/arm/src/lpc54xx/lpc54_i2c_master.c
View File

@ -185,34 +185,103 @@ struct i2c_ops_s lpc54_i2c_ops =
};
#ifdef CONFIG_LPC54_I2C0_MASTER
static struct lpc54_i2cdev_s g_i2c0_dev;
static struct lpc54_i2cdev_s g_i2c0_dev =
{
.lock = NXMUTEX_INITIALIZER,
# ifndef CONFIG_I2C_POLLED
.waitsem = SEM_INITIALIZER(0),
# endif
};
#endif
#ifdef CONFIG_LPC54_I2C1_MASTER
static struct lpc54_i2cdev_s g_i2c1_dev;
static struct lpc54_i2cdev_s g_i2c1_dev =
{
.lock = NXMUTEX_INITIALIZER,
# ifndef CONFIG_I2C_POLLED
.waitsem = SEM_INITIALIZER(0),
# endif
};
#endif
#ifdef CONFIG_LPC54_I2C2_MASTER
static struct lpc54_i2cdev_s g_i2c2_dev;
static struct lpc54_i2cdev_s g_i2c2_dev =
{
.lock = NXMUTEX_INITIALIZER,
# ifndef CONFIG_I2C_POLLED
.waitsem = SEM_INITIALIZER(0),
# endif
};
#endif
#ifdef CONFIG_LPC54_I2C3_MASTER
static struct lpc54_i2cdev_s g_i2c3_dev;
static struct lpc54_i2cdev_s g_i2c3_dev =
{
.lock = NXMUTEX_INITIALIZER,
# ifndef CONFIG_I2C_POLLED
.waitsem = SEM_INITIALIZER(0),
# endif
};
#endif
#ifdef CONFIG_LPC54_I2C4_MASTER
static struct lpc54_i2cdev_s g_i2c4_dev;
static struct lpc54_i2cdev_s g_i2c4_dev =
{
.lock = NXMUTEX_INITIALIZER,
# ifndef CONFIG_I2C_POLLED
.waitsem = SEM_INITIALIZER(0),
# endif
};
#endif
#ifdef CONFIG_LPC54_I2C5_MASTER
static struct lpc54_i2cdev_s g_i2c5_dev;
static struct lpc54_i2cdev_s g_i2c5_dev =
{
.lock = NXMUTEX_INITIALIZER,
# ifndef CONFIG_I2C_POLLED
.waitsem = SEM_INITIALIZER(0),
# endif
};
#endif
#ifdef CONFIG_LPC54_I2C6_MASTER
static struct lpc54_i2cdev_s g_i2c6_dev;
static struct lpc54_i2cdev_s g_i2c6_dev =
{
.lock = NXMUTEX_INITIALIZER,
# ifndef CONFIG_I2C_POLLED
.waitsem = SEM_INITIALIZER(0),
# endif
};
#endif
#ifdef CONFIG_LPC54_I2C7_MASTER
static struct lpc54_i2cdev_s g_i2c7_dev;
static struct lpc54_i2cdev_s g_i2c7_dev =
{
.lock = NXMUTEX_INITIALIZER,
# ifndef CONFIG_I2C_POLLED
.waitsem = SEM_INITIALIZER(0),
# endif
};
#endif
#ifdef CONFIG_LPC54_I2C8_MASTER
static struct lpc54_i2cdev_s g_i2c8_dev;
static struct lpc54_i2cdev_s g_i2c8_dev =
{
.lock = NXMUTEX_INITIALIZER,
# ifndef CONFIG_I2C_POLLED
.waitsem = SEM_INITIALIZER(0),
# endif
};
#endif
#ifdef CONFIG_LPC54_I2C9_MASTER
static struct lpc54_i2cdev_s g_i2c9_dev;
static struct lpc54_i2cdev_s g_i2c9_dev =
{
.lock = NXMUTEX_INITIALIZER,
# ifndef CONFIG_I2C_POLLED
.waitsem = SEM_INITIALIZER(0),
# endif
};
#endif
/****************************************************************************
@ -1207,13 +1276,6 @@ struct i2c_master_s *lpc54_i2cbus_initialize(int port)
lpc54_i2c_setfrequency(priv, I2C_DEFAULT_FREQUENCY);
/* Initialize mutex & semaphores */
nxmutex_init(&priv->lock);
#ifndef CONFIG_I2C_POLLED
nxsem_init(&priv->waitsem, 0, 0);
#endif
#ifndef CONFIG_I2C_POLLED
/* Attach Interrupt Handler */

9
arch/arm/src/lpc54xx/lpc54_rng.c
View File

@ -55,7 +55,10 @@ struct rng_dev_s
* Private Data
****************************************************************************/
static struct rng_dev_s g_rngdev;
static struct rng_dev_s g_rngdev =
{
.rd_devlock = NXMUTEX_INITIALIZER,
};
static const struct file_operations g_rngops =
{
@ -145,7 +148,6 @@ static ssize_t lpc54_read(struct file *filep, char *buffer, size_t buflen)
#ifdef CONFIG_DEV_RANDOM
void devrandom_register(void)
{
nxmutex_init(&g_rngdev.rd_devlock);
register_driver("/dev/random", &g_rngops, 0444, NULL);
}
#endif
@ -167,9 +169,6 @@ void devrandom_register(void)
#ifdef CONFIG_DEV_URANDOM_ARCH
void devurandom_register(void)
{
#ifndef CONFIG_DEV_RANDOM
nxmutex_init(&g_rngdev.rd_devlock);
#endif
register_driver("/dev/urandom", &g_rngops, 0444, NULL);
}
#endif

2
arch/arm/src/lpc54xx/lpc54_rtc_lowerhalf.c
View File

@ -146,6 +146,7 @@ static const struct rtc_ops_s g_rtc_ops =
static struct lpc54_lowerhalf_s g_rtc_lowerhalf =
{
.ops = &g_rtc_ops,
.devlock = NXMUTEX_INITIALIZER,
};
/****************************************************************************
@ -639,7 +640,6 @@ static int lpc54_cancelperiodic(struct rtc_lowerhalf_s *lower, int id)
struct rtc_lowerhalf_s *lpc54_rtc_lowerhalf(void)
{
nxmutex_init(&g_rtc_lowerhalf.devlock);
return (struct rtc_lowerhalf_s *)&g_rtc_lowerhalf;
}

5
arch/arm/src/lpc54xx/lpc54_sdmmc.c
View File

@ -380,6 +380,7 @@ struct lpc54_dev_s g_scard_dev =
.dmasendsetup = lpc54_dmasendsetup,
#endif
},
.waitsem = SEM_INITIALIZER(0),
};
#ifdef CONFIG_LPC54_SDMMC_DMA
@ -2827,10 +2828,6 @@ struct sdio_dev_s *lpc54_sdmmc_initialize(int slotno)
lpc54_sdmmc_enableclk();
/* Initialize semaphores */
nxsem_init(&priv->waitsem, 0, 0);
/* Configure GPIOs for 4-bit, wide-bus operation */
lpc54_gpio_config(GPIO_SD_D0);

54
arch/arm/src/lpc54xx/lpc54_spi_master.c
View File

@ -237,7 +237,10 @@ static const struct spi_ops_s g_spi0_ops =
#endif
};
static struct lpc54_spidev_s g_spi0_dev;
static struct lpc54_spidev_s g_spi0_dev =
{
.lock = NXMUTEX_INITIALIZER,
};
#endif
#ifdef CONFIG_LPC54_SPI1_MASTER
@ -269,7 +272,10 @@ static const struct spi_ops_s g_spi1_ops =
#endif
};
static struct lpc54_spidev_s g_spi1_dev;
static struct lpc54_spidev_s g_spi1_dev =
{
.lock = NXMUTEX_INITIALIZER,
};
#endif
#ifdef CONFIG_LPC54_SPI2_MASTER
@ -301,7 +307,10 @@ static const struct spi_ops_s g_spi2_ops =
#endif
};
static struct lpc54_spidev_s g_spi2_dev;
static struct lpc54_spidev_s g_spi2_dev =
{
.lock = NXMUTEX_INITIALIZER,
};
#endif
#ifdef CONFIG_LPC54_SPI3_MASTER
@ -333,7 +342,10 @@ static const struct spi_ops_s g_spi3_ops =
#endif
};
static struct lpc54_spidev_s g_spi3_dev;
static struct lpc54_spidev_s g_spi3_dev =
{
.lock = NXMUTEX_INITIALIZER,
};
#endif
#ifdef CONFIG_LPC54_SPI4_MASTER
@ -365,7 +377,10 @@ static const struct spi_ops_s g_spi4_ops =
#endif
};
static struct lpc54_spidev_s g_spi4_dev;
static struct lpc54_spidev_s g_spi4_dev =
{
.lock = NXMUTEX_INITIALIZER,
};
#endif
#ifdef CONFIG_LPC54_SPI5_MASTER
@ -397,7 +412,10 @@ static const struct spi_ops_s g_spi5_ops =
#endif
};
static struct lpc54_spidev_s g_spi5_dev;
static struct lpc54_spidev_s g_spi5_dev =
{
.lock = NXMUTEX_INITIALIZER,
};
#endif
#ifdef CONFIG_LPC54_SPI6_MASTER
@ -429,7 +447,10 @@ static const struct spi_ops_s g_spi6_ops =
#endif
};
static struct lpc54_spidev_s g_spi6_dev;
static struct lpc54_spidev_s g_spi6_dev =
{
.lock = NXMUTEX_INITIALIZER,
};
#endif
#ifdef CONFIG_LPC54_SPI7_MASTER
@ -461,7 +482,10 @@ static const struct spi_ops_s g_spi7_ops =
#endif
};
static struct lpc54_spidev_s g_spi7_dev;
static struct lpc54_spidev_s g_spi7_dev =
{
.lock = NXMUTEX_INITIALIZER,
};
#endif
#ifdef CONFIG_LPC54_SPI8_MASTER
@ -493,7 +517,10 @@ static const struct spi_ops_s g_spi8_ops =
#endif
};
static struct lpc54_spidev_s g_spi8_dev;
static struct lpc54_spidev_s g_spi8_dev =
{
.lock = NXMUTEX_INITIALIZER,
};
#endif
#ifdef CONFIG_LPC54_SPI9_MASTER
@ -525,7 +552,10 @@ static const struct spi_ops_s g_spi9_ops =
#endif
};
static struct lpc54_spidev_s g_spi9_dev;
static struct lpc54_spidev_s g_spi9_dev =
{
.lock = NXMUTEX_INITIALIZER,
};
#endif
/****************************************************************************
@ -2016,10 +2046,6 @@ struct spi_dev_s *lpc54_spibus_initialize(int port)
priv->nbits = 8;
priv->mode = SPIDEV_MODE0;
/* Initialize the SPI mutex that enforces mutually exclusive access */
nxmutex_init(&priv->lock);
/* Configure master mode in mode 0:
*
* ENABLE - Disabled for now (0)

11
arch/arm/src/lpc54xx/lpc54_usb0_ohci.c
View File

@ -500,7 +500,11 @@ static inline void lpc54_ep0init(struct lpc54_usbhost_s *priv);
* single global instance.
*/
static struct lpc54_usbhost_s g_usbhost;
static struct lpc54_usbhost_s g_usbhost =
{
.lock = NXMUTEX_INITIALIZER,
.pscsem = SEM_INITIALIZER(0),
};
/* This is the connection/enumeration interface */
@ -3822,11 +3826,6 @@ struct usbhost_connection_s *lpc54_usbhost_initialize(int controller)
usbhost_devaddr_initialize(&priv->rhport);
/* Initialize semaphores & mutex */
nxsem_init(&priv->pscsem, 0, 0);
nxmutex_init(&priv->lock);
#ifndef CONFIG_OHCI_INT_DISABLE
priv->ininterval = MAX_PERINTERVAL;
priv->outinterval = MAX_PERINTERVAL;

2
arch/arm/src/max326xx/common/max326_rtc_lowerhalf.c
View File

@ -152,6 +152,7 @@ static const struct rtc_ops_s g_rtc_ops =
static struct max326_lowerhalf_s g_rtc_lowerhalf =
{
.ops = &g_rtc_ops,
.devlock = NXMUTEX_INITIALIZER,
};
/****************************************************************************
@ -747,7 +748,6 @@ static int max326_cancelperiodic(struct rtc_lowerhalf_s *lower, int id)
struct rtc_lowerhalf_s *max326_rtc_lowerhalf(void)
{
nxmutex_init(&g_rtc_lowerhalf.devlock);
return (struct rtc_lowerhalf_s *)&g_rtc_lowerhalf;
}

5
arch/arm/src/max326xx/max32660/max32660_spim.c
View File

@ -236,6 +236,7 @@ static struct max326_spidev_s g_spi0dev =
&g_sp0iops
},
.base = MAX326_SPI0_BASE,
.lock = NXMUTEX_INITIALIZER,
#ifdef CONFIG_MAX326_SPI_INTERRUPTS
.irq = MAX326_IRQ_SPI,
#endif
@ -1433,10 +1434,6 @@ static void spi_bus_initialize(struct max326_spidev_s *priv)
regval = priv->wire3 ? SPI_CTRL2_DATWIDTH_SINGLE : SPI_CTRL2_DATWIDTH_DUAL;
spi_modify_ctrl2(priv, regval, SPI_CTRL2_DATWIDTH_MASK);
/* Initialize the SPI mutex that enforces mutually exclusive access */
nxmutex_init(&priv->lock);
/* Disable all interrupts at the peripheral */
spi_putreg(priv, MAX326_SPI_INTEN_OFFSET, 0);

7
arch/arm/src/nrf52/nrf52_radio.c
View File

@ -143,6 +143,8 @@ struct nrf52_radio_dev_s g_nrf52_radio_dev_1 =
.txbuf_len = NRF52_RADIO_TXBUFFER,
.rxbuf = g_nrf52_radio_dev_rx1,
.txbuf = g_nrf52_radio_dev_tx1,
.lock = NXMUTEX_INITIALIZER,
.sem_isr = SEM_INITIALIZER(0),
};
/****************************************************************************
@ -1160,11 +1162,6 @@ nrf52_radio_initialize(int intf, struct nrf52_radio_board_s *board)
irq_attach(dev->irq, nrf52_radio_isr, dev);
up_enable_irq(dev->irq);
/* Initialize mutex */
nxmutex_init(&dev->lock);
nxsem_init(&dev->sem_isr, 0, 0);
/* Connect board-specific data */
dev->board = board;

13
arch/arm/src/nrf52/nrf52_rng.c
View File

@ -72,7 +72,11 @@ struct rng_dev_s
* Private Data
****************************************************************************/
static struct rng_dev_s g_rngdev;
static struct rng_dev_s g_rngdev =
{
.rd_sem = SEM_INITIALIZER(0),
.lock = NXMUTEX_INITIALIZER,
};
static const struct file_operations g_rngops =
{
@ -124,13 +128,6 @@ static int nrf52_rng_initialize(void)
first_flag = false;
_info("Initializing RNG\n");
memset(&g_rngdev, 0, sizeof(struct rng_dev_s));
nxsem_init(&g_rngdev.rd_sem, 0, 0);
nxmutex_init(&g_rngdev.lock);
_info("Ready to stop\n");
nrf52_rng_stop();

10
arch/arm/src/nrf52/nrf52_sdc.c
View File

@ -171,7 +171,10 @@ static const mpsl_clock_lfclk_cfg_t g_clock_config =
.skip_wait_lfclk_started = false
};
static struct nrf52_sdc_dev_s g_sdc_dev;
static struct nrf52_sdc_dev_s g_sdc_dev =
{
.lock = NXMUTEX_INITIALIZER,
};
/****************************************************************************
* Private Functions
@ -499,11 +502,6 @@ int nrf52_sdc_initialize(void)
int32_t required_memory;
sdc_cfg_t cfg;
/* Initialize device data */
memset(&g_sdc_dev, 0, sizeof(g_sdc_dev));
nxmutex_init(&g_sdc_dev.lock);
/* Register interrupt handler for normal-priority events. SWI5 will be
* used by MPSL to delegate low-priority work
*/

14
arch/arm/src/nrf52/nrf52_spi.c
View File

@ -202,7 +202,9 @@ static struct nrf52_spidev_s g_spi0dev =
},
.base = NRF52_SPIM0_BASE,
.lock = NXMUTEX_INITIALIZER,
#ifdef CONFIG_NRF52_SPI_MASTER_INTERRUPTS
.sem_isr = SEM_INITIALIZER(0),
.irq = NRF52_IRQ_SPI_TWI_0,
#endif
.sck_pin = BOARD_SPI0_SCK_PIN,
@ -253,7 +255,9 @@ static struct nrf52_spidev_s g_spi1dev =
},
.base = NRF52_SPIM1_BASE,
.lock = NXMUTEX_INITIALIZER,
#ifdef CONFIG_NRF52_SPI_MASTER_INTERRUPTS
.sem_isr = SEM_INITIALIZER(0),
.irq = NRF52_IRQ_SPI_TWI_1,
#endif
.sck_pin = BOARD_SPI1_SCK_PIN,
@ -304,7 +308,9 @@ static struct nrf52_spidev_s g_spi2dev =
},
.base = NRF52_SPIM2_BASE,
.lock = NXMUTEX_INITIALIZER,
#ifdef CONFIG_NRF52_SPI_MASTER_INTERRUPTS
.sem_isr = SEM_INITIALIZER(0),
.irq = NRF52_IRQ_SPI2,
#endif
.sck_pin = BOARD_SPI2_SCK_PIN,
@ -355,7 +361,9 @@ static struct nrf52_spidev_s g_spi3dev =
},
.base = NRF52_SPIM3_BASE,
.lock = NXMUTEX_INITIALIZER,
#ifdef CONFIG_NRF52_SPI_MASTER_INTERRUPTS
.sem_isr = SEM_INITIALIZER(0),
.irq = NRF52_IRQ_SPI3,
#endif
.sck_pin = BOARD_SPI3_SCK_PIN,
@ -1470,13 +1478,7 @@ struct spi_dev_s *nrf52_spibus_initialize(int port)
priv->initialized = true;
/* Initialize the SPI mutex */
nxmutex_init(&priv->lock);
#ifdef CONFIG_NRF52_SPI_MASTER_INTERRUPTS
nxsem_init(&priv->sem_isr, 0, 0);
/* Attach SPI interrupt */
irq_attach(priv->irq, nrf52_spi_isr, priv);

9
arch/arm/src/rp2040/rp2040_dmac.c
View File

@ -72,7 +72,11 @@ struct dma_controller_s
/* This is the overall state of the DMA controller */
static struct dma_controller_s g_dmac;
static struct dma_controller_s g_dmac =
{
.lock = NXMUTEX_INITIALIZER,
.chansem = SEM_INITIALIZER(RP2040_DMA_NCHANNELS),
};
/* This is the array of all DMA channels */
@ -161,9 +165,6 @@ void weak_function arm_dma_initialize(void)
/* Initialize the channel list */
nxmutex_init(&g_dmac.lock);
nxsem_init(&g_dmac.chansem, 0, RP2040_DMA_NCHANNELS);
for (i = 0; i < RP2040_DMA_NCHANNELS; i++)
{
g_dmach[i].chan = i;

5
arch/arm/src/rp2040/rp2040_flash_mtd.c
View File

@ -165,7 +165,8 @@ static struct rp2040_flash_dev_s my_dev =
#endif
rp2040_flash_ioctl,
"rp_flash"
}
},
.lock = NXMUTEX_INITIALIZER,
};
static bool initialized = false;
@ -503,8 +504,6 @@ struct mtd_dev_s *rp2040_flash_mtd_initialize(void)
initialized = true;
nxmutex_init(&my_dev.lock);
if (FLASH_BLOCK_COUNT < 4)
{
errno = ENOMEM;

14
arch/arm/src/rp2040/rp2040_spi.c
View File

@ -186,6 +186,10 @@ static struct rp2040_spidev_s g_spi0dev =
.initialized = 0,
#ifdef CONFIG_RP2040_SPI_INTERRUPTS
.spiirq = RP2040_SPI0_IRQ,
#endif
.lock = NXMUTEX_INITIALIZER,
#ifdef CONFIG_RP2040_SPI_DMA
.dmasem = SEM_INITIALIZER(0),
#endif
};
#endif
@ -231,6 +235,10 @@ static struct rp2040_spidev_s g_spi1dev =
.initialized = 0,
#ifdef CONFIG_RP2040_SPI_INTERRUPTS
.spiirq = RP2040_SPI1_IRQ,
#endif
.lock = NXMUTEX_INITIALIZER,
#ifdef CONFIG_RP2040_SPI_DMA
.dmasem = SEM_INITIALIZER(0),
#endif
};
#endif
@ -817,8 +825,6 @@ struct spi_dev_s *rp2040_spibus_initialize(int port)
/* DMA settings */
#ifdef CONFIG_RP2040_SPI_DMA
nxsem_init(&priv->dmasem, 0, 0);
priv->txdmach = rp2040_dmachannel();
txconf.size = RP2040_DMA_SIZE_BYTE;
txconf.noincr = false;
@ -857,10 +863,6 @@ struct spi_dev_s *rp2040_spibus_initialize(int port)
spi_setfrequency((struct spi_dev_s *)priv, 400000);
/* Initialize the SPI mutex that enforces mutually exclusive access */
nxmutex_init(&priv->lock);
regval = spi_getreg(priv, RP2040_SPI_SSPCR1_OFFSET);
spi_putreg(priv, RP2040_SPI_SSPCR1_OFFSET, regval | RP2040_SPI_SSPCR1_SSE);

14
arch/arm/src/s32k1xx/s32k1xx_edma.c
View File

@ -155,7 +155,13 @@ struct s32k1xx_edma_s
/* The state of the eDMA */
static struct s32k1xx_edma_s g_edma;
static struct s32k1xx_edma_s g_edma =
{
.chlock = NXMUTEX_INITIALIZER,
#if CONFIG_S32K1XX_EDMA_NTCD > 0
.dsem = SEM_INITIALIZER(CONFIG_S32K1XX_EDMA_NTCD),
#endif
};
#if CONFIG_S32K1XX_EDMA_NTCD > 0
/* This is a singly-linked list of free TCDs */
@ -706,18 +712,12 @@ void weak_function arm_dma_initialize(void)
/* Initialize data structures */
memset(&g_edma, 0, sizeof(struct s32k1xx_edma_s));
for (i = 0; i < S32K1XX_EDMA_NCHANNELS; i++)
{
g_edma.dmach[i].chan = i;
}
/* Initialize mutex & semaphores */
nxmutex_init(&g_edma.chlock);
#if CONFIG_S32K1XX_EDMA_NTCD > 0
nxsem_init(&g_edma.dsem, 0, CONFIG_S32K1XX_EDMA_NTCD);
/* Initialize the list of free TCDs from the pool of pre-allocated TCDs. */
s32k1xx_tcd_initialize();

7
arch/arm/src/s32k1xx/s32k1xx_lpspi.c
View File

@ -261,6 +261,7 @@ static struct s32k1xx_lpspidev_s g_lpspi0dev =
#ifdef CONFIG_S32K1XX_LPSPI_INTERRUPTS
.spiirq = S32K1XX_IRQ_LPSPI0,
#endif
.lock = NXMUTEX_INITIALIZER,
#ifdef CONFIG_S32K1XX_LPSPI_DMA
.rxch = DMAMAP_LPSPI0_RX,
.txch = DMAMAP_LPSPI0_TX,
@ -311,6 +312,7 @@ static struct s32k1xx_lpspidev_s g_lpspi1dev =
#ifdef CONFIG_S32K1XX_LPSPI_INTERRUPTS
.spiirq = S32K1XX_IRQ_LPSPI1,
#endif
.lock = NXMUTEX_INITIALIZER,
#ifdef CONFIG_S32K1XX_LPSPI_DMA
.rxch = DMAMAP_LPSPI1_RX,
.txch = DMAMAP_LPSPI1_TX,
@ -361,6 +363,7 @@ static struct s32k1xx_lpspidev_s g_lpspi2dev =
#ifdef CONFIG_S32K1XX_LPSPI_INTERRUPTS
.spiirq = S32K1XX_IRQ_LPSPI2,
#endif
.lock = NXMUTEX_INITIALIZER,
#ifdef CONFIG_S32K1XX_LPSPI_DMA
.rxch = DMAMAP_LPSPI2_RX,
.txch = DMAMAP_LPSPI2_TX,
@ -1714,10 +1717,6 @@ static void s32k1xx_lpspi_bus_initialize(struct s32k1xx_lpspidev_s *priv)
s32k1xx_lpspi_setmode((struct spi_dev_s *)priv, SPIDEV_MODE0);
/* Initialize the SPI mutex that enforces mutually exclusive access */
nxmutex_init(&priv->lock);
/* Enable LPSPI */
s32k1xx_lpspi_modifyreg32(priv, S32K1XX_LPSPI_CR_OFFSET, 0, LPSPI_CR_MEN);

14
arch/arm/src/s32k3xx/s32k3xx_edma.c
View File

@ -203,7 +203,13 @@ uintptr_t const S32K3XX_EDMA_TCD[S32K3XX_EDMA_NCHANNELS] =
/* The state of the eDMA */
static struct s32k3xx_edma_s g_edma;
static struct s32k3xx_edma_s g_edma =
{
.chlock = NXMUTEX_INITIALIZER,
#if CONFIG_S32K3XX_EDMA_NTCD > 0
.dsem = SEM_INITIALIZER(CONFIG_S32K3XX_EDMA_NTCD),
#endif
};
#if CONFIG_S32K3XX_EDMA_NTCD > 0
/* This is a singly-linked list of free TCDs */
@ -916,18 +922,12 @@ void weak_function arm_dma_initialize(void)
/* Initialize data structures */
memset(&g_edma, 0, sizeof(struct s32k3xx_edma_s));
for (i = 0; i < S32K3XX_EDMA_NCHANNELS; i++)
{
g_edma.dmach[i].chan = i;
}
/* Initialize mutex & semaphore */
nxmutex_init(&g_edma.chlock);
#if CONFIG_S32K3XX_EDMA_NTCD > 0
nxsem_init(&g_edma.dsem, 0, CONFIG_S32K3XX_EDMA_NTCD);
/* Initialize the list of free TCDs from the pool of pre-allocated TCDs. */
s32k3xx_tcd_initialize();

29
arch/arm/src/s32k3xx/s32k3xx_lpspi.c
View File

@ -252,9 +252,12 @@ static struct s32k3xx_lpspidev_s g_lpspi0dev =
#ifdef CONFIG_S32K3XX_LPSPI_INTERRUPTS
.spiirq = S32K3XX_IRQ_LPSPI0,
#endif
.lock = NXMUTEX_INITIALIZER,
#ifdef CONFIG_S32K3XX_LPSPI0_DMA
.rxch = DMA_REQ_LPSPI0_RX,
.txch = DMA_REQ_LPSPI0_TX,
.rxsem = SEM_INITIALIZER(0),
.txsem = SEM_INITIALIZER(0),
#endif
.pincfg = CONFIG_S32K3XX_LPSPI0_PINCFG,
};
@ -299,9 +302,12 @@ static struct s32k3xx_lpspidev_s g_lpspi1dev =
#ifdef CONFIG_S32K3XX_LPSPI_INTERRUPTS
.spiirq = S32K3XX_IRQ_LPSPI1,
#endif
.lock = NXMUTEX_INITIALIZER,
#ifdef CONFIG_S32K3XX_LPSPI1_DMA
.rxch = DMA_REQ_LPSPI1_RX,
.txch = DMA_REQ_LPSPI1_TX,
.rxsem = SEM_INITIALIZER(0),
.txsem = SEM_INITIALIZER(0),
#endif
.pincfg = CONFIG_S32K3XX_LPSPI1_PINCFG,
};
@ -346,9 +352,12 @@ static struct s32k3xx_lpspidev_s g_lpspi2dev =
#ifdef CONFIG_S32K3XX_LPSPI_INTERRUPTS
.spiirq = S32K3XX_IRQ_LPSPI2,
#endif
.lock = NXMUTEX_INITIALIZER,
#ifdef CONFIG_S32K3XX_LPSPI2_DMA
.rxch = DMA_REQ_LPSPI2_RX,
.txch = DMA_REQ_LPSPI2_TX,
.rxsem = SEM_INITIALIZER(0),
.txsem = SEM_INITIALIZER(0),
#endif
.pincfg = CONFIG_S32K3XX_LPSPI2_PINCFG,
};
@ -393,9 +402,12 @@ static struct s32k3xx_lpspidev_s g_lpspi3dev =
#ifdef CONFIG_S32K3XX_LPSPI_INTERRUPTS
.spiirq = S32K3XX_IRQ_LPSPI3,
#endif
.lock = NXMUTEX_INITIALIZER,
#ifdef CONFIG_S32K3XX_LPSPI3_DMA
.rxch = DMA_REQ_LPSPI3_RX,
.txch = DMA_REQ_LPSPI3_TX,
.rxsem = SEM_INITIALIZER(0),
.txsem = SEM_INITIALIZER(0),
#endif
.pincfg = CONFIG_S32K3XX_LPSPI3_PINCFG,
};
@ -440,9 +452,12 @@ static struct s32k3xx_lpspidev_s g_lpspi4dev =
#ifdef CONFIG_S32K3XX_LPSPI_INTERRUPTS
.spiirq = S32K3XX_IRQ_LPSPI4,
#endif
.lock = NXMUTEX_INITIALIZER,
#ifdef CONFIG_S32K3XX_LPSPI4_DMA
.rxch = DMA_REQ_LPSPI4_RX,
.txch = DMA_REQ_LPSPI4_TX,
.rxsem = SEM_INITIALIZER(0),
.txsem = SEM_INITIALIZER(0),
#endif
.pincfg = CONFIG_S32K3XX_LPSPI4_PINCFG,
};
@ -487,9 +502,12 @@ static struct s32k3xx_lpspidev_s g_lpspi5dev =
#ifdef CONFIG_S32K3XX_LPSPI_INTERRUPTS
.spiirq = S32K3XX_IRQ_LPSPI5,
#endif
.lock = NXMUTEX_INITIALIZER,
#ifdef CONFIG_S32K3XX_LPSPI5_DMA
.rxch = DMA_REQ_LPSPI5_RX,
.txch = DMA_REQ_LPSPI5_TX,
.rxsem = SEM_INITIALIZER(0),
.txsem = SEM_INITIALIZER(0),
#endif
.pincfg = CONFIG_S32K3XX_LPSPI5_PINCFG,
};
@ -2013,10 +2031,6 @@ static void s32k3xx_lpspi_bus_initialize(struct s32k3xx_lpspidev_s *priv)
s32k3xx_lpspi_setmode((struct spi_dev_s *)priv, SPIDEV_MODE0);
/* Initialize the SPI mutex that enforces mutually exclusive access */
nxmutex_init(&priv->lock);
/* Enable LPSPI */
s32k3xx_lpspi_modifyreg32(priv, S32K3XX_LPSPI_CR_OFFSET, 0, LPSPI_CR_MEN);
@ -2369,17 +2383,10 @@ struct spi_dev_s *s32k3xx_lpspibus_initialize(int bus)
}
#ifdef CONFIG_S32K3XX_LPSPI_DMA
/* Initialize the SPI semaphores that is used to wait for DMA completion.
* This semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
if (priv->rxch && priv->txch)
{
if (priv->txdma == NULL && priv->rxdma == NULL)
{
nxsem_init(&priv->rxsem, 0, 0);
nxsem_init(&priv->txsem, 0, 0);
priv->txdma = s32k3xx_dmach_alloc(priv->txch | DMAMUX_CHCFG_ENBL,
0);
priv->rxdma = s32k3xx_dmach_alloc(priv->rxch | DMAMUX_CHCFG_ENBL,

24
arch/arm/src/s32k3xx/s32k3xx_qspi.c
View File

@ -226,14 +226,18 @@ static struct s32k3xx_qspidev_s g_qspi0dev =
.ops = &g_qspi0ops,
},
.base = S32K3XX_QSPI_BASE,
.lock = NXMUTEX_INITIALIZER,
#ifdef CONFIG_S32K3XX_QSPI_INTERRUPTS
.handler = qspi_interrupt,
.irq = S32K3XX_IRQ_QSPI,
.op_sem = SEM_INITIALIZER(0),
#endif
.intf = 0,
#ifdef CONFIG_S32K3XX_QSPI_DMA
.rxch = DMA_REQ_QSPI_RX,
.txch = DMA_REQ_QSPI_TX,
.rxsem = SEM_INITIALIZER(0),
.txsem = SEM_INITIALIZER(0),
#endif
};
@ -1785,13 +1789,7 @@ struct qspi_dev_s *s32k3xx_qspi_initialize(int intf)
if (!priv->initialized)
{
/* Now perform one time initialization.
*
* Initialize the QSPI semaphore that enforces mutually exclusive
* access to the QSPI registers.
*/
nxmutex_init(&priv->lock);
/* Now perform one time initialization. */
#ifdef CONFIG_S32K3XX_QSPI_INTERRUPTS
/* Attach the interrupt handler */
@ -1801,8 +1799,6 @@ struct qspi_dev_s *s32k3xx_qspi_initialize(int intf)
{
spierr("ERROR: Failed to attach irq %d\n", priv->irq);
}
nxsem_init(&priv->op_sem, 0, 0);
#endif
/* Perform hardware initialization. Puts the QSPI into an active
@ -1824,17 +1820,12 @@ struct qspi_dev_s *s32k3xx_qspi_initialize(int intf)
#endif
#ifdef CONFIG_S32K3XX_QSPI_DMA
/* Initialize the QSPI semaphores that is used to wait for DMA completion.
* This semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
/* Initialize the QSPI dma channel. */
if (priv->rxch && priv->txch)
{
if (priv->txdma == NULL && priv->rxdma == NULL)
{
nxsem_init(&priv->rxsem, 0, 0);
nxsem_init(&priv->txsem, 0, 0);
priv->txdma = s32k3xx_dmach_alloc(priv->txch
| DMAMUX_CHCFG_ENBL, 0);
priv->rxdma = s32k3xx_dmach_alloc(priv->rxch
@ -1851,9 +1842,6 @@ struct qspi_dev_s *s32k3xx_qspi_initialize(int intf)
}
return &priv->qspi;
nxmutex_destroy(&priv->lock);
return NULL;
}
#endif /* CONFIG_S32K3XX_QSPI */

3
arch/arm/src/sam34/sam_aes.c
View File

@ -59,7 +59,7 @@
* Private Data
****************************************************************************/
static mutex_t g_samaes_lock;
static mutex_t g_samaes_lock = NXMUTEX_INITIALIZER;
static bool g_samaes_initdone = false;
/****************************************************************************
@ -159,7 +159,6 @@ static int samaes_setup_mr(uint32_t keysize, int mode, int encrypt)
static int samaes_initialize(void)
{
nxmutex_init(&g_samaes_lock);
sam_aes_enableclk();
putreg32(AES_CR_SWRST, SAM_AES_CR);
return OK;

9
arch/arm/src/sam34/sam_dmac.c
View File

@ -104,8 +104,8 @@ struct sam_dma_s
/* These mutex protect the DMA channel and descriptor tables */
static mutex_t g_chlock;
static sem_t g_dsem;
static mutex_t g_chlock = NXMUTEX_INITIALIZER;
static sem_t g_dsem = SEM_INITIALIZER(CONFIG_SAM34_NLLDESC);
/* CTRLA field lookups */
@ -1340,11 +1340,6 @@ void weak_function arm_dma_initialize(void)
/* Enable the DMA controller */
putreg32(DMAC_EN_ENABLE, SAM_DMAC_EN);
/* Initialize mutex & semaphores */
nxmutex_init(&g_chlock);
nxsem_init(&g_dsem, 0, CONFIG_SAM34_NLLDESC);
}
/****************************************************************************

4
arch/arm/src/sam34/sam_hsmci.c
View File

@ -542,6 +542,7 @@ struct sam_dev_s g_sdiodev =
.dmasendsetup = sam_dmasendsetup,
#endif
},
.waitsem = SEM_INITIALIZER(0),
};
/* Register logging support */
@ -2699,9 +2700,6 @@ struct sdio_dev_s *sdio_initialize(int slotno)
/* Initialize the HSMCI slot structure */
/* Initialize semaphores */
nxsem_init(&priv->waitsem, 0, 0);
#ifdef CONFIG_SAM34_DMAC0
/* Allocate a DMA channel. A FIFO size of 8 is sufficient. */

7
arch/arm/src/sam34/sam_spi.c
View File

@ -322,6 +322,7 @@ static const struct spi_ops_s g_spi0ops =
static struct sam_spidev_s g_spi0dev =
{
.base = SAM_SPI0_BASE,
.spilock = NXMUTEX_INITIALIZER,
.select = sam_spi0select,
#ifdef CONFIG_SAM34_SPI_DMA
.rxintf = DMACHAN_INTF_SPI0RX,
@ -359,6 +360,7 @@ static const struct spi_ops_s g_spi1ops =
static struct sam_spidev_s g_spi1dev =
{
.base = SAM_SPI1_BASE,
.spilock = NXMUTEX_INITIALIZER,
.select = sam_spi1select,
#ifdef CONFIG_SAM34_SPI_DMA
.rxintf = DMACHAN_INTF_SPI1RX,
@ -1857,11 +1859,6 @@ struct spi_dev_s *sam_spibus_initialize(int port)
spi_getreg(spi, SAM_SPI_SR_OFFSET);
spi_getreg(spi, SAM_SPI_RDR_OFFSET);
/* Initialize the SPI mutex that enforces mutually exclusive
* access to the SPI registers.
*/
nxmutex_init(&spi->spilock);
spi->initialized = true;
#ifdef CONFIG_SAM34_SPI_DMA

64
arch/arm/src/sam34/sam_twi.c
View File

@ -187,21 +187,43 @@ static void twi_hw_initialize(struct twi_dev_s *priv, unsigned int pid,
* Private Data
****************************************************************************/
static const struct i2c_ops_s g_twiops =
{
.transfer = twi_transfer,
#ifdef CONFIG_I2C_RESET
.reset = twi_reset
#endif
};
#ifdef CONFIG_SAM34_TWIM0
static struct twi_dev_s g_twi0;
static struct twi_dev_s g_twi0 =
{
.dev =
{
.ops = g_twiops,
},
.base = SAM_TWI0_BASE,
.irq = SAM_IRQ_TWI0,
.twi = 0,
.lock = NXMUTEX_INITIALIZER,
.waitsem = SEM_INITIALIZER(0),
};
#endif
#ifdef CONFIG_SAM34_TWIM1
static struct twi_dev_s g_twi1;
#endif
static const struct i2c_ops_s g_twiops =
static struct twi_dev_s g_twi1 =
{
.transfer = twi_transfer
#ifdef CONFIG_I2C_RESET
, .reset = twi_reset
#endif
.dev =
{
.ops = g_twiops,
},
.base = SAM_TWI1_BASE,
.irq = SAM_IRQ_TWI1,
.twi = 1,
.lock = NXMUTEX_INITIALIZER,
.waitsem = SEM_INITIALIZER(0),
};
#endif
/****************************************************************************
* Private Functions
@ -891,12 +913,7 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus)
#ifdef CONFIG_SAM34_TWIM0
if (bus == 0)
{
/* Set up TWI0 register base address and IRQ number */
priv = &g_twi0;
priv->base = SAM_TWI0_BASE;
priv->irq = SAM_IRQ_TWI0;
priv->twi = 0;
/* Enable peripheral clocking */
@ -917,12 +934,7 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus)
#ifdef CONFIG_SAM34_TWIM1
if (bus == 1)
{
/* Set up TWI1 register base address and IRQ number */
priv = &g_twi1;
priv->base = SAM_TWI1_BASE;
priv->irq = SAM_IRQ_TWI1;
priv->twi = 1;
/* Enable peripheral clocking */
@ -946,15 +958,6 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus)
return NULL;
}
/* Initialize the device structure */
priv->dev.ops = &g_twiops;
/* Initialize mutex & semaphores */
nxmutex_init(&priv->lock);
nxsem_init(&priv->waitsem, 0, 0);
/* Configure and enable the TWI hardware */
priv->pid = pid;
@ -989,11 +992,6 @@ int sam_i2cbus_uninitialize(struct i2c_master_s * dev)
up_disable_irq(priv->irq);
/* Reset data structures */
nxmutex_destroy(&priv->lock);
nxsem_destroy(&priv->waitsem);
/* Cancel the watchdog timer */
wd_cancel(&priv->timeout);

21
arch/arm/src/sama5/sam_adc.c
View File

@ -497,11 +497,20 @@ static const struct adc_ops_s g_adcops =
/* ADC internal state */
static struct sam_adc_s g_adcpriv;
static struct sam_adc_s g_adcpriv =
{
.lock = NXMUTEX_INITIALIZER,
};
/* ADC device instance */
static struct adc_dev_s g_adcdev;
static struct adc_dev_s g_adcdev =
{
#ifdef SAMA5_ADC_HAVE_CHANNELS
.ad_ops = &g_adcops,
#endif
.ad_priv = &g_adcpriv,
};
/****************************************************************************
* Private Functions
@ -2041,17 +2050,9 @@ struct adc_dev_s *sam_adc_initialize(void)
/* Initialize the public ADC device data structure */
#ifdef SAMA5_ADC_HAVE_CHANNELS
g_adcdev.ad_ops = &g_adcops;
priv->dev = &g_adcdev;
#endif
g_adcdev.ad_priv = priv;
/* Initialize the private ADC device data structure */
nxmutex_init(&priv->lock);
priv->cb = NULL;
#ifdef CONFIG_SAMA5_ADC_DMA
/* Allocate a DMA channel from DMAC1 */

37
arch/arm/src/sama5/sam_can.c
View File

@ -287,8 +287,17 @@ static const struct sam_config_s g_can0const =
},
};
static struct sam_can_s g_can0priv;
static struct can_dev_s g_can0dev;
static struct sam_can_s g_can0priv =
{
.config = &g_can0const,
.freemb = CAN_ALL_MAILBOXES,
.lock = NXMUTEX_INITIALIZER,
};
static struct can_dev_s g_can0dev =
{
.cd_ops = &g_canops,
.cd_priv = &g_can0priv,
};
#endif
#ifdef CONFIG_SAMA5_CAN1
@ -322,8 +331,17 @@ static const struct sam_config_s g_can1const =
},
};
static struct sam_can_s g_can1priv;
static struct can_dev_s g_can1dev;
static struct sam_can_s g_can1priv =
{
.config = &g_can1const,
.freemb = CAN_ALL_MAILBOXES,
.lock = NXMUTEX_INITIALIZER,
};
static struct can_dev_s g_can1dev =
{
.cd_ops = &g_canops,
.cd_priv = &g_can1priv,
};
#endif
/****************************************************************************
@ -1902,7 +1920,6 @@ struct can_dev_s *sam_caninitialize(int port)
{
struct can_dev_s *dev;
struct sam_can_s *priv;
const struct sam_config_s *config;
caninfo("CAN%d\n", port);
@ -1917,7 +1934,6 @@ struct can_dev_s *sam_caninitialize(int port)
dev = &g_can0dev;
priv = &g_can0priv;
config = &g_can0const;
}
else
#endif
@ -1928,7 +1944,6 @@ struct can_dev_s *sam_caninitialize(int port)
dev = &g_can1dev;
priv = &g_can1priv;
config = &g_can1const;
}
else
#endif
@ -1943,16 +1958,8 @@ struct can_dev_s *sam_caninitialize(int port)
{
/* Yes, then perform one time data initialization */
memset(priv, 0, sizeof(struct sam_can_s));
priv->config = config;
priv->freemb = CAN_ALL_MAILBOXES;
priv->initialized = true;
nxmutex_init(&priv->lock);
dev->cd_ops = &g_canops;
dev->cd_priv = (void *)priv;
/* And put the hardware in the initial state */
can_reset(dev);

11
arch/arm/src/sama5/sam_dmac.c
View File

@ -342,6 +342,9 @@ static struct sam_dmach_s g_dmach0[SAM_NDMACHAN] =
static struct sam_dmac_s g_dmac0 =
{
.chlock = NXMUTEX_INITIALIZER,
.dsem = SEM_INITIALIZER(SAM_NDMACHAN),
/* DMAC 0 base address */
.base = SAM_DMAC0_VBASE,
@ -444,6 +447,9 @@ static struct sam_dmach_s g_dmach1[SAM_NDMACHAN] =
static struct sam_dmac_s g_dmac1 =
{
.chlock = NXMUTEX_INITIALIZER,
.dsem = SEM_INITIALIZER(SAM_NDMACHAN),
/* DMAC 0 base address */
.base = SAM_DMAC1_VBASE,
@ -1854,11 +1860,6 @@ void sam_dmainitialize(struct sam_dmac_s *dmac)
/* Enable the DMA controller */
sam_putdmac(dmac, DMAC_EN_ENABLE, SAM_DMAC_EN_OFFSET);
/* Initialize muttex & semaphores */
nxmutex_init(&dmac->chlock);
nxsem_init(&dmac->dsem, 0, SAM_NDMACHAN);
}
/****************************************************************************

16
arch/arm/src/sama5/sam_ehci.c
View File

@ -435,7 +435,12 @@ static int sam_reset(void);
* global instance.
*/
static struct sam_ehci_s g_ehci;
static struct sam_ehci_s g_ehci =
{
.lock = NXMUTEX_INITIALIZER,
.pscsem = SEM_INITIALIZER(0),
.ep0.iocsem = SEM_INITIALIZER(1),
};
/* This is the connection/enumeration interface */
@ -4820,15 +4825,6 @@ struct usbhost_connection_s *sam_ehci_initialize(int controller)
usbhost_vtrace1(EHCI_VTRACE1_INITIALIZING, 0);
/* Initialize the EHCI state data structure */
nxmutex_init(&g_ehci.lock);
nxsem_init(&g_ehci.pscsem, 0, 0);
/* Initialize EP0 */
nxsem_init(&g_ehci.ep0.iocsem, 0, 1);
/* Initialize the root hub port structures */
for (i = 0; i < SAM_EHCI_NRHPORT; i++)

131
arch/arm/src/sama5/sam_hsmci.c
View File

@ -596,9 +596,12 @@ static void sam_callback(void *arg);
* Private Data
****************************************************************************/
/* Callbacks */
/* Pre-allocate memory for each HSMCI device */
static const struct sdio_dev_s g_callbacks =
#ifdef CONFIG_SAMA5_HSMCI0
static struct sam_dev_s g_hsmci0 =
{
.dev =
{
.reset = sam_reset,
.capabilities = sam_capabilities,
@ -635,18 +638,103 @@ static const struct sdio_dev_s g_callbacks =
.dmasendsetup = sam_sendsetup,
#endif
#endif
},
.waitsem = SEM_INITIALIZER(0),
.base = SAM_HSMCI0_VBASE,
.hsmci = 0,
};
/* Pre-allocate memory for each HSMCI device */
#ifdef CONFIG_SAMA5_HSMCI0
static struct sam_dev_s g_hsmci0;
#endif
#ifdef CONFIG_SAMA5_HSMCI1
static struct sam_dev_s g_hsmci1;
static struct sam_dev_s g_hsmci1 =
{
.dev =
{
.reset = sam_reset,
.capabilities = sam_capabilities,
.status = sam_status,
.widebus = sam_widebus,
.clock = sam_clock,
.attach = sam_attach,
.sendcmd = sam_sendcmd,
.blocksetup = sam_blocksetup,
.recvsetup = sam_recvsetup,
.sendsetup = sam_sendsetup,
.cancel = sam_cancel,
.waitresponse = sam_waitresponse,
.recv_r1 = sam_recvshort,
.recv_r2 = sam_recvlong,
.recv_r3 = sam_recvshort,
.recv_r4 = sam_recvnotimpl,
.recv_r5 = sam_recvnotimpl,
.recv_r6 = sam_recvshort,
.recv_r7 = sam_recvshort,
.waitenable = sam_waitenable,
.eventwait = sam_eventwait,
.callbackenable = sam_callbackenable,
.registercallback = sam_registercallback,
#ifdef CONFIG_SDIO_DMA
#ifndef HSCMI_NORXDMA
.dmarecvsetup = sam_dmarecvsetup,
#else
.dmarecvsetup = sam_recvsetup,
#endif
#ifndef HSCMI_NOTXDMA
.dmasendsetup = sam_dmasendsetup,
#else
.dmasendsetup = sam_sendsetup,
#endif
#endif
},
.waitsem = SEM_INITIALIZER(0),
.base = SAM_HSMCI0_VBASE,
.hsmci = 0,
};
#endif
#ifdef CONFIG_SAMA5_HSMCI2
static struct sam_dev_s g_hsmci2;
static struct sam_dev_s g_hsmci2 =
{
.dev =
{
.reset = sam_reset,
.capabilities = sam_capabilities,
.status = sam_status,
.widebus = sam_widebus,
.clock = sam_clock,
.attach = sam_attach,
.sendcmd = sam_sendcmd,
.blocksetup = sam_blocksetup,
.recvsetup = sam_recvsetup,
.sendsetup = sam_sendsetup,
.cancel = sam_cancel,
.waitresponse = sam_waitresponse,
.recv_r1 = sam_recvshort,
.recv_r2 = sam_recvlong,
.recv_r3 = sam_recvshort,
.recv_r4 = sam_recvnotimpl,
.recv_r5 = sam_recvnotimpl,
.recv_r6 = sam_recvshort,
.recv_r7 = sam_recvshort,
.waitenable = sam_waitenable,
.eventwait = sam_eventwait,
.callbackenable = sam_callbackenable,
.registercallback = sam_registercallback,
#ifdef CONFIG_SDIO_DMA
#ifndef HSCMI_NORXDMA
.dmarecvsetup = sam_dmarecvsetup,
#else
.dmarecvsetup = sam_recvsetup,
#endif
#ifndef HSCMI_NOTXDMA
.dmasendsetup = sam_dmasendsetup,
#else
.dmasendsetup = sam_sendsetup,
#endif
#endif
},
.waitsem = SEM_INITIALIZER(0),
.base = SAM_HSMCI0_VBASE,
.hsmci = 0,
};
#endif
/****************************************************************************
@ -3193,11 +3281,6 @@ struct sdio_dev_s *sdio_initialize(int slotno)
priv = &g_hsmci0;
/* HSMCI0 Initialization */
priv->base = SAM_HSMCI0_VBASE;
priv->hsmci = 0;
/* Configure PIOs for 4-bit, wide-bus operation. NOTE: (1) the chip
* is capable of 8-bit wide bus operation but D4-D7 are not configured,
* (2) any card detection PIOs must be set up in board-specific logic.
@ -3232,11 +3315,6 @@ struct sdio_dev_s *sdio_initialize(int slotno)
priv = &g_hsmci1;
/* HSMCI1 Initialization */
priv->base = SAM_HSMCI1_VBASE;
priv->hsmci = 1;
/* Configure PIOs for 4-bit, wide-bus operation. NOTE: (1) the chip
* is capable of 8-bit wide bus operation but D4-D7 are not configured,
* (2) any card detection PIOs must be set up in board-specific logic.
@ -3271,11 +3349,6 @@ struct sdio_dev_s *sdio_initialize(int slotno)
priv = &g_hsmci2;
/* HSMCI2 Initialization */
priv->base = SAM_HSMCI2_VBASE;
priv->hsmci = 2;
/* Configure PIOs for 4-bit, wide-bus operation. NOTE: (1) the chip
* is capable of 8-bit wide bus operation but D4-D7 are not configured,
* (2) any card detection PIOs must be set up in board-specific logic.
@ -3312,16 +3385,6 @@ struct sdio_dev_s *sdio_initialize(int slotno)
" hsmci: %d dmac: %d pid: %" PRId32 "\n",
priv, priv->base, priv->hsmci, dmac, pid);
/* Initialize the HSMCI slot structure */
/* Initialize semaphores */
nxsem_init(&priv->waitsem, 0, 0);
/* Initialize the callbacks */
memcpy(&priv->dev, &g_callbacks, sizeof(struct sdio_dev_s));
/* Allocate a DMA channel */
priv->dma = sam_dmachannel(dmac, DMA_FLAGS(pid));

60
arch/arm/src/sama5/sam_nand.c
View File

@ -272,16 +272,36 @@ static void nand_reset(struct sam_nandcs_s *priv);
*/
#ifdef CONFIG_SAMA5_EBICS0_NAND
static struct sam_nandcs_s g_cs0nand;
static struct sam_nandcs_s g_cs0nand =
{
#ifdef CONFIG_SAMA5_NAND_DMA
.waitsem = SEM_INITIALIZER(0)
#endif
};
#endif
#ifdef CONFIG_SAMA5_EBICS1_NAND
static struct sam_nandcs_s g_cs1nand;
static struct sam_nandcs_s g_cs1nand =
{
#ifdef CONFIG_SAMA5_NAND_DMA
.waitsem = SEM_INITIALIZER(0)
#endif
};
#endif
#ifdef CONFIG_SAMA5_EBICS2_NAND
static struct sam_nandcs_s g_cs2nand;
static struct sam_nandcs_s g_cs2nand =
{
#ifdef CONFIG_SAMA5_NAND_DMA
.waitsem = SEM_INITIALIZER(0)
#endif
};
#endif
#ifdef CONFIG_SAMA5_EBICS3_NAND
static struct sam_nandcs_s g_cs3nand;
static struct sam_nandcs_s g_cs3nand =
{
#ifdef CONFIG_SAMA5_NAND_DMA
.waitsem = SEM_INITIALIZER(0)
#endif
};
#endif
/****************************************************************************
@ -290,7 +310,15 @@ static struct sam_nandcs_s g_cs3nand;
/* NAND global state */
struct sam_nand_s g_nand;
struct sam_nand_s g_nand =
{
#if NAND_NBANKS > 1
.lock = NXMUTEX_INITIALIZER,
#endif
#ifdef CONFIG_SAMA5_NAND_HSMCINTERRUPTS
.waitsem = SEM_INITIALIZER(0),
#endif
};
/****************************************************************************
* Private Functions
@ -2966,7 +2994,6 @@ struct mtd_dev_s *sam_nand_initialize(int cs)
/* Initialize the device structure */
memset(priv, 0, sizeof(struct sam_nandcs_s));
priv->raw.cmdaddr = cmdaddr;
priv->raw.addraddr = addraddr;
priv->raw.dataaddr = dataaddr;
@ -2980,34 +3007,15 @@ struct mtd_dev_s *sam_nand_initialize(int cs)
#endif
priv->cs = cs;
#ifdef CONFIG_SAMA5_NAND_DMA
nxsem_init(&priv->waitsem, 0, 0);
#endif
/* Perform one-time, global NFC/PMECC initialization */
if (!g_nand.initialized)
{
/* Initialize the global nand state structure */
#if NAND_NBANKS > 1
nxmutex_init(&g_nand.lock);
#endif
#ifdef CONFIG_SAMA5_NAND_HSMCINTERRUPTS
nxsem_init(&g_nand.waitsem, 0, 0);
#endif
/* Enable the NAND FLASH Controller (The NFC is always used) */
nand_putreg(SAM_HSMC_CTRL, HSMC_CTRL_NFCEN);
#ifdef CONFIG_SAMA5_HAVE_PMECC
/* Perform one-time initialization of the PMECC */
pmecc_initialize();
#else
#ifndef CONFIG_SAMA5_HAVE_PMECC
/* Disable the PMECC if it is not being used */
nand_putreg(SAM_HSMC_PMECCTRL, HSMC_PMECCTRL_RST);

11
arch/arm/src/sama5/sam_ohci.c
View File

@ -461,7 +461,11 @@ static void sam_disconnect(struct usbhost_driver_s *drvr,
* single global instance.
*/
static struct sam_ohci_s g_ohci;
static struct sam_ohci_s g_ohci =
{
.lock = NXMUTEX_INITIALIZER,
.pscsem = SEM_INITIALIZER(0),
};
/* This is the connection/enumeration interface */
@ -3954,11 +3958,6 @@ struct usbhost_connection_s *sam_ohci_initialize(int controller)
DEBUGASSERT(sizeof(struct sam_ed_s) == SIZEOF_SAM_ED_S);
DEBUGASSERT(sizeof(struct sam_gtd_s) == SIZEOF_SAM_TD_S);
/* Initialize the state data structure */
nxsem_init(&g_ohci.pscsem, 0, 0);
nxmutex_init(&g_ohci.lock);
#ifndef CONFIG_USBHOST_INT_DISABLE
g_ohci.ininterval = MAX_PERINTERVAL;
g_ohci.outinterval = MAX_PERINTERVAL;

27
arch/arm/src/sama5/sam_pmecc.c
View File

@ -172,7 +172,10 @@ static uint32_t pmecc_correctionalgo(uint32_t isr, uintptr_t data);
/* PMECC state data */
static struct sam_pmecc_s g_pmecc;
static struct sam_pmecc_s g_pmecc =
{
.lock = NXMUTEX_INITIALIZER,
};
/* Maps BCH_ERR correctability register value to number of errors per
* sector.
@ -999,28 +1002,6 @@ static int pmecc_pagelayout(uint16_t datasize, uint16_t eccsize)
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: pmecc_initialize
*
* Description:
* Perform one-time PMECC initialization. This must be called before any
* other PMECC interfaces are used.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#if NAND_NPMECC_BANKS > 1
void pmecc_initialize(void)
{
nxmutex_init(&g_pmecc.lock);
}
#endif
/****************************************************************************
* Name: pmecc_configure
*

22
arch/arm/src/sama5/sam_pmecc.h
View File

@ -294,27 +294,6 @@ void pmecc_enable(void);
void pmecc_disable(void);
/****************************************************************************
* Name: pmecc_initialize
*
* Description:
* Perform one-time PMECC initialization. This must be called before any
* other PMECC interfaces are used.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#if NAND_NPMECC_BANKS > 1
void pmecc_initialize(void);
#else
# define pmecc_initialize()
#endif
/****************************************************************************
* Name: pmecc_configure
*
@ -417,7 +396,6 @@ void pmecc_buildgf(uint32_t mm, int16_t *indexof, int16_t *alphato);
# define pmecc_unlock()
# define pmecc_enable()
# define pmecc_disable()
# define pmecc_initialize()
# define pmecc_configure(a,b) (0)
# define pmecc_get_eccsize() (0)
# define pmecc_get_pagesize() (0)

12
arch/arm/src/sama5/sam_sdmmc.c
View File

@ -425,7 +425,8 @@ struct sam_dev_s g_sdmmcdev[SAM_MAX_SDMMC_DEV_SLOTS] =
.dmasendsetup = sam_sendsetup,
#endif
#endif
}
},
.waitsem = SEM_INITIALIZER(0),
},
#endif
@ -482,7 +483,8 @@ struct sam_dev_s g_sdmmcdev[SAM_MAX_SDMMC_DEV_SLOTS] =
.dmarecvsetup = sam_recvsetup,
.dmasendsetup = sam_sendsetup,
#endif
}
},
.waitsem = SEM_INITIALIZER(0),
}
#endif
#endif
@ -3588,11 +3590,7 @@ struct sdio_dev_s *sam_sdmmc_sdio_initialize(int slotno)
struct sam_dev_s *priv = &g_sdmmcdev[slotno];
/* Initialize the SDMMC slot structure data structure
* Initialize semaphores
*/
nxsem_init(&priv->waitsem, 0, 0);
/* Initialize the SDMMC slot structure data structure */
switch (priv->addr)
{

7
arch/arm/src/sama5/sam_spi.c
View File

@ -309,6 +309,7 @@ static const struct spi_ops_s g_spi0ops =
static struct sam_spidev_s g_spi0dev =
{
.base = SAM_SPI0_VBASE,
.spilock = NXMUTEX_INITIALIZER,
.select = sam_spi0select,
#ifdef CONFIG_SAMA5_SPI_DMA
.pid = SAM_PID_SPI0,
@ -345,6 +346,7 @@ static const struct spi_ops_s g_spi1ops =
static struct sam_spidev_s g_spi1dev =
{
.base = SAM_SPI1_VBASE,
.spilock = NXMUTEX_INITIALIZER,
.select = sam_spi1select,
#ifdef CONFIG_SAMA5_SPI_DMA
.pid = SAM_PID_SPI1,
@ -1783,11 +1785,6 @@ struct spi_dev_s *sam_spibus_initialize(int port)
spi_getreg(spi, SAM_SPI_SR_OFFSET);
spi_getreg(spi, SAM_SPI_RDR_OFFSET);
/* Initialize the SPI mutex that enforces mutually exclusive
* access to the SPI registers.
*/
nxmutex_init(&spi->spilock);
spi->initialized = true;
#ifdef CONFIG_SAMA5_SPI_DMA

50
arch/arm/src/sama5/sam_tc.c
View File

@ -98,10 +98,7 @@ struct sam_chconfig_s
struct sam_tcconfig_s
{
uintptr_t base; /* TC register base address */
uint8_t pid; /* Peripheral ID */
uint8_t chfirst; /* First channel number */
uint8_t tc; /* Timer/counter number */
/* Channels */
@ -201,10 +198,7 @@ static inline struct sam_chan_s *sam_tc_initialize(int channel);
#ifdef CONFIG_SAMA5_TC0
static const struct sam_tcconfig_s g_tc012config =
{
.base = SAM_TC012_VBASE,
.pid = SAM_PID_TC0,
.chfirst = 0,
.tc = 0,
.channel =
{
[0] =
@ -271,10 +265,7 @@ static const struct sam_tcconfig_s g_tc012config =
#ifdef CONFIG_SAMA5_TC1
static const struct sam_tcconfig_s g_tc345config =
{
.base = SAM_TC345_VBASE,
.pid = SAM_PID_TC1,
.chfirst = 3,
.tc = 1,
.channel =
{
[0] =
@ -341,10 +332,7 @@ static const struct sam_tcconfig_s g_tc345config =
#ifdef CONFIG_SAMA5_TC2
static const struct sam_tcconfig_s g_tc678config =
{
.base = SAM_TC678_VBASE,
.pid = SAM_PID_TC2,
.chfirst = 6,
.tc = 2,
.channel =
{
[0] =
@ -411,15 +399,33 @@ static const struct sam_tcconfig_s g_tc678config =
/* Timer/counter state */
#ifdef CONFIG_SAMA5_TC0
static struct sam_tc_s g_tc012;
static struct sam_tc_s g_tc012 =
{
.lock = NXMUTEX_INITIALIZER,
.base = SAM_TC012_VBASE,
.pid = SAM_PID_TC0,
.tc = 0,
};
#endif
#ifdef CONFIG_SAMA5_TC1
static struct sam_tc_s g_tc345;
static struct sam_tc_s g_tc345 =
{
.lock = NXMUTEX_INITIALIZER,
.base = SAM_TC345_VBASE,
.pid = SAM_PID_TC1,
.tc = 1,
};
#endif
#ifdef CONFIG_SAMA5_TC2
static struct sam_tc_s g_tc678;
static struct sam_tc_s g_tc678 =
{
.lock = NXMUTEX_INITIALIZER,
.base = SAM_TC678_VBASE,
.pid = SAM_PID_TC2,
.tc = 2,
};
#endif
/* TC frequency data.
@ -954,19 +960,11 @@ static inline struct sam_chan_s *sam_tc_initialize(int channel)
flags = enter_critical_section();
if (!tc->initialized)
{
/* Initialize the timer counter data structure. */
memset(tc, 0, sizeof(struct sam_tc_s));
nxmutex_init(&tc->lock);
tc->base = tcconfig->base;
tc->tc = channel < 3 ? 0 : 1;
tc->pid = tcconfig->pid;
/* Initialize the channels */
for (i = 0, ch = tcconfig->chfirst; i < SAM_TC_NCHANNELS; i++)
{
tmrerr("ERROR: Initializing TC%d channel %d\n", tcconfig->tc, ch);
tmrerr("ERROR: Initializing TC%d channel %d\n", tc->tc, ch);
/* Initialize the channel data structure */
@ -1008,7 +1006,7 @@ static inline struct sam_chan_s *sam_tc_initialize(int channel)
/* Set the maximum TC peripheral clock frequency */
regval = PMC_PCR_PID(tcconfig->pid) | PMC_PCR_CMD | PMC_PCR_EN;
regval = PMC_PCR_PID(tc->pid) | PMC_PCR_CMD | PMC_PCR_EN;
#ifdef SAMA5_HAVE_PMC_PCR_DIV
/* Set the MCK divider (if any) */
@ -1020,7 +1018,7 @@ static inline struct sam_chan_s *sam_tc_initialize(int channel)
/* Enable clocking to the timer counter */
sam_enableperiph0(tcconfig->pid);
sam_enableperiph0(tc->pid);
/* Attach the timer interrupt handler and enable the timer interrupts */

15
arch/arm/src/sama5/sam_trng.c
View File

@ -74,7 +74,11 @@ struct trng_dev_s
* Private Data
****************************************************************************/
static struct trng_dev_s g_trngdev;
static struct trng_dev_s g_trngdev =
{
.lock = NXMUTEX_INITIALIZER,
.waitsem = SEM_INITIALIZER(0),
};
static const struct file_operations g_trngops =
{
@ -333,15 +337,6 @@ static int sam_rng_initialize(void)
finfo("Initializing TRNG hardware\n");
/* Initialize the device structure */
memset(&g_trngdev, 0, sizeof(struct trng_dev_s));
/* Initialize mutex & semphores */
nxmutex_init(&g_trngdev.lock);
nxsem_init(&g_trngdev.waitsem, 0, 0);
/* Enable clocking to the TRNG */
sam_trng_enableclk();

17
arch/arm/src/sama5/sam_tsd.c
View File

@ -245,7 +245,12 @@ static const struct file_operations g_tsdops =
/* The driver state structure is pre-allocated. */
static struct sam_tsd_s g_tsd;
static struct sam_tsd_s g_tsd =
{
.threshx = INVALID_THRESHOLD,
.threshy = INVALID_THRESHOLD,
.waitsem = SEM_INITIALIZER(0),
};
/****************************************************************************
* Private Functions
@ -1650,11 +1655,7 @@ int sam_tsd_register(struct sam_adc_s *adc, int minor)
/* Initialize the touchscreen device driver instance */
memset(priv, 0, sizeof(struct sam_tsd_s));
priv->adc = adc; /* Save the ADC device handle */
priv->threshx = INVALID_THRESHOLD; /* Initialize thresholding logic */
priv->threshy = INVALID_THRESHOLD; /* Initialize thresholding logic */
nxsem_init(&priv->waitsem, 0, 0);
/* Register the device as an input device */
@ -1665,7 +1666,7 @@ int sam_tsd_register(struct sam_adc_s *adc, int minor)
if (ret < 0)
{
ierr("ERROR: register_driver() failed: %d\n", ret);
goto errout_with_priv;
return ret;
}
/* And return success. The hardware will be initialized as soon as the
@ -1673,10 +1674,6 @@ int sam_tsd_register(struct sam_adc_s *adc, int minor)
*/
return OK;
errout_with_priv:
nxsem_destroy(&priv->waitsem);
return ret;
}
/****************************************************************************

96
arch/arm/src/sama5/sam_twi.c
View File

@ -229,6 +229,14 @@ static void twi_hw_initialize(struct twi_dev_s *priv, uint32_t frequency);
* Private Data
****************************************************************************/
static const struct i2c_ops_s g_twiops =
{
.transfer = twi_transfer,
#ifdef CONFIG_I2C_RESET
.reset = twi_reset
#endif
};
#ifdef CONFIG_SAMA5_TWI0
static const struct twi_attr_s g_twi0attr =
{
@ -240,7 +248,16 @@ static const struct twi_attr_s g_twi0attr =
.base = SAM_TWI0_VBASE,
};
static struct twi_dev_s g_twi0;
static struct twi_dev_s g_twi0 =
{
.dev =
{
.ops = &g_twiops,
},
.attr = &g_twi0attr,
.lock = NXMUTEX_INITIALIZER,
.waitsem = SEM_INITIALIZER(0),
};
#endif
#ifdef CONFIG_SAMA5_TWI1
@ -254,7 +271,16 @@ static const struct twi_attr_s g_twi1attr =
.base = SAM_TWI1_VBASE,
};
static struct twi_dev_s g_twi1;
static struct twi_dev_s g_twi1 =
{
.dev =
{
.ops = &g_twiops,
},
.attr = &g_twi1attr,
.lock = NXMUTEX_INITIALIZER,
.waitsem = SEM_INITIALIZER(0),
};
#endif
#ifdef CONFIG_SAMA5_TWI2
@ -268,7 +294,16 @@ static const struct twi_attr_s g_twi2attr =
.base = SAM_TWI2_VBASE,
};
static struct twi_dev_s g_twi2;
static struct twi_dev_s g_twi2 =
{
.dev =
{
.ops = &g_twiops,
},
.attr = &g_twi2attr,
.lock = NXMUTEX_INITIALIZER,
.waitsem = SEM_INITIALIZER(0),
};
#endif
#ifdef CONFIG_SAMA5_TWI3
@ -282,16 +317,17 @@ static const struct twi_attr_s g_twi3attr =
.base = SAM_TWI3_VBASE,
};
static struct twi_dev_s g_twi3;
#endif
static const struct i2c_ops_s g_twiops =
static struct twi_dev_s g_twi3 =
{
.transfer = twi_transfer
#ifdef CONFIG_I2C_RESET
, .reset = twi_reset
#endif
.dev =
{
.ops = &g_twiops,
},
.attr = &g_twi3attr,
.lock = NXMUTEX_INITIALIZER,
.waitsem = SEM_INITIALIZER(0),
};
#endif
/****************************************************************************
* Private Functions
@ -1177,13 +1213,9 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus)
#ifdef CONFIG_SAMA5_TWI0
if (bus == 0)
{
/* Select up TWI0 and setup invariant attributes */
/* Select up TWI0 and the (initial) TWI frequency */
priv = &g_twi0;
priv->attr = &g_twi0attr;
/* Select the (initial) TWI frequency */
frequency = CONFIG_SAMA5_TWI0_FREQUENCY;
}
else
@ -1191,13 +1223,9 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus)
#ifdef CONFIG_SAMA5_TWI1
if (bus == 1)
{
/* Select up TWI1 and setup invariant attributes */
/* Select up TWI1 and the (initial) TWI frequency */
priv = &g_twi1;
priv->attr = &g_twi1attr;
/* Select the (initial) TWI frequency */
frequency = CONFIG_SAMA5_TWI1_FREQUENCY;
}
else
@ -1205,13 +1233,9 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus)
#ifdef CONFIG_SAMA5_TWI2
if (bus == 2)
{
/* Select up TWI2 and setup invariant attributes */
/* Select up TWI2 and the (initial) TWI frequency */
priv = &g_twi2;
priv->attr = &g_twi2attr;
/* Select the (initial) TWI frequency */
frequency = CONFIG_SAMA5_TWI2_FREQUENCY;
}
else
@ -1219,13 +1243,9 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus)
#ifdef CONFIG_SAMA5_TWI3
if (bus == 3)
{
/* Select up TWI3 and setup invariant attributes */
/* Select up TWI3 and the (initial) TWI frequency */
priv = &g_twi3;
priv->attr = &g_twi3attr;
/* Select the (initial) TWI frequency */
frequency = CONFIG_SAMA5_TWI3_FREQUENCY;
}
else
@ -1248,15 +1268,6 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus)
goto errout_with_lock;
}
/* Initialize the TWI driver structure */
priv->dev.ops = &g_twiops;
/* Initialize mutex & semaphores */
nxmutex_init(&priv->lock);
nxsem_init(&priv->waitsem, 0, 0);
/* Perform repeatable TWI hardware initialization */
twi_hw_initialize(priv, frequency);
@ -1286,11 +1297,6 @@ int sam_i2cbus_uninitialize(struct i2c_master_s *dev)
up_disable_irq(priv->attr->irq);
/* Reset data structures */
nxmutex_destroy(&priv->lock);
nxsem_destroy(&priv->waitsem);
/* Cancel the watchdog timer */
wd_cancel(&priv->timeout);

11
arch/arm/src/sama5/sam_xdmac.c
View File

@ -539,6 +539,9 @@ static struct sam_xdmach_s g_xdmach0[SAM_NDMACHAN] =
static struct sam_xdmac_s g_xdmac0 =
{
.chlock = NXMUTEX_INITIALIZER,
.dsem = SEM_INITIALIZER(SAM_NDMACHAN),
/* XDMAC 0 base address */
.base = SAM_XDMAC0_VBASE,
@ -713,6 +716,9 @@ static struct sam_xdmach_s g_xdmach1[SAM_NDMACHAN] =
static struct sam_xdmac_s g_xdmac1 =
{
.chlock = NXMUTEX_INITIALIZER,
.dsem = SEM_INITIALIZER(SAM_NDMACHAN),
/* XDMAC 0 base address */
.base = SAM_XDMAC1_VBASE,
@ -1979,11 +1985,6 @@ void sam_dmainitialize(struct sam_xdmac_s *xdmac)
/* Disable all DMA channels */
sam_putdmac(xdmac, XDMAC_CHAN_ALL, SAM_XDMAC_GD_OFFSET);
/* Initialize mutex & semaphores */
nxmutex_init(&xdmac->chlock);
nxsem_init(&xdmac->dsem, 0, SAM_NDMACHAN);
}
/****************************************************************************

Some files were not shown because too many files have changed in this diff Show More