Commit Graph

1496 Commits

Author SHA1 Message Date
anjiahao
749655d785 tcbinfo:remove total_num form tcbinfo.
total_num is not required
test:

make -f tools/Makefile.host
cp tools/jlink-nuttx /opt/SEGGER/JLink_V786a/libnuttxplugin.so
JLinkGDBServer -if SWD -speed 5000 -device STM32F429ZI -NoGui 1 -rtos libnuttxplugin

can run normally

Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2023-11-21 21:52:24 -08:00
chao an
64cf63475c arch/dumponexit: unify dump on exit to common code
remove arch implement and move to common code

Signed-off-by: chao an <anchao@xiaomi.com>
2023-11-15 08:28:25 -08:00
Eren Terzioglu
4033018a72 xtensa/esp32s3: Add XTWDT support 2023-11-14 19:42:33 -03:00
Eren Terzioglu
d92a7011fd xtensa/esp32s3: Add RWDT support 2023-11-13 21:04:30 -03:00
chenwen@espressif.com
b6e09955dd xtensa/esp32s3: Support multiple PHY init data bin
1. If CONFIG_ESP32S3_PHY_INIT_DATA_IN_PARTITION and CONFIG_ESP32S3_SUPPORT_MULTIPLE_PHY_INIT_DATA are enabled,
PHY initialization data (PHY initialization data is used for RF calibration) will be loaded from a partition.

2. The corresponding PHY init data type can be automatically switched according to the country code,
China's PHY init data bin is used by default, country code can be modified through the wapi command: wapi country <ifname> <country code>.

Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
2023-11-10 15:55:14 -03:00
chenwen@espressif.com
cc10c54f6c xtensa/esp32s3: Support partition and OTA device
Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
2023-11-10 15:55:14 -03:00
Tiago Medicci Serrano
18718316dc esp32/ble: enable the BLE interrupt during a SPI flash operation
This commit sets the BLE's interrupt as a IRAM-enabled interrupt,
which enables it to run during a SPI flash operation. This enables
us to create a cache to off-load semaphores and message queues
operations and treat them when the SPI flash operation is finished.
By doing that, we avoid packet losses during a SPI flash operation.
2023-11-10 09:11:35 +08:00
Tiago Medicci Serrano
f94daf09b2 esp32s3/spiflash: Fix comment and remove unused variable 2023-11-10 09:11:35 +08:00
Tiago Medicci Serrano
b25793ebac esp32/spiflash: Make it similar to ESP32-S3 by removing cache state 2023-11-10 09:11:35 +08:00
Tiago Medicci Serrano
57b8fc9954 esp32/irq: Allow IRAM ISRs to run during SPI flash operation
This commit provides an interface to register ISRs that run from
IRAM and keeps track of the non-IRAM interrupts. It enables, for
instance, to avoid disabling all the interrupts during a SPI flash
operation: IRAM-enabled ISRs are, then, able to run during these
operations.

It also makes the code look more similar to the ESP32-S3 SPI flash
implementation by creating a common `esp32_spiflash_init` that is
responsible to create the SPI flash operation tasks. The function
intended to initialize the SPI flash partions was, then, renamed to
`board_spiflash_init`.
2023-11-10 09:11:35 +08:00
Tiago Medicci Serrano
606190d9b3 esp32/ble: fix saving/restoring the interrupt status flags
Whenever we enter/leave a critical section, the interrupt status is
saved and, then, restored. However, for the ESP32's BLE adapter,
entering/leaving a critical section is done on separate functions
that need to be registered as a callback.

The status flag was being saved as a global variable. However,
calling nested enter_critical_section would overwrite this global
variable that was storing the previous flag and, when leaving the
last critical section, the restored status would be different from
the one expected. The proposed solution for this issue is to create
a global array to store the interrupt status flags for nested calls.
2023-11-10 09:11:35 +08:00
Tiago Medicci Serrano
c60d5c2ea1 esp32s3/wireless: Fix typo
The CPU 2 interrupt source (which is not used for anything else) is
used to off-load BLE data after a SPI flash operation.
2023-11-10 09:11:35 +08:00
Tiago Medicci Serrano
fae075a749 esp32/ble: Lock the scheduler before creating pinned thread
This ensures that the thread that has been just created doesn't
run before its affinity is set, avoiding it to be scheduled in the
wrong CPU core.
2023-11-10 09:11:35 +08:00
Eren Terzioglu
9997a858e2 xtensa/esp32s2: Add SPI slave support 2023-11-10 00:34:39 +08:00
Eren Terzioglu
77df430f30 xtensa/esp32s2: Add rtc heap support 2023-11-09 23:58:30 +08:00
chenwen@espressif.com
5239d01dba xtensa/esp32s3: Disable psram as task stack
1. Disable psram as task stack to avoid system blocking.
2. Add some function comments.
2023-11-08 16:25:57 -03:00
chenwen@espressif.com
8d94c1b3cb xtensa/esp32s3: Support malloc from external RAM and internal RAM
Enables the allocation of the entire Userspace heap into SPI RAM and reserving the Internal RAM exclusively for the Kernel heap.
2023-11-08 16:25:57 -03:00
simbit18
8fa6a29503 Fix Kconfig style
Remove extra TABs
Remove spaces from Kconfig
Add comments
2023-11-08 22:58:26 +08:00
SPRESENSE
f3fabc5d32 Revert "make/archive: Use the full path name when matching or storing names in the archive"
This reverts commit 563125fde3.
2023-10-27 22:26:18 +08:00
Tiago Medicci Serrano
a2be27ef7d espressif: Update esp-hal-3rdparty version
This version includes a bugfix for the NULL definition.
2023-10-26 20:02:13 +08:00
Dong Heng
d4cebae155 xtensa/esp32s3: Support to read data from flash to PSRAM 2023-10-26 08:23:34 -03:00
chao an
2b06142232 kernel: replace all sem_* to nxsem_*: in kernel space
syscall cannot be called from kernel space

Signed-off-by: chao an <anchao@xiaomi.com>
2023-10-25 15:46:03 +08:00
chao an
3cadf6642a kernel: replace all usleep to nxsig_usleep in kernel space
syscall cannot be called from kernel space

Signed-off-by: chao an <anchao@xiaomi.com>
2023-10-25 15:46:03 +08:00
Tiago Medicci Serrano
41c1b153e3 esp32/bluetooth: Select option to pin the HCI TX thread to CPU core
When ESP32's BLE is enabled, select the option to pin the HCI TX
thread to a specific core. This is necessary to avoid problems
with the BLE task that runs pinned to the PRO CPU (core 0) while
running with SMP enabled.
2023-10-24 22:41:44 +08:00
hujun5
061be5f18e refine: move BIT Macro to nuttx/bits.h
The BIT macro is widely used in NuttX,
and to achieve a unified strategy,
we have placed the implementation of the BIT macro
in bits.h to simplify code implementation.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2023-10-12 14:52:56 +08:00
nuttxs
3d6e893215 esp32s3: fix the halt issue when esp32s3 wlan has high-speed
or long time data transmission.

The spin_lock in the wlan_recvframe() function that receives
RX data packets from the wireless network card and the critical
section lock in the iob_remove_queue() processing are nested,
which causes the interrupt to be disabled for a longer period
of time, resulting in a risk of deadlock.
2023-10-12 10:09:20 +08:00
Lee Lup Yuen
6cad7e9582 arm, arm64, xtensa, libxx: Change sed -r to sed -E to support macOS
When we build NuttX on macOS, it shows many `sed` messages (and the build still completes successfully):

```text
$ tools/configure.sh pinephone:nsh
$ make
sed: illegal option -- r
```

This is due to the Makefiles executing `sed -r` which is not a valid option on macOS.

This PR proposes to change `sed -r` to `sed -E` because:

- `sed -E` on macOS is equivalent to `sed -r` on Linux

- `sed -E` and `sed -r` are aliases according to the GNU `sed` Manual

- `sed -E` is already used in nuttx_add_romfs.cmake, nuttx_add_symtab.cmake and process_config.sh
2023-10-10 11:36:32 +03:00
Marco Casaroli
cba44cc9dc fix(esp32s3_i2c): i2c_clear_bus on for I2C_RESET
This function is only used now for I2C_RESET, so we wrap it with the
config macro.
2023-10-09 18:55:04 +03:00
Marco Casaroli
f25a382c1a feat(esp32s3_i2c): do not destuck every transaction
It looks like we do not need to send the 9 clock ticks whenever we reset
the FSM. We are already doing this in i2c_reset function if necessary.

This makes the i2c transfers much faster, for example the i2c(-tool) dev
scan feature.
2023-10-09 18:55:04 +03:00
Marco Casaroli
141dc1e3e7 fix(esp32s3_i2c): set regs order
It looks like we need to set this bit before the UPGATE, like we do on
the esp32c3 port.
2023-10-09 18:55:04 +03:00
Xiang Xiao
dfa0283d83 spinlock: Rename spin_islocked to spin_is_locked
align with Linux naming style

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-10-06 20:03:19 -04:00
Tiago Medicci Serrano
6521bdfa1f esp32s3/ble: fix saving/restoring the interrupt status flags
Whenever we enter/leave a critical section, the interrupt status is
saved and, then, restored. However, for the ESP32-S3's BLE adapter,
entering/leaving a critical section is done on separate functions
that need to be registered as a callback.

The status flag was being saved as a global variable. However,
calling nested enter_critical_section would overwrite this global
variable that was storing the previous flag and, when leaving the
last critical section, the restored status would be different from
the one expected. The proposed solution for this issue is to create
a global array to store the interrupt status flags for nested calls.
2023-10-05 11:25:43 +08:00
Tiago Medicci Serrano
a71a3258b7 esp32s3/ble: enable the BLE interrupt during a SPI flash operation
This commit sets the BLE's interrupt as a IRAM-enabled interrupt,
which enables it to run during a SPI flash operation. This enables
us to create a cache to off-load semaphores and message queues
operations and treat them when the SPI flash operation is finished.
By doing that, we avoid packet losses during a SPI flash operation.
2023-10-05 11:25:43 +08:00
Tiago Medicci Serrano
0ddb64555a esp32s3/irq: Allow IRAM ISRs to run during SPI flash operation
This commit provides an interface to register ISRs that run from
IRAM and keeps track of the non-IRAM interrupts. It enables, for
instance, to avoid disabling all the interrupts during a SPI flash
operation: IRAM-enabled ISRs are, then, able to run during these
operations.
2023-10-05 11:25:43 +08:00
Tiago Medicci Serrano
86b118854e esp32s3/irq: Fix erroneous interrupt allocation for each CPU core
When allocating a CPU interrupt, make sure to select the correct
CPU core to query for it. Simply checking for the current CPU does
not satisfy this requirement because the CPU allocation thread may
be executed by the other core: it's necessary to stick with the
intended CPU passed as an argument of the `esp32s3_setup_irq`.
2023-10-05 11:25:43 +08:00
Tiago Medicci Serrano
2e93882bcf esp32/ble: Fix task_create_wrapper CPU core ID passed as argument
The registered `task_create_wrapper` receives the `core_id`, but
the current implementation ignores this parameter while calling
`esp_task_create_pinned_to_core`. This commit fix this.
2023-10-05 00:37:55 +03:00
Eren Terzioglu
071fb18501 xtensa/esp32s2: add UART RS485 support 2023-10-04 10:18:45 +03:00
Tiago Medicci Serrano
b8b0ae9238 esp32/irq: Fix erroneous interrupt allocation for each CPU core
When allocating a CPU interrupt, make sure to select the correct
CPU core to query for it. Simply checking for the current CPU does
not satisfy this requirement because the CPU allocation thread may
be executed by the other core: it's necessary to stick with the
intended CPU passed as an argument of the `esp32_setup_irq`.
2023-10-03 16:51:49 -04:00
Xiang Xiao
cb11747f36 arch: add use_data to g_tcbinfo
to avoid compiler/linker remove it from the final image

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-09-29 08:00:18 +03:00
Eren Terzioglu
ded321a515 xtensa/esp32s2: Add support to TWAI/CANBus controller 2023-09-28 09:35:08 +08:00
simbit18
4f985f4367 Fix Kconfig style
Remove spaces from Kconfig
Add comments
2023-09-22 00:35:48 +08:00
Roy Feng
d98367693d esp32s3: fix build error 2023-09-20 00:35:28 +08:00
Dong Heng
6ac28d5526 xtensa/esp32s3: LCD controller driver 2023-09-19 11:38:05 +08:00
chao an
5026a96cfa nxstyle: cleanup UTF-8 Unicode to ASCII
Signed-off-by: chao an <anchao@xiaomi.com>
2023-09-18 11:54:17 -04:00
Xiang Xiao
8dbe86084e Remove FAR from source code under 32bit arch and board
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-09-16 19:12:13 +03:00
Petro Karashchenko
c56aa7b527 esp32: use ESP32 specific macro for register values extraction
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2023-09-16 14:17:47 +08:00
Petro Karashchenko
dbc37a0165 nuttx: fix nxstyle issues
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2023-09-16 14:17:47 +08:00
Petro Karashchenko
b0a42f0146 arch/xtensa/esp32: fix return values in BLE adapter
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2023-09-16 14:17:47 +08:00
Petro Karashchenko
816cb3cfaf style: fix multiple style issues and remove unused
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2023-09-16 14:17:47 +08:00
chenwen@espressif.com
827c2df889 xtensa/esp32s3: Fix octal lines mode SPIRAM blocking issue
Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
2023-09-15 20:40:52 +03:00