hostfs has its copies of some of nuttx definitions with different
names to avoid conflicting with the host OS definitions.
sometimes people only modifies one of them and forgets updating
another. eg. https://github.com/apache/nuttx/pull/11445
this commit introduces some assertions to detect that kind of
mistakes.
This is to align with ARCH_KMAP_VBASE by source codes.
It also fixes fake warnings from `tools/refresh.sh`.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
By integrating the Espressif`s HAL repository into the current
ESP32-S2 implementation on NuttX, it is possible to call functions
that makes it easier to setup the registers of the ESP32-S2,
enabling the usage of common Espressif drivers.
By integrating the Espressif`s HAL repository into the current
ESP32-S3 implementation on NuttX, it is possible to call functions
that make it easier to set up the registers of the ESP32-S3 and
enables the usage of common Espressif drivers. Please note that
Espressif's HAL repository was already being used for the Wi-Fi
driver. Then, this commit includes other source files to be used
by other drivers other than Wi-Fi and reorganize the build process.
This lower-half WS2812 LED driver uses the RMT peripheral of the
Espressif's SoCs to drive the RGB addressable LEDs. Compared to
the SPI-based implementation, it is faster!
The lower-half implementation of the RMT character driver based on
Espressif HAL enables using the RMT peripheral of ESP32, ESP32-S2
and ESP32-S3 as a common xtensa-based Espressif driver.
The RMT packages on Espressif SoCs are 4-byte long and are known as
"items". Please check the Techinal Reference Manual of the chip to
obtain more details.
Summary:
- I noticed that qemu-armv8a:netnsh_smp_hv does not detect
GICv2 on Raspi4B (ubuntu 22.04 server + qemu-8.1.2)
- According to the GIC-400 TRM, it says that the architecture
version can be obtained from GICC_IIDR (See Table 3-7)
- This commit fixes this issue.
Impact:
- Should be none
Testing:
- Tested with qemu-armv8a:netnsh_smp_hv on
- Raspi3B+ (ubuntu 22.04 server + qemu-8.1.2)
- Raspi4B (ubuntu 22.04 server + qemu-8.1.2)
- M1/MacBook Pro 2021 (macOS 13.6 + qemu-8.1.2)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
1. Solve wifi may not work bug for bbpll not lock or not stable when enable RF.
2. Improved timing tuning stability on ESP32-S3.
The root cause of the issue:
The application won't re-calibrate the BBPLL clock if it's already enabled.
We add a force-recalib function in the app startup code to make sure even if
the patch is applied by OTA, the clock is still re-calibrated.
Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
since gcc report the false alarm if the pointer offset from zero address:
inlined from 'up_vectormapping' at chip/dm320_boot.c:162:7,
inlined from 'arm_boot' at chip/dm320_boot.c:211:3:
Error: chip/dm320_boot.c:117:17: error: array subscript 0 is outside array bounds of 'uint32_t[0]' {aka 'long unsigned int[]'} [-Werror=array-bounds=]
117 | ctable[index] = (paddr | mmuflags);
| ~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
The opening and closing of the window has been associated with the opening and closing of fb, but the LCD has not yet been optimized. The window will only open when sim_x11openwindow is called, and similarly, the window will only close when sim_x11closewindow is called.
Signed-off-by: jianglianfang <jianglianfang@xiaomi.com>
The code is mainly derived from the NuttX qemu-rv/rv-virt codebase.
Major changes:
- boards/Kconfig: add new BOARD_K230_CANMV
- arch/risc-v/Kconfig: add new CHIP_K230 chip and ARCH_RV_MMIO_BITS
- arch/risc-v/src/common/riscv_mtimer.c: use ARCH_RV_MMIO_BITS to
select MMIO access width
New additions:
- arch/risc-v/include/k230/: k230 SoC definitions
- arch/risc-v/src/k230/: k230 SoC sources
- boards/risc-v/k230/canmv230/: CanMV-K230 board sources and configs
- Documentation/platforms/risc-v/k230/: simple doc
Note that only FLAT build works for canmv230 now.
This PR has changes in RiscV common layer thus may affect other RiscV ports
It changes the mtime/mtimecmp access control from using config ARCH_RV64 to
newly intorduced config ARCH_RV_MMIO_BITS.
Original design uses ARCH_RV64 to select 64bit MMIO in riscv_mtimer.c, this
can't cope with the situation with K230 --- it has ARCH_RV64 but only can do
32bit MMIO. So a new ARCH_RV_MMIO_BITS config has been introduced. Its value
depicts the MMIO width in bits. The MMIO_BITS defaults to 32/64 for RV32/
RV64 respectively. This allows the macro to replace current use of ARCH_RV64
in riscv_mtimer.c.
The new MMIO_BITS config is a derived one, and for RiscV chips with
equal CPU and MMIO widths there is no need to explicitly set it as the
default rule will do that. Only chips with different CPU and MMIO widths
need set it in Kconfig.
So by design this change should be safe but RiscV ports should be checked.
"ostest" verification has been done for:
- canmv230/nsh
- rv-vivt/nsh
- rv-virt/nsh64
configuration generation and manual check of derived RV_MMIO_BITS has been
done for:
- star64/nsh
- arty_a7/nsh
- bl602evb/nsh
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
The `xxx_ipv6multicast` function in each driver is not adapted to
multiple IPv6 addresses yet, and they're redundant, so try to take them
into common code.
Change:
1. Add MAC `g_ipv6_ethallnodes` and `g_ipv6_ethallrouters` in
`icmpv6_devinit` and call them in `netdev_register`
2. Add multicast MAC for Neighbor Solicitation when adding any IPv6
address, and remove them when IPv6 address is removed
3. Select `NET_MCASTGROUP` when `NET_ICMPv6` because now we need
`d_addmac` when we have ICMPv6
Note:
We want modules outside net stack to call functions like
`netdev_ipv6_add` and never touch the related MAC address, so these MAC
functions are added as internal functions to `net/netdev/netdev.h`
Signed-off-by: Zhe Weng <wengzhe@xiaomi.com>
DMA directly to user (virtual) memory won't work, as the DMA engine(s)
don't do address translations, i.e. they require a physical address.
Using kernel heap is fine as it is mapped vaddr=paddr. Also, the USB DMA
engine does not have any alignment requirements.
The hack just opens the entire SoC memory unconditionally, which is not
a good idea.
Test features can be used ad-hoc, they don't need to be supported by the
build.
There is a problem with the current elf loader for risc-v: when a pair of
PCREL_HI20 / LO12 relocations are encountered, it is assumed that these
will follow each other immediately, as follows:
label:
auipc a0, %pcrel_hi(symbol) // R_RISCV_PCREL_HI20
load/store a0, %pcrel_lo(label)(a0) // R_RISCV_PCREL_LO12_I/S
With this assumption, the hi/lo relocations are both done when a hi20
relocation entry is encountered, first to the current instruction (addr)
and to the next instruction (addr + 4).
However, this assumption is wrong. There is nothing in the elf relocation
specification[1] that mandates this. Thus, the hi/lo relocation always
needs to first fixup the hi-part, and when the lo-part is encountered, it
needs to find the corresponding hi relocation entry, via the given "label".
This necessitates (re-)visiting the relocation entries for the current
section as well as looking for "label" in the symbol table.
The NuttX elf loader does not allow such operations to be done in the
machine specific part, so this patch fixes the relocation issue by
introducing an architecture specific cache for the hi20 relocation and
symbol table entries. When a lo12 relocation is encountered, the cache
can be consulted to find the hi20 part.
[1] https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc
The macro LOG2_CEIL is intended to be used in the pre-processor phase. If
used run-time it will generate a massive amount of extra code (~3.5K) which
is a problem, as the PMP configuration is quite often executed from a first
stage bootloader with a limited amount of code memory.
Code size differences pre- and post:
Memory region Used Size Region Size %age Used
envm: 112064 B 112384 B 99.72%
Memory region Used Size Region Size %age Used
envm: 108952 B 112384 B 96.95%
This PR adds support for the Bouffalo Lab BL808 SoC, based on T-Head C906 64-bit RISC-V Core. This will be used by the upcoming port of NuttX for PINE64 Ox64 SBC.
Most of the code was derived from NuttX for Star64 JH7110. The UART Driver was derived from BL602 NuttX. The source files are explained in the articles here: https://github.com/lupyuen/nuttx-ox64
`Kconfig`: Added ARCH_CHIP_BL808 for BL808 SoC
`include/bl808/chip.h`: BL808 Definitions
`include/bl808/irq.h`: External Interrupts
`src/bl808/chip.h`: Interrupt Stack Macro
`src/bl808/bl808_allocateheap.c`: Kernel Heap
`src/bl808/bl808_head.S`: Linux Header and Boot Code
`src/bl808/bl808_irq.c`: Configure Interrupts
`src/bl808/bl808_irq_dispatch.c`: Dispatch Interrupts
`src/bl808/bl808_memorymap.h`: Memory Map
`src/bl808/bl808_mm_init.c`, `bl808_mm_init.h`: Memory Mgmt
`src/bl808/bl808_pgalloc.c`: Page Allocator
`src/bl808/bl808_serial.c`, `bl808_serial.h`: UART Driver
`src/bl808/bl808_start.c`: Startup Code
`src/bl808/bl808_timerisr.c`: Timer Interrupt
`src/bl808/hardware/bl808_memorymap.h`: PLIC and UART Base Address
`src/bl808/hardware/bl808_plic.h`: PLIC Register Addresses
`src/bl808/hardware/bl808_uart.h`: UART Register Addresses
`src/bl808/Kconfig`: BL808 Config
`src/bl808/Make.defs`: Makefile
Currently RISC-V NuttX supports 32-bit MMU Flags inside a Page Table Entry. This PR extends the MMU Flags to 64-bit, to support T-Head C906 Core and the new RISC-V Svpbmt Extension.
T-Head C906 uses Bits 59 to 63 in a Leaf Page Table Entry to configure the Memory Type: Cacheable / Bufferable / Strongly-Ordered. For the upcoming port of NuttX to PINE64 Ox64 BL808 SBC, we need to set the Memory Type to Strongly-Ordered for I/O Memory, which requires 64-bit MMU Flags.
Details of C906 MMU: https://lupyuen.github.io/articles/plic3#t-head-errata
Newer RISC-V Cores will use the Svpbmt Extension to configure the Memory Type (Cacheable / Strongly-Ordered). Svpbmt uses Bits 61 to 62 in a Leaf Page Table Entry to define the Memory Type. This also requires 64-bit MMU Flags.
Details of Svpbmt: https://github.com/riscv/riscv-isa-manual/blob/main/src/supervisor.adoc#svpbmt
Usage:
1. CONFIG_FS_PROCFS_MAX_STACK_RECORD > 0, such as 32,
2. add '-finstrument-functions' to CFLAGS for What you want to check
stack.
3. mount porcfs
4. cat /proc/<pid>/stack will print backtace & size
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
Add registration function instrumentation API,
which can achieve instrumentation of entering and
exiting functions through the compiler's functionality.
We can use CONFIG_ARCH_INSTRUMENT_ALL to add instrumentation for all
source, or add '-finstrument-functions' to CFLAGS for Part of the
source.
Notice:
1. use CONFIG_ARCH_INSTRUMENT_ALL must mark _start or entry noinstrument_function,
becuase bss not set.
2. Make sure your callbacks are not instrumented recursively.
use instrument_register to register entry function and exit function.
They will be called by the instrumented function
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
