The motvations is to version the IP blocks of the Kinetis
K series family of parts.
This added versioning and configuration features for the
Kinetis PMC IP block.
It is envisioned that in the long term as a chip is added.
The author of the new chip definitions will either find
the exact configuration in an existing chip define and
add the new chip to it Or add the PMC fature configuration
#defines to the chip ifdef list in
arch/arm/include/kinetis/kinetis_pmc.h In either case the
author should mark it as "Verified to Document Number:"
taken from the reference manual.
The version KINETIS_PMC_VERSION_UKN has been applied to
most all the SoCs in the kinetis arch prior to this commit.
The exceptions are the CONFIG_ARCH_CHIP_MK60FN1M0VLQ12,
CONFIG_ARCH_CHIP_MK20DXxxxVLH7 All K64 and K66 have ben
Verified PMC configurations.
The motvations is to version the IP blocks of the Kinetis
K series family of parts.
This added versioning and configuration features for the
Kinetis SIM IP block.
It is envisioned that in the long term as a chip is added.
The author of the new chip definitions will either find
the exact configuration in an existing chip define and
add the new chip to it Or add the SIM feature configuration
#defines to the chip ifdef list in
arch/arm/include/kinetis/kinetis_sim.h In either case the
author should mark it as "Verified to Document Number:"
taken from the reference manual.
The version KINETIS_SIM_VERSION_UKN has been applied to
most all the SoCs in the kinetis arch prior to this commit.
The exceptions are the CONFIG_ARCH_CHIP_MK60FN1M0VLQ12,
All K64 and K66 which not have Verified SIM configurations.
The K whole family line has max 4 or each. But the supported
parts have the maximums listed below:
K46 and K66 3 SPI SPI0-SPI2
K46 and K66 4 I2C I2C0-I2C3
The "mcr CP15_BPIALLIS(r0)" instruction is used for invalidating entire branch predictor. But the problem is, since this is the generic code and can be called on any armv7-r architecture based CPU's. It is a problem, if this instruction is called in uni processor configuration. Because, BPIALLIS (c7, 0, c1, 6) instruction is only added as part of the "Multiprocessing Extensions" (As per ARM® Architecture Reference Manual /ARMv7-A and ARMv7-R edition)
So in my opinion, this instruction should be under SMP configuration. In non-SMP configuration this instruction could become undefined.
