Gustavo Henrique Nihei
1967805b91
risc-v: Fix format specifier in debug log
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Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-04-28 01:18:46 +08:00
chao.an
042640abbf
arch/arm: add support for GCC LTO
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1. Enable GCC link-time optimizer
2. Enable use of a linker plugin during link-time optimization
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-04-27 23:42:54 +08:00
chao.an
cbef8681fe
arch/risc-v: add support for GCC LTO
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Signed-off-by: chao.an <anchao@xiaomi.com>
2022-04-27 23:42:37 +08:00
Ville Juven
216574bba8
OpenSBI: Add riscv_hardfp.S to compilation
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It will just become an empty object if FPU support is not included.
2022-04-27 23:20:51 +08:00
dytang
d7cc3f9275
RISC-V: workaround for the RV64 SoC which does not has mem mapped MTIMER currten value regs.
2022-04-27 22:48:54 +08:00
Abdelatif Guettouche
98d8d2a1ff
arch/xtensa: Group all the macros in one file.
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Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-04-27 08:57:53 -03:00
Abdelatif Guettouche
541eabb535
xtensa_int_handlers.S: Refactor the calls to ps_setup.
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Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-04-27 08:57:53 -03:00
chao.an
db54b0b836
arm/assert: fix build warning on clang
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common/arm_assert.c:80:14: warning: format specifies type 'unsigned int' but the argument has type 'uint32_t' (aka 'unsigned long') [-Wformat]
stack, ptr[0], ptr[1], ptr[2], ptr[3],
^~~~~
include/debug.h:119:59: note: expanded from macro '_alert'
__arch_syslog(LOG_EMERG, EXTRA_FMT format EXTRA_ARG, ##__VA_ARGS__)
~~~~~~ ^~~~~~~~~~~
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-04-27 14:18:42 +08:00
Abdelatif Guettouche
587145a881
riscv/Makefile: Delete old target used for debugging.
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Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-04-27 12:58:57 +08:00
Xiang Xiao
fc16cfaefe
Correct the code alignment found in review
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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-26 11:34:28 +03:00
Abdelatif Guettouche
aaa5316235
arch/xtensa: Simply use xtensa_createstack for CPU1 idle task.
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Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-04-26 01:36:54 +08:00
Ville Juven
6546789b7e
RISC-V: Add syscall support for vfork
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If vfork is called via syscall (PROTECTED/KERNEL build) need to set up
return parameters for syscall. Otherwise the SW will get lost.
2022-04-25 16:23:17 +03:00
Xiang Xiao
8f8ee25a9c
boards: Move -g from Make.defs to Toolchain.defs
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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-25 16:23:03 +03:00
Xiang Xiao
e9f5eb0823
boards: Move "-fno-exceptions -fcheck-new" from Make.defs to Toolchain.defs
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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-25 16:22:46 +03:00
Ville Juven
a014daf44f
RISC-V: Add implementation for vfork
2022-04-25 15:44:32 +08:00
Ville Juven
2580520828
RISC-V: Fix system crash when FPU is in use
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FPU registers need to be written prior to updating CSR_STATUS
2022-04-25 15:44:06 +08:00
Xiang Xiao
75326e563d
boards: Move -fno-common from Make.defs to Toolchain.defs
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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-25 07:57:29 +03:00
Abdelatif Guettouche
3942f4d133
arch/xtensa: No need to save SP in EXCSAVE_1 when linking the interrupt
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frame with the previous frame. The SP is already saved in A12.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-04-23 10:19:23 +08:00
Abdelatif Guettouche
f130d8c143
xtensa_user_handler.S: Fix backtrace.
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Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-04-23 10:19:23 +08:00
Abdelatif Guettouche
7a3ad4b224
xtensa_user_handler.S: Use the ps_setup
macro when dealing with an
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exception.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-04-23 10:19:23 +08:00
Xiang Xiao
5a565e753c
pm: Move pm_initialize call from driver_initialize to xxx_pminitialize
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since it's too late with the below commit:
ommit a594a5d7a8
Author: chao.an <anchao@xiaomi.com>
Date: Mon Apr 11 19:44:26 2022 +0800
sched/init: drivers_initialize() should be late than up_initialize()
up_initialize
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->up_serialinit
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->uart_register /* ("/dev/console", &CONSOLE_DEV); */
drivers_initialize
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->syslog_console_init
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->register_driver /* ("/dev/console", &g_consoleops, 0666, NULL); */
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-22 14:36:27 +03:00
Masayuki Ishikawa
04f81ecddb
arch: risc-v: Do not enable FPU for K210 with QEMU
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Summary:
- I noticed that maix-bit:smp does not work with QEMU.
- Actually, QEMU supports sifive_u (not K210) but it works
if FPU is disabled.
- This commit fixes this issue.
Impact:
- K210 with QEMU only
Testing:
- Tested with qemu-5.2
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-04-22 14:52:04 +08:00
Huang Qi
06c7a3ca59
arch/risc-v/riscv_misaligned: Implement float load/store support
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Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-04-22 12:23:10 +08:00
Huang Qi
be95e76910
arch/risc-v: Enable FPU for K210
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K210 support rv64gc ISA, now we enable F/D extension for it.
Note: QEMU for K210 don't support FPU now.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-04-21 21:47:29 +03:00
chao.an
1c8e12406e
compile/opt: add config DEBUG_LINK_MAP
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Selecting this option will pass "-Map=$(TOPDIR)$(DELIM)nuttx.map" to ld
when linking NuttX ELF. That file can be useful for verifying
and debugging magic section games, and for seeing which
pieces of code get eliminated with DEBUG_OPT_UNUSED_SECTIONS.
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-04-22 01:37:23 +08:00
chao.an
64d7326ed5
compile/opt: add config DEBUG_OPT_UNUSED_SECTIONS
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Enable this option to optimization the unused input sections with the
linker by compiling with " -ffunction-sections -fdata-sections ", and
linking with " --gc-sections ".
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-04-22 01:37:23 +08:00
Abdelatif Guettouche
56ecd44f63
arch/xtensa: Color the other CPUs task when they are created.
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Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-04-22 01:12:55 +08:00
Xiang Xiao
1320e5add4
arch/arm: Move the duplicated assembly code to common folder
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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-21 12:56:34 +03:00
Xiang Xiao
ebf1093cff
arch/arm: Switch the context of save and restore from assembler to c
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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-21 12:56:34 +03:00
Huang Qi
0332b78f99
arch/risc-v: Don't clear reserved bits in fcsr in riscv_fpuconfig
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Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-04-21 15:26:05 +08:00
chao.an
875c5dac75
arm/armv[7|8]m: compare of hardware fp registers should skip REG_FP_RESERVED
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Fix fpu test break
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-04-21 14:55:54 +09:00
Abdelatif Guettouche
64e4c9ca02
arch/xtensa: Move xtensa_save_context to up_saveusercontext for
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consistency with other archs.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-04-21 01:59:34 +08:00
Abdelatif Guettouche
6db910a1aa
arch/xtensa: Use syscall interface for xtensa_save/restore_context.
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Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-04-21 01:59:34 +08:00
chao.an
0315283c21
arch/clang: add support for Clang LTO
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add support of Clang's Link Time Optimization (LTO) on NuttX build system
Reference:
https://gcc.gnu.org/onlinedocs/gccint/LTO-Overview.html
https://llvm.org/docs/LinkTimeOptimization.html
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-04-21 01:21:54 +08:00
chao.an
67fbfda974
arch/armv6-m: add support of LLVM Clang
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Signed-off-by: chao.an <anchao@xiaomi.com>
2022-04-21 01:21:54 +08:00
Huang Qi
48b81bda09
arch/risc-v: Change riscv_savefpu/riscv_loadfpu to macro
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Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-04-20 16:08:17 +03:00
Alin Jerpelea
dda675779a
arch: arm: mor1kx: remove empty files
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during contribution empty files have been pushed.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2022-04-20 21:05:45 +08:00
Alin Jerpelea
af98967439
arch: arm: stm32l4: remove empty files
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during contribution empty files have been pushed.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2022-04-20 21:05:45 +08:00
Alin Jerpelea
73cd86dad7
arch: arm: phy62xx: Add Apache license to files
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In the initial contribution those files were missing the license
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2022-04-20 21:05:45 +08:00
Alin Jerpelea
22ceda26bb
arch: arm: lpc43xx: Add Apache license to files
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In the initial contribution those files were missing the license
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2022-04-20 21:05:45 +08:00
Alin Jerpelea
4e19a97916
arch: arm: imxrt: Add Apache license to files
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In the initial contribution those files were missing the license
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2022-04-20 21:05:45 +08:00
Alin Jerpelea
208b892efe
arch: arm: cxd56xx: Add Apache license to files
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In the initial contribution those files were missing the license
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2022-04-20 21:05:45 +08:00
Huang Qi
95ab7b973b
arch/sparc,xtensa: Control output by $(Q) as other arch
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Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-04-20 12:04:17 +02:00
zhuyanlin
8d756a75a2
armv7/r:cp15_cache_all: fix error in LineSize 'r5' mask
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r5 = r3 & r1
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-04-20 08:06:58 +09:00
chao.an
fc3565e9eb
arch/z80: Unify the toolchain definition of SDCC for linux and windows
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Signed-off-by: chao.an <anchao@xiaomi.com>
2022-04-19 23:17:27 +08:00
chao.an
0cf8088406
arch/misoc: Unify the toolchain definition of GNU for linux and windows
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Signed-off-by: chao.an <anchao@xiaomi.com>
2022-04-19 23:17:27 +08:00
chao.an
e066d5d1e0
arch/risc-v: Unify the toolchain definition of RVG for linux and windows
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Signed-off-by: chao.an <anchao@xiaomi.com>
2022-04-19 23:17:27 +08:00
chao.an
2df591b3bb
arch/armv7-a/r: Unify the toolchain definition of eabi for linux and windows
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Signed-off-by: chao.an <anchao@xiaomi.com>
2022-04-19 23:17:27 +08:00
chao.an
4a085e1cdb
arch/arm/armv6-m: Unify the toolchain definition of eabi for linux and windows
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Signed-off-by: chao.an <anchao@xiaomi.com>
2022-04-19 23:17:27 +08:00
chao.an
2246afcdd8
arch/armv7-m: Unify the toolchain definition of eabi/clang/iar for linux and windows
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Signed-off-by: chao.an <anchao@xiaomi.com>
2022-04-19 23:17:27 +08:00