riscv_mhartid is no longer called by exception_common, so can remove
this file from platforms that don't need it.
Also fixes make warning:
Makefile:123: target 'riscv_cpuindex.o' given more than once in the same rule
IRQ_NSTACKS, ARCH_CPU_COUNT, CONFIG_SMP_NCPUS all relate to each
other. However, a bit of clean up can be done and everything can
be merged into SMP_NCPUS.
The MPFS bootloader case works also as it requires only 1 IRQ stack
for the hart that executes as bootloader.
malloc() should return aligned (with MM_MIN_CHUNK) pointer, but
pr #5906 destroy that, this pr find a better method to solve
these questions.
Signed-off-by: YAMAMOTO Takashi <yamamoto@midokura.com>
and
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
functionality. In function "wm8904_hw_reset" the priv->balance
is initialized with b16HALF, indicating a range from
0 to b16ONE. In function "wm8904_setvolume" the assumed
range for priv->balance is between 0 and 1000. The changes
now make this consistent for 0 to b16ONE-1. Furthermore,
in wm8904_configure the change of balance was not implemented.
Some risc-v based chips don't support unaligned data access,
it will trigger a exception and then lead to crash.
In this patch, we handle the misaligned access by software to make
system run continue.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
pthread_join need check thread is DETACHED,
Whether to wait according to the result.And,
if a thread is DETACHED,it will not set a new
attr.
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
CONFIG_LIBM option may be required by some toolchains that do not include
standard math library. Morover CONFIG_PTHREAD_STACK_MIN was listed twice
in the list.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
ESP32C3 use customized irq encoding so it's hard to share further code
with other risc-v based chips, in this patch, we keep the exception
number definition with risc-v spec.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
- Access to PLIC via S-mode registers
- Access to IRQs via S-mode registers / definitions
- Initialize S-mode registers upon boot
- Initialize per CPU area before nx_start
NOTE: S-mode requires a companion SW (SBI) which is not yet implemented,
thus S-mode is not usable as is, yet.
complete the following commits:
commit d87cf8d4ca
Author: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
Date: Fri Apr 1 20:59:55 2022 +0800
fs/poll: change format for type pollevent_t
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
commit d535943a69
Author: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
Date: Fri Apr 1 17:49:10 2022 +0800
fs/epoll: change type of eventset from uint8_t to uint32_t
to support EPOLLONESHOT and so on.
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
Signed-off-by: chao.an <anchao@xiaomi.com>
