Commit Graph

1168 Commits

Author SHA1 Message Date
hujun5
35b597ec2c arch/all: in smp pthread_cancel occasionally deadlock except for arm64
please reference the issue here for more information:
https://github.com/apache/nuttx/pull/9065

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2023-05-23 15:48:35 +09:00
Xiang Xiao
7990f90915 Indent the define statement by two spaces
follow the code style convention

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-05-21 09:52:08 -03:00
Xiang Xiao
7dc0d70092 arch: Save sigdeliver into xcp in the case of signal self delevery
to avoid the infinite recusive dispatch:
*0  myhandler (signo=27, info=0xf3e38b9c, context=0x0) at ltp/testcases/open_posix_testsuite/conformance/interfaces/sigqueue/7-1.c:39
*1  0x58f1c39e in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:167
*2  0x58fa0664 in up_schedule_sigaction (tcb=0xf4e20f40, sigdeliver=0x58f1bab5 <nxsig_deliver>) at sim/sim_schedulesigaction.c:88
*3  0x58f19907 in nxsig_queue_action (stcb=0xf4e20f40, info=0xf4049334) at signal/sig_dispatch.c:115
*4  0x58f1b089 in nxsig_tcbdispatch (stcb=0xf4e20f40, info=0xf4049334) at signal/sig_dispatch.c:435
*5  0x58f31853 in nxsig_unmask_pendingsignal () at signal/sig_unmaskpendingsignal.c:104
*6  0x58f1ca09 in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:199
*7  0x58fa0664 in up_schedule_sigaction (tcb=0xf4e20f40, sigdeliver=0x58f1bab5 <nxsig_deliver>) at sim/sim_schedulesigaction.c:88
*8  0x58f19907 in nxsig_queue_action (stcb=0xf4e20f40, info=0xf4049304) at signal/sig_dispatch.c:115
*9  0x58f1b089 in nxsig_tcbdispatch (stcb=0xf4e20f40, info=0xf4049304) at signal/sig_dispatch.c:435
*10 0x58f31853 in nxsig_unmask_pendingsignal () at signal/sig_unmaskpendingsignal.c:104
*11 0x58f1ca09 in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:199
*12 0x58fa0664 in up_schedule_sigaction (tcb=0xf4e20f40, sigdeliver=0x58f1bab5 <nxsig_deliver>) at sim/sim_schedulesigaction.c:88
*13 0x58f19907 in nxsig_queue_action (stcb=0xf4e20f40, info=0xf40492d4) at signal/sig_dispatch.c:115
*14 0x58f1b089 in nxsig_tcbdispatch (stcb=0xf4e20f40, info=0xf40492d4) at signal/sig_dispatch.c:435
*15 0x58f31853 in nxsig_unmask_pendingsignal () at signal/sig_unmaskpendingsignal.c:104
*16 0x58f1ca09 in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:199
*17 0x58fa0664 in up_schedule_sigaction (tcb=0xf4e20f40, sigdeliver=0x58f1bab5 <nxsig_deliver>) at sim/sim_schedulesigaction.c:88
*18 0x58f19907 in nxsig_queue_action (stcb=0xf4e20f40, info=0xf40492a4) at signal/sig_dispatch.c:115
*19 0x58f1b089 in nxsig_tcbdispatch (stcb=0xf4e20f40, info=0xf40492a4) at signal/sig_dispatch.c:435
*20 0x58f31853 in nxsig_unmask_pendingsignal () at signal/sig_unmaskpendingsignal.c:104
*21 0x58f1ca09 in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:199
*22 0x58fa0664 in up_schedule_sigaction (tcb=0xf4e20f40, sigdeliver=0x58f1bab5 <nxsig_deliver>) at sim/sim_schedulesigaction.c:88
*23 0x58f19907 in nxsig_queue_action (stcb=0xf4e20f40, info=0xf4049274) at signal/sig_dispatch.c:115
*24 0x58f1b089 in nxsig_tcbdispatch (stcb=0xf4e20f40, info=0xf4049274) at signal/sig_dispatch.c:435
*25 0x58f31853 in nxsig_unmask_pendingsignal () at signal/sig_unmaskpendingsignal.c:104
*26 0x58f1ca09 in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:199
*27 0x58fa0664 in up_schedule_sigaction (tcb=0xf4e20f40, sigdeliver=0x58f1bab5 <nxsig_deliver>) at sim/sim_schedulesigaction.c:88
*28 0x58f19907 in nxsig_queue_action (stcb=0xf4e20f40, info=0xf4049244) at signal/sig_dispatch.c:115
*29 0x58f1b089 in nxsig_tcbdispatch (stcb=0xf4e20f40, info=0xf4049244) at signal/sig_dispatch.c:435
*30 0x58f31853 in nxsig_unmask_pendingsignal () at signal/sig_unmaskpendingsignal.c:104
*31 0x58f1ca09 in nxsig_deliver (stcb=0xf4e20f40) at signal/sig_deliver.c:199

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-05-17 11:53:18 -06:00
Xiang Xiao
7a8cf7ff70 Indent the include statement by two spaces
follow the coding style

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-05-16 12:34:32 -03:00
Ville Juven
a940ea0134 riscv/riscv_copystate.c: Remove riscv_copystate.c as it is not used anymore
I keep getting confused by this function until I remember again that it is
not used any more. Let's just get rid of it.
2023-05-15 19:35:18 +08:00
Ville Juven
aee45c9c43 riscv/addrenv: Create utility function for dynamic mappings
Move the mapping functionality from up_shmat/shmdt into two generic
mapping functions. This makes it possible to do other mappings besides
user shared memory area mappings.
2023-05-12 22:32:31 +08:00
Alan Carvalho de Assis
694e6f550b esp32xx: Workaround to avoid printing serial trash character
During the serial reconfiguration from bootloader to the
NuttX a trash character "?" (Unicode replacement U+FFFD)
was printed in the screen.

This fix was discovered by Sylvio Alves from Espressif!
2023-05-12 06:30:35 +03:00
Tiago Medicci Serrano
e8e50900d0 esp32c3/wifi: use wapis init config to save Wi-Fi data
Instead of using Espressif's emulated NVS to save Wi-Fi data, use
`wapi`s wireless configure initialization mechanism for saving
Wi-Fi data. It 1) avoids creating a specific storage partition
just to save Wi-Fi data (ESP32-C3's storage partition is used
instead); 2) avoids initialization problems of the emulated NVS
when SMP is enabled (the Wi-Fi driver tries to initialize it before
the actual partition is initialized); and 3) enables reconnecting
using `wapi reconnect` command and connect the device automatically
on bringup if `CONFIG_NETUTILS_NETINIT` is selected.
2023-05-12 01:09:09 +08:00
simbit18
53d0d04e8e arch/risc-v/src/esp32c6/Kconfig: Fix help attribute
Replace help => ---help---
2023-05-10 22:51:11 +08:00
simbit18
e01a46c8c3 arch/risc-v/src/qemu-rv/Kconfig: Fix indentation
Remove spaces from Kconfig
Add TABs
2023-05-10 00:45:29 +08:00
simbit18
4452ee0743 arch/risc-v/src/mpfs/Kconfig: Fix indentation
Remove spaces from Kconfig
Add TABs
2023-05-10 00:45:29 +08:00
simbit18
94aff9f937 arch/risc-v/src/mpfs/kconfig: Fix indentation
Remove spaces from Kconfig
Add TABs
2023-05-08 12:42:54 -03:00
Ville Juven
22d6f97843 mpfs/mpfs_spi.c: Fix some logic errors in the driver
- putreg32() is used the wrong way around (reg, val) instead of (val, reg)
- MPFS_SPI_FRAMESIZE is not a register, FSIZE is the name
- Clear all interrupts _before_ writing the FIFO, this prevents a race
  condition where a short transmission completes before the interrupt is
  enabled.
2023-05-08 11:49:30 -03:00
Xiang Xiao
6f6fce95a2 Replace all sprintf with snprintf
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-05-08 09:57:01 +02:00
hujun5
0f243bde33 arch: fix the issue of asynchronous signal processing
in SMP, signal processing cannot be nested, we use xcp.sigdeliver to identify whether there is currently a signal being processed, but this state does not match the actual situation
One possible scenario is that signal processing has already been completed, but an interrupt occurs, resulting in xcp.sigdeliver not being correctly set to NULL,
At this point, a new signal arrives, which can only be placed in the queue and cannot be processed immediately
Our solution is that signal processing and signal complete status are set in the same critical section, which can ensure status synchronization

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2023-05-08 09:11:14 +02:00
zhangyuan21
841b178782 assert: show stacks with the sp from regs
1. Get the value of sp from dump regs when an exception occurs,
   to avoid getting the value of fp from up_getsp and causing
   incomplete stack printing.
2. Determine which stack the value belongs to based on the value
   of SP to avoid false reports of stack overflow

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-05-05 13:40:04 +08:00
Stuart Ianna
dec80be431 arch/risc-v/litex: Fix emac driver compilation when only IPv6 is used. 2023-05-05 11:53:13 +08:00
zhangyuan21
884be2bdb9 assert: Distinguish between assert and exception
CURRENT_REGS may change during assert handling, so pass
in the 'regs' parameter at the entry point of _assert.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-05-03 14:49:32 +08:00
Ville Juven
7184d1f5f9 arch/risc-v: Fix save/load FPU macros
The macros destroy t0, t1, t2 when used, make them explicitly restore them
so they are safe to use from where-ever
2023-04-28 00:54:39 +08:00
zhangyuan21
89ae45be18 arch/risc-v: change up_saveusercontext to assembly code
minidump will backtrace failure when use C code to save user context,
because the stack push operation in C code can disrupt the stack information.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-27 17:34:30 +08:00
Radek Pesina
a0e2f29bdf Add option for selecting coherent DMA. 2023-04-27 16:41:00 +08:00
Radek Pesina
50a8ec62c4 Add eMMC driver support
- Fix DMA addressing issues within litex_sendsetup/litex_recvsetup
- Extend with handling specific to eMMC commands during init & use.
- Cleanup of 4-bit BUS handling for SD and eMMC
- For eMMC, Send CMD0 during init as per JEDEC v4.41 for pre-idle
2023-04-26 00:34:36 -04:00
Ville Juven
d48114a4b7 sched/addrenv.c: Implement re-entrancy for addrenv_select()
Store the old environment in a local context so another temporary address
environment can be selected. This can happen especially when a process
is being loaded (the new process's mappings are temporarily instantiated)
and and interrupt occurs.
2023-04-25 14:33:19 +02:00
Ville Juven
20623d7369 sem/sem_init: Change sem_xxx -> nxsem_xxx in kernel modules
Use the kernel space api nxsem_xxx when inside the kernel.
2023-04-25 13:41:51 +02:00
Petro Karashchenko
d50ec662be arch/risc-v/esp32c3: Change the linker generated symbols from uint32_t to uint8_t *
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2023-04-24 09:35:58 -07:00
Stuart Ianna
4cae98674d litex: Support for kernel build with vexriscv-smp. 2023-04-22 01:40:32 +08:00
Ville Juven
b982c1747b sched/addrenv: Miscellaneous clean-up and fixes
- Remove the temporary "saved" variable when temporarily changing MMU
  mappings to access another process's memory. The fact that it has an
  address environment is enough to make the choice
- Restore nxflat_addrenv_restore-macro. It was accidentally lost when
  the address environment handling was re-factored.
2023-04-15 13:21:48 +09:00
wangming9
a7fc26124d arch/arm64: the arm64 perf interface supports pmu
Summary:
- Support arm64 pmu api, Currently only the cycle counter function is supported.
- Using ARM64 PMU hardware capability to implement perf interface, modify all
  perf interface related code.
- Support for pmu init under smp.

Signed-off-by: wangming9 <wangming9@xiaomi.com>
2023-04-10 16:23:49 -03:00
Gustavo Henrique Nihei
8e83379b84 risc-v/espressif: Initialize HR Timer where it is required
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-04-07 12:27:56 -03:00
Gustavo Henrique Nihei
ebe4ab8894 risc-v/espressif: Add support for RTC subsystem
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-04-07 12:27:56 -03:00
Gustavo Henrique Nihei
38861f6154 risc-v/espressif: Use spinlock APIs for defining critical sections
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-04-06 14:35:36 -03:00
Gustavo Henrique Nihei
ac746fd87f risc-v/espressif: Add support for Tickless mode
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-04-06 19:29:23 +03:00
Masayuki Ishikawa
5e7d48f4b0 arch: k210: Fix k210 timer on QEMU 6.1 or later
Summary:
- I noticed that 'sleep 1' on nsh took 10 seconds on QEMU-6.1,
  though the old version (e.g. QEMU-5.2) works correctly.
- I think we should implement PLL for the QEMU environment.
  However, this fix works as a tentative solution.

Impact:
- K210 on QEMU only

Tested
- Tested with QEMU-7.1

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2023-04-06 00:54:08 -07:00
Gustavo Henrique Nihei
8be8aab9bb risc-v/espressif: Panic if CPU interrupt allocation fails
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-04-05 16:52:07 -03:00
Gustavo Henrique Nihei
7aecd751f0 risc-v/espressif: Add support for Oneshot Timer
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-04-05 16:51:34 -03:00
Gustavo Henrique Nihei
31d68f2dd3 risc-v/espressif: Add support for Periodic Timers
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-04-05 16:51:34 -03:00
Huang Qi
7f27129896 tools: Move Rust relative settings to Rust.defs
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2023-04-01 16:45:11 +03:00
Gustavo Henrique Nihei
ffef83c9a1 risc-v/espressif: Add High Resolution Timer driver
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-04-01 10:40:04 -03:00
Huang Qi
5d4e4b1919 tools/riscv: Map extensions to certain cpu model for LLVM based toolchain
RISCV has a modular instruction set. It's hard to define cpu-model to support all toolchain.
For Zig, cpu model is this formal: generic_rv[32|64][i][m][a][f][d][c]
For Rust, cpu model is this formal: riscv[32|64][i][m][a][f][d][c]
So, it's better to map the NuttX config to LLVM builtin cpu model, these models supported by
all LLVM based toolchain.
Refer to : https://github.com/llvm/llvm-project/blob/release/15.x/llvm/lib/Target/RISCV/RISCV.td
These models can't cover all implementation of RISCV, but it's enough for most cases.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2023-03-31 16:55:15 -03:00
Gustavo Henrique Nihei
5081cef2c9 risc-v/espressif: Add Hardware RNG support
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-03-31 22:01:39 +03:00
Gustavo Henrique Nihei
cf90fa62b2 risc-v/espressif: Add support for System Reset
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-03-31 22:00:17 +03:00
Gustavo Henrique Nihei
c1efa8c85a risc-v/espressif: Fix include path for brownout.h
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-03-31 22:00:17 +03:00
Ville Juven
fc44cbdbdb arch/risc-v: Set Supervisor User Memory (access) for idle process too
This has been a long issue for me as it results in random crashes when
asynchronous events occur when the idle process is active.

The problem is that the kernel cannot access user memory, because the CPU
status prevents it.
2023-03-29 10:53:09 -03:00
Stuart Ianna
01b0305ab5 risc-v: SV32 MMU support for qemu-rv. 2023-03-29 22:15:19 +09:00
Huang Qi
536739d2da tools: Export LLVM style arch info for non-c language
Current Toolchain.defs set the compile flags directly, it's OK for
target specified gcc toolchain.

But some LLVM based toolchains (Rust/Zig etc) use single toolchain to handle all supported paltform.

In this patch, arch level Toolchain.defs export standard LLVM style arch flags, and let <Lang>.defs to map them into internal style,

This will simplify the intergration of non-c language.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2023-03-29 09:26:38 -03:00
Gustavo Henrique Nihei
f462be5365 risc-v/espressif: Fix NULL-dereferencing in WDT interrupt handling
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-03-28 22:39:00 +03:00
Gustavo Henrique Nihei
6647f194db risc-v/espressif: Update revision of esp-hal-3rdparty
Small cleanup, no added features.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-03-28 14:43:40 -03:00
Xiang Xiao
bc3e6c84e1 arch: Rename up_[early]serialinit to [arm64|riscv|x86_64][early]serialinit
The naming standard at:
https://cwiki.apache.org/confluence/display/NUTTX/Naming+of+Architecture%2C+MCU%2C+and+Board+Interfaces
requires that all MCU-private function begin with the name of the architecture, not up_.

follow the change from: https://github.com/apache/nuttx/pull/930

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-03-27 12:35:04 +03:00
chao an
0eae218b49 arm/chip/sdio/muxbus: comment all undefined symbols
comment all undefined symbols to avoid build break if CONFIG_SDIO_MUXBUS enabled

Signed-off-by: chao an <anchao@xiaomi.com>
2023-03-26 13:04:48 -03:00
Xiang Xiao
901cd599b1 arch: Remove MIN macro definition
use the definition from sys/param.h instead

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-03-22 17:26:37 -03:00