Huang Qi
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9284770f75
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arch/risc-v: Move epc adjustment to riscv_doirq
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
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2022-04-10 00:52:04 +08:00 |
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Xiang Xiao
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3a26cf6a02
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arch/risc-v: Remove the unnecessary inclusion of board header files
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
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2022-04-07 11:25:12 +03:00 |
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Huang Qi
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32fe25278a
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arch/risc-v: Merge duplicated logic by riscv_doirq
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
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2022-03-31 19:33:08 +08:00 |
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Petro Karashchenko
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7afedda89e
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arch/risc-v: improve style consistency accross chip variants
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
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2022-03-25 10:26:15 -03:00 |
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Xiang Xiao
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54e630e14d
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arch: Merge up_arch.h into up_internal.h
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
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2022-03-14 09:32:17 +02:00 |
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Huang Qi
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6dc4dd207f
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arch/risc-v: Remove dupped irq code from rv32m1
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
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2022-01-21 00:44:43 +08:00 |
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Huang Qi
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10bb48b9b4
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arch/risc-v: Merge rv32im and rv64gc into common
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
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2022-01-11 23:24:33 +08:00 |
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Huang Qi
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33df35f003
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arch/risc-v: Correct epc adjustment with C ISA
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
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2021-12-30 22:54:17 +09:00 |
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unixjet
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68f19a6290
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risc-v/rv32m1: Basic port to rv32m1 ri5cy
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2021-06-05 17:25:57 -03:00 |
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